Evaluation Board CS5321 CS5322 CDB5321 evaluation board that allo

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Evaluation Board CS5321 CS5322 CDB5321 evaluation board that allo

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CDB5321
Evaluation Board CS5321 CS5322
CDB5321 evaluation board that allows laboratory characterization CS5321/CS5322 converter chip-set. chip-set supports seven different selectable word rates: kHz, kHz, kHz, 62.5 Input board volts peak-to-peak. Output header connections CS5322 serial interface. ORDERING INFORMATION CDB5321
switch control CS5322 logic pins Header control CS5322 logic pins Supports manual operation RESET
SYNC
Evaluation Board
Switch Selections SYNC Reference Circuitry CS5321 VREF+ MSYNC MCLK MDATA AIN+ AINR 2.048 Oscillator/ Divider Analog Regulator Analog Regulator MFLG CS5322 MSYNC MCLK MDATA MFLG CLKIN RESET Headers
Switch Selections Digital
+15V
AGND
-15V
DGND
Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.crystal.com
Copyright Cirrus Logic, Inc. 1998 (All Rights Reserved)
DS88DB2
CDB5321
+15V 47µF 0.1µF
78L05
+5VA +5VA 0.1µF
1N6276
0.1µF
LT1019 4.5V TRIM OPTIONAL VREF (4.5 Figure
-15V 47µF 1N6276 0.1µF
79L05 0.1µF
6.8V P6KE
47µF
0.1µF
DGND
Figure Power Supplies
DS88DB2
CDB5321 OVERVIEW CDB5321 evaluation board requires three separate power supplies proper operation. Figure illustrates power supply connections. required power supply input voltages consist +5V, +15V, -15V. CS5322 filter logic support devices board operate from supply. +15V -15V inputs regulated down provide supplies necessary CS5321 modulator. Figure also illustrates LT1019 4.5V reference used with CS5321 modulator. Figure illustrates CS5321 modulator circuitry, including analog input test signal source. Most often switch selections HBR=1, LPWR=0,
TANT VREF From Figure 0.1µF
OFST LPWR
OFST LPWR 100k 100k 100k
VREF+ TANT VREF-
CS5321 Datasheet
AIN-
CS5321
MCLK AIN+ MSYNC MDATA AINR MFLG MDATA AGND1 AGND2 AGND3 AGND4 AGND5 AGND6 AGND7 V1-5 TEST POINT
MCLK MSYNC MDATA MFLG MDATA Figure
DGND1 DGND2 DGND3 DGND4 V221
Figure CS5321 Modulator Input Circuitry. DS88DB2
CDB5321
10µF
0.1µF
74HC74
2.048
*2.048 exceeds specified clock frequency CS5321
CLK/4 (512 kHz) CLK/2 (1.024 MHz) (2.048 MHz)* CLKIN Figure
Figure Oscillator Divider
OFST=1. Figure illustrates 2.048 oscillator dual flip flop clock divider. Note that both oscillator divider separately decoupled from supply reduce clock jitter which introduced from noisy supplies. Jumper should CLK/2 position source 1.024 CS5322 chip normal operation. operation from clock desired, jumper should changed CLK/4 position. board tested without modification. digital interface pins CS5322 filter chip available header connectors shown Figures Note that pins each headers ground. advised that connections made control lines done with twisted pair ribbon cable; with each twisted pair containing signal ground connection. This minimizes radiated noise.
CAUTION! Caution advised when interfacing evaluation board circuitry powered from another source. example, when interfacing computer card sure that evaluation board computer both powered before connecting evaluation board headers. Always disconnect header connections when powering down board computer. Failure follow this advice cause damage either computer CS5322, because computer outputs power CDB5321 board.
DS88DB2
DS88DB2
CLKIN (From Figure CLKIN 0.1µF JP13 SCLK 0.1µF DRDY Figure SCLK
VD1+ DGND VD2+ DGND CLKIN Figure MDATA MFLG MSYNC MCLK SCLK DRDY
SIPS DRDY SCLK ERROR RSEL SYNC SYNC +5VD TDATA CSEL PWDN DECC DECB DECA USEOR ORCAL
ERROR RSEL SYNC RESET TDATA CSEL PWDN DECC DECB DECA USEOR ORCAL DECA DECB DECC PWDN CSEL TDATA
CS5322
RESET
USEOR ORCAL RSEL
CDB5321
Figure CS5322 Filter Interface
CDB5321
DECA USEOR ORCAL offset register offset register Disable offset register calibration Enable offset register calibration Sets Logic PWDN DECC DECB
Output Word Rate 62.5 Selection hardware pins 1000 2000 4000 Normal Operation Power down active Selects configuration register operating mode Select hardware pins operating mode Selects MDATA from modulator Selects TDATA filter input Sets TDATA input logic Enables TDATA from header
OFF* Allows pull-up line Sets logic
OFF* Allows CS5322 ERROR output RSEL Select status register
OFF* CSEL TDATA
OFF* Select conversion data register Chip select active Chip select inactive Enables write mode
OFF* Enables read mode OPEN *Default Figure interface. Table Switch Selections
DRDY SCLK
OPEN *Default Figure interface. Table switch selections
DRDY SCLK
DRDY From Figure SCLK
74HC04
Figure Serial Latch Interface CDB5321 (Rev board DS88DB2
CDB5321 Figures illustrate logic used drive connections header (Rev. Board) (Rev. Board). Rev. evaluation board directly interface CDBCAPTURE board through connector D-type Flip-Flop must added patch area Rev. evaluation board enable interface CDBCAPTURE board. CDBCAPTURE used perform analysis noise histograms. Tables illustrate switch positions switches switch positions with asterisks indicate preferred settin driving interface CDBCAPTURE system. CS5322 filter should hardware mode (H/S switch open). switch then used select desired output word rate. After selection DECA, DECB, DECC positions switch, RESET switch must activated,
From Figure SCLK SCLK 74HC74 DRDYD DRDYD SCLK
followed SYNC switch (unless these signals controlled header signals). Figure illustrates component layout board while figures illustrate board layout (not scale).
Using Evaluation Board Connect appropriate power supplies binding posts board. Twist digital supply lead with digital ground lead from board supply. Also twist supply leads analog voltages. high quality power supply which noise line frequency(50/60 interference. Power supplies. Then connect coaxial cable from analog signal source. Note that performance converter chip will exceed capability most signal generators, with respect noise, distortion, line frequency interference.
DRDY
74HC04
Figure Serial Latch Interface CDB5321 (Rev board. DS88DB2
CDB5321 Once power been applied board, connect ribbon cable appropriate headers (J1, and/or J3). reset sync signals CS5322 must applied before normal operation commence. This done using RESET switch SYNC switch interfacing these signals headers.
DS88DB2
CDB5321
Figure CDB5321 (Rev. Silk Screen Layout (Not Scale) DS88DB2
CDB5321
Figure CDB5321 (Rev. Component Side Layer (Not Scale)
DS88DB2
CDB5321
Figure CDB5321 (Rev. Solder Side Layer (Not Scale)
DS88DB2

Evaluation Board CS5321 CS5322 CDB5321 evaluation board that allo

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