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MAC7100EC/D Rev. 0.1, 10/2003 MAC7100 Microcontroller Family Hardware Specifications
32-bit Embedded Controller Division
This document provides electrical specifications, assignments, package diagrams MAC7100 family microcontroller devices. functional characteristics family, refer MAC7100 Microcontroller Family Reference Manual (MAC7100RM/D). This document contains following topics: Topic Section "Overview" Section "Ordering Information" Section "Electrical Characteristics" Section "Device Assignments" Section "Mechanical Information" Page
Overview
MAC7100 Family microcontrollers (MCUs) members pin-compatible family 32-bit Flash-memory-based devices developed specifically embedded automotive applications. pin-compatible family concept enables users select between different memory peripheral options scalable designs. MAC7100 Family members composed 32-bit central processing unit (ARM7TDMI-S), 512Kbytes embedded Flash EEPROM program storage, 32Kbytes embedded Flash data and/or program storage, 32Kbytes RAM. family implemented with enhanced (eDMA) controller improve performance transfers between memory many on-chip peripherals. peripheral includes asynchronous serial communications interfaces (eSCI), serial peripheral interfaces (DSPI), inter-integrated circuit (I2C) controllers, FlexCAN interfaces, enhanced modular subsystem (eMIOS), 10-bit analog-to-digital converter (ATD) channels, general-purpose timers (PIT) special-purpose timers (RTI SWT). peripherals share large number general purpose input-output (GPIO) pins, which bidirectional available with interrupt capability trigger wake-up from low-power chip modes. inclusion circuit allows power consumption performance adjusted suit operational requirements. operating frequency devices family maximum MHz. internal data paths between core, eDMA, memory peripherals bits wide, further improving performance 32-bit applications.
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Ordering Information
MAC7111 MAC7131 also offer 16-bit wide external data with address lines. family devices capable operating over junction temperature range -40° 150° Table provides comparison members MAC7100 Family availability peripheral modules various devices.
Table MAC7100 Family Device Derivatives
Module Options Program Flash Data Flash SRAM External MAC7101 512Kbytes 32Kbytes 32Kbytes channels, 16-bit channels, 24-bit LQFP MAC7111 512Kbytes 32Kbytes 32Kbytes channels, 16-bit channels, 24-bit LQFP MAC7121 512Kbytes 32Kbytes 32Kbytes channels, 16-bit channels, 24-bit LQFP MAC7131 512Kbytes 32Kbytes 32Kbytes channels, 16-bit channels, 24-bit MAC7141 512Kbytes 32Kbytes 32Kbytes channels, 16-bit channels, 24-bit LQFP
Modules Modules eSCI Modules DSPI Modules Modules eMIOS Module Timer Module GPIO Pins (max.) Package
Ordering Information
Status Core Code Core Number Generation Family Package Option Device Number Temperature Range Package Identifier Speed (MHz) Optional Package Identifiers Temperature Option -40° -40° 105° -40° 125° Package Option LQFP
Figure Order Part Number Example
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Electrical Characteristics
Electrical Characteristics
This section contains electrical information MAC7100 Family microcontrollers. information preliminary subject change without notice. MAC7100 Family devices specified tested over ranges. operation voltage within that range, specifications generally apply. However, production testing done verify operation intermediate supply voltage levels.
Parameter Classification
electrical parameters shown this appendix derived various methods. provide better understanding designer, following classification used. Parameters tagged accordingly column labeled parametric tables, appropriate.
Table Parametric Value Classification
Parameters guaranteed during production testing each individual device. Parameters derived design characterization measuring statistically relevant sample size across process variations. Parameters derived design characterization small sample size from typical devices under typical conditions (unless otherwise noted). values shown typical column within this classification, even tagged. Parameters derived mainly from simulations.
Absolute Maximum Ratings
Absolute maximum ratings stress ratings only. Functional operation outside these maximums guaranteed. Stress beyond these limits affect reliability cause permanent damage device. MAC7100 Family devices contain circuitry protecting against damage high static voltage electrical fields; however, advised that normal precautions taken avoid application voltages higher than maximum-rated voltages this high-impedance circuit. Reliability operation enhanced unused inputs tied appropriate logic voltage level (for example, either VSS5 VDD5).
Table Absolute Maximum Ratings
Rating I/O, Regulator Analog Supply Voltage Digital Logic Supply Voltage Supply Voltage Supply Voltage Analog Reference Voltage difference VDDX VDDA Voltage difference VSSX VSSA Voltage difference Voltage difference VDDA Digital Input Voltage Symbol VDD5 VDD2.5 VDDPLL VDDA VRH, VDDX VSSX VDDA -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -6.5 -0.3 +6.0 +3.0 +3.0 +6.5 +6.0 +0.3 +0.3 +6.5 +6.5 +6.0 Unit
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Electrical Characteristics
Table Absolute Maximum Ratings (continued)
Rating XFC, EXTAL, XTAL inputs TEST input Instantaneous Maximum Current Single limit digital Single limit TEST
Symbol VILV VTEST
-0.3 -0.3 -0.25
+3.0 +10.0 +155
Unit
Single limit XFC, EXTAL, XTAL pins
Single limit analog input pins Storage Temperature Range
device contains internal voltage regulator generate logic supply from supply. absolute maximum ratings apply when device powered from external source. Input must current limited value specified. determine value required current-limiting resistor, calculate resistance values using VPOSCLAMP VDDA VNEGCLAMP -0.3 then larger calculated values. These pins internally clamped VSSPLL VDDPLL. pins internally clamped VSSX VDDX, VSSR VDDR VSSA VDDA. This clamped VSSX, clamped high, must tied applications.
Protection Latch-up Immunity
testing conformity with CDF-AEC-Q100 Stress test qualification Automotive Grade Integrated Circuits. During device qualification stresses were performed Human Body Model (HBM), Machine Model (MM) Charge Device Model. device defined failure after exposure pulses device longer meets device specification. Complete parametric functional testing performed applicable device specification room temperature followed temperature, unless specified otherwise.
Table Latch-up Test Conditions
Model Human Body Series Resistance Storage Capacitance Number Pulses positive negative Machine Series Resistance Storage Capacitance Number Pulse positive negative Latch-up Minimum input voltage limit Maximum input voltage limit Description Symbol Value 1500 -2.5 Unit
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Electrical Characteristics
Table Latch-Up Protection Characteristics
Rating Symbol VHBM VCDM ILAT 2000 +100 -100 +200 -200 Unit
Human Body Model (HBM) Machine Model (MM) Charge Device Model (CDM) Latch-up Current 125°C positive negative Latch-up Current 27°C positive negative
ILAT
Operating Conditions
Unless otherwise noted, following conditions apply parametric data. Refer temperature rating device with respect ambient temperature (TA) junction temperature (TJ). power dissipation calculations refer Section 3.5, "Power Dissipation Thermal Characteristics."
Table MAC7100 Family Device Operating Conditions
Rating I/O, Regulator Analog Supply Voltage Digital Logic Supply Supply Voltage Voltage Symbol VDD5 VDD2.5 VDDPLL VDDX VSSX fosc fbus
2.35 2.35 -0.1 -0.1
2.75 2.75
Unit
Voltage Difference VDDX VDDA Voltage Difference VSSX VSSA Oscillator Frequency Frequency MAC7100C Operating Junction Temperature Range
Operating Ambient Temperature Range MAC7100V Operating Junction Temperature Range
Operating Ambient Temperature Range
C10a MAC7100M Operating Junction Temperature Range C10b
Operating Ambient Temperature Range
device contains internal voltage regulator generate logic supply from supply. absolute maximum ratings apply when this regulator disabled device powered from external source. Please refer Section 3.5, "Power Dissipation Thermal Characteristics," more details about relation between ambient temperature device junction temperature
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Electrical Characteristics
3.4.1
Pins
pins operate nominal level This class pins comprised clocks, control general purpose/peripheral pins. internal structure these pins identical; however, some functionality disabled (for example, analog inputs output drivers, pull-up/down resistors permanently disabled).
3.4.2
Oscillator Pins
pins XFC, EXTAL, XTAL dedicated oscillator operate nominal level
Power Dissipation Thermal Characteristics
Power dissipation thermal characteristics closely related. user must assure that maximum operating junction temperature exceeded. Note that JEDEC specification reserves symbol (Theta-JA) strictly junction-toambient thermal resistance test board natural convection environment. RJMA (Theta-JMA) will used both junction-to-ambient 2s2p test board natural convection junction-to-ambient with forced convection both 2s2p test boards. anticipated that generic name, will continue commonly used. average chip-junction temperature (TJ) obtained from:
Junction Temperature Ambient Temperature Total Chip Power Dissipation Package Thermal Resistance C/W)
total power dissipation calculated from:
Chip Internal Power Dissipation
cases PIO, with internal voltage regulator enabled disabled, must considered: Internal Voltage Regulator disabled:
RDSON
output currents ports associated with VDDX VDDR.
DSON (for outputs driven low)
DSON (for outputs driven high)
Internal voltage regulator enabled: IDDR current shown Table overall current flowing into VDDR, which additionally contains current flowing into external loads with output high.
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Electrical Characteristics
3.5.1
Power Dissipation Simulation Details
Table Thermal Resistance lead 14x14 LQFP, Pitch
Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) RJMA RJMA RJMA Value Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W Comments
Rating Junction Ambient (Natural Convection) Junction Ambient (Natural Convection) Junction Ambient ft./min.) Junction Ambient ft./min.) Junction Board Junction Case Junction Package
Natural Convection
LQFP, Case Outline: 983-02
Table Thermal Resistance lead 20x20 LQFP, 0.65 Pitch
Rating Junction Ambient (Natural Convection) Junction Ambient (Natural Convection) Junction Ambient ft./min.) Junction Ambient ft./min.) Junction Board Junction Case Junction Package
Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p)
Natural Convection
RJMA RJMA RJMA
Value
Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W
Comments
LQFP, Case Outline: 987-01
Table Thermal Resistance lead 20x20 LQFP, Pitch
Rating Junction Ambient (Natural Convection) Junction Ambient (Natural Convection) Junction Ambient ft./min.) Junction Ambient ft./min.) Junction Board Junction Case Junction Package
Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p)
Natural Convection
RJMA RJMA RJMA
Value
Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W
Comments
LQFP, Case Outline: 918-03
Table Thermal Resistance lead 17x17 MAP, Pitch
Rating Junction Ambient (Natural Convection) Junction Ambient (Natural Convection) Junction Ambient ft./min.) Junction Ambient ft./min.) Junction Board Junction Case Junction Package
Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p)
Natural Convection
RJMA RJMA RJMA
Value
Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W
Comments
BGA, Case Outline: 1159A-01
Comments:
Junction temperature function size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, flow, power dissipation other components board, board thermal resistance. SEMI G38-87 JEDEC JESD51-2 with single layer board (JESD51-3) horizontal. JEDEC JESD51-6 with board (JESD51-7) horizontal. Thermal resistance between printed circuit board JEDEC JESD51-8. Board temperature measured surface board center lead. fused lead packages, adjacent lead used. Thermal resistance between case surface measured cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating temperature difference between package junction temperature JEDEC JESD51-2. When Greek letters available, thermal characterization parameter written Psi-JT.
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Electrical Characteristics
Table Power Dissipation Simulation Model Packaging Parameters
Component Mold Compound Leadframe (Copper) Attach Conductivity
Power Supply
MAC7100 Family utilizes several pins supply power oscillator, PLL, digital core, ports ATD. context this section, VDD5 used VDDA, VDDR VDDX; VSS5 used VSSA, VSSR VSSX unless otherwise noted. IDD5 denotes currents flowing into VDDA, VDDX, VDDR. used VDD2.5, VDDPLL, used VSS2.5 VSSPLL. used currents flowing into VDD2.5 VDDPLL.
3.6.1
Current Injection
power supply must maintain regulation within VDD5 VDD2.5 operating range during instantaneous operating maximum current conditions. positive injection current (Vin VDD5) greater than IDD5, injection current flow VDD5 could result external power supply going regulation. important ensure that external VDD5 load will shunt current greater than maximum injection current. greatest risk will when consuming very little power (for example, system clock present, clock rate very low).
3.6.2
Power Supply Pins
VDDR VSSR pair supplies internal voltage regulator. VDDA VSSA pair supplies converter reference circuit internal voltage regulator. VDDX VSSX pair supplies pins. VDDPLL VSSPLL pair supplies oscillator PLL. VDDX pins internally connected metal. VSSX pins internally connected metal. VSS2.5 pins internally connected metal. VDDA, VDDX VDDR well VSSA, VSSX VSSR connected anti-parallel diodes protection.
3.6.3
Supply Currents
current measurements without output loads. Unless otherwise noted currents measured single chip mode, internal voltage regulator enabled 40MHz frequency using 4MHz oscillator power mode. Production testing performed using square wave signal EXTAL input. expanded modes, currents flowing system highly dependent load address, data control signals well duty cycle those signals. generally applicable numbers given. good estimate take single chip currents currents external loads.
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Table Supply Current Characteristics
Rating Supply Current Single Chip -40° 105° 125° -40° 105° 125° -40° 105° 125° -40° 105° 125° -40° 105° 125° -40° 105° 125° -40° 105° 125° -40° 105° 125° -40° 105° 125°
Electrical Characteristics
Pins
Pins
Pins
time publication, this value determined, will supplied when device characterization complete. 85°C, 105°C, 125°C refer "C", "V", Temperature Options, respectively. disabled enabled.
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Regulator
Core
Stop Current assumed
Regulator
Core
Doze Supply Current Psuedo Stop Current
Regulator enabled)
IDDRreg IDDRpins Doze Pseudo Stop IDDPScore IDDPSreg IDDPSpins 4/53 IDDScore IDDSreg IDDSpins
Symbol IDDRcore
Unit
Core
Electrical Characteristics
3.6.4
Voltage Regulator Characteristics
Table VREG Operating Conditions
Characteristic Symbol VVDDRA IREG 2.97 2.45 1.60 2.35 2.00 1.60 4.10 4.25 2.25 0.97 Typical 4.37 4.52 2.35 2.75 2.75 2.75 2.75 2.75 4.66 4.77 2.05 Unit
Input Voltages Regulator Current Reduced Power Mode Shutdown Mode Output Voltage Core Full Performance Mode Reduced Power Mode Shutdown Mode Output Voltage Full Performance Mode Reduced Power Mode Reduced Power Mode Shutdown Mode Voltage Interrupt Assert Level Deassert Level Voltage Reset Assert Level Power Reset Assert Level Deassert Level
VDDPLL
VLVIA VLVID VLVRA VPORA VPORD
High Impedance Output. Current IDDPLL (Low Power Oscillator). Current IDDPLL (Standard Oscillator). Monitors VDDA, active only full performance mode. Indicated performance degradation supply voltage. Monitors VDD2.5, active only full performance mode. Only active reduced performance mode. Monitors VDD2.5, active modes.
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Electrical Characteristics
3.6.5
Chip Power Voltage Drops
VREG sub-modules (low voltage interrupt), (power reset) (low voltage reset) handle chip power-up drops supply voltage. Refer Figure
Voltage VLVID VLVIA VDDA
VDD2.5 VLVRD VLVRA VPORD
Note: scale.
Enabled
Disabled
Time
Figure VREG Chip Power-up Voltage Drops
3.6.6
Output Loads
Table VREG Recommended Load Capacitances
Rating Symbol CLVDD CLVDDfcPLL 12000 5000 Unit
on-chip voltage regulator intended supply internal logic oscillator circuits. external load allowed. Capacitive loads specified Table Capacitors with dielectricum required.
Load Capacitance each VDD2.5 Load Capacitance VDDPLL
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Electrical Characteristics
Characteristics
Table Characteristics
This section describes characteristics pins both operating conditions. parameters always applicable; example, pins feature pull up/down resistances.
Conditions shown Table unless otherwise noted Input High Voltage Input High Voltage Input Voltage Input Voltage Input Hysteresis Input Leakage Current (pins high impedance input mode) VDD5 VSS5 Output High Voltage (pins output mode) Partial Drive -2mA Full Drive -10mA Output Voltage (pins output mode) Partial Drive +2mA Full Drive +10mA Internal Pull Device Current, tested Max. Internal Pull Device Current, tested Min. Internal Pull Down Device Current, tested Min. Internal Pull Down Device Current, tested Max. Input Capacitance Injection Single limit Total Device Limit. injected currents Port Interrupt Input Pulse filtered Port Interrupt Input Pulse passed current Rating Symbol
0.65 VDD5 VSS5 VDD5
VDD5 0.35 VDD5
Unit
VHYS
IPUL IPUH IPDH IPDL IICS IICP tPULSE tPULSE
-2.5
-130
Maximum leakage current occurs maximum operating temperature. Current decreases approximately one-half each 12°C temperature range from 50°C 125°C. Refer Section 3.6.1, "Current Injection," more details Parameter only applies STOP Pseudo STOP mode.
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Table Characteristics
Conditions shown Table with VDDX ±10% temperature maximum +140°C unless otherwise noted. Input High Voltage Input High Voltage Input Voltage Input Voltage Input Hysteresis Input Leakage Current (pins high impedance input mode)
Rating
Symbol VHYS
0.65 VDD5 VSS5 VDD5
VDD5 0.35 VDD5
Unit
Output High Voltage (pins output mode) Partial Drive -0.75mA Full Drive -4.5mA Output Voltage (pins output mode) Partial Drive +0.9mA Full Drive +5.5mA Internal Pull Device Current, tested Max. Internal Pull Device Current, tested Min. Internal Pull Down Device Current, tested Min.
IPUL IPUH IPDH IPDL IICS IICP tPULSE tPULSE
-2.5
Internal Pull Down Device Current, tested Max. Input Capacitance Injection Single limit Total Device Limit. injected currents Port Interrupt Input Pulse filtered Port Interrupt Input Pulse passed
current
Maximum leakage current occurs maximum operating temperature. Current decreases approximately one-half each 12°C temperature range from 50°C 125°C. Refer Section 3.6.1, "Current Injection," more details Parameter only applies STOP Pseudo STOP mode.
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Electrical Characteristics
Clock Reset Generator Electrical Characteristics
This section describes electrical characteristics oscillator, phase-locked loop, clock monitor reset generator.
3.8.1
Oscillator Characteristics
MAC7100 Family features internal power loop controlled Pierce oscillator full swing Pierce oscillator/external clock mode. selection loop controlled Pierce oscillator full swing Pierce oscillator/external clock depends level XCLKS signal rising edge RESET signal. Before asserting oscillator internal system clock distribution subsystem, quality oscillation checked each start from either power STOP oscillator fail. tCQOUT specifies maximum time before switching internal self clock mode after STOP proper oscillation detected. quality check also determines minimum oscillator start-up time tUPOSC. device also features clock monitor. Clock Monitor Failure asserted frequency incoming clock signal below Clock Monitor Assert Frequency fCMFA.
Table Oscillator Characteristics
Rating Symbol fOSC fOSC IOSC tUPOSC tCQOUT fCMFA fEXT tEXTL tEXTH tEXTR tEXTF VDCBIAS
0.45
Unit
Crystal oscillator range (loop controlled Pierce) Crystal oscillator range (full swing Pierce) Startup Current Oscillator start-up time (loop controlled Pierce) Clock Quality check time-out Clock Monitor Failure Assert Frequency External square wave input frequency External square wave pulse width External square wave pulse width high External square wave rise time
External square wave fall time Input Capacitance (EXTAL, XTAL pins) EXTAL Operating Bias loop controlled mode
Depending crystal; damping series resistor might necessary XCLKS negated during reset fosc MHz, Maximum value extreme cases using high frequency crystals
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Electrical Characteristics
3.8.2
Filter Characteristics
oscillator provides reference clock PLL. voltage controlled oscillator (VCO) also system clock source self clock mode. order operate reliably, care must taken select proper values external loop filter components.
VDDPLL fVCO
Phase Detector fOSC REFDV+1 fREF
fCMP
Loop Divider SYNR+1
Figure Basic Functional Diagram
procedure described below used calculate resistance capacitance values using typical values from Table First, Gain desired output frequency approximated
phase detector relationship given
current tracking mode. loop bandwidth should chosen fulfill Gardner's stability criteria least factor typical values ensures good transient response.
finally frequency relationship defined
synr
With above inputs resistance calculated
capacitance calculated
0.516
capacitance should chosen range
stabilization delays shown Table dependant operational settings external component selection (for example, crystal, filter).
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Electrical Characteristics
3.8.2.1
Jitter Information
basic functionality shown Figure With each transition clock fcmp, deviation from reference clock fref measured input voltage adjusted accordingly. adjustment done continuously with abrupt changes clock output frequency. Noise, voltage, temperature other factors cause slight variations control loop resulting clock jitter. This jitter affects real minimum maximum clock periods illustrated Figure important note that pre-scaler used timers serial modules will eliminate effect jitter large extent.
tMIN1 tNOM
tMAX1 tMIN(N) tMAX(N)
Figure Jitter Definitions
relative deviation tNOM maximum clock period, decreases towards zero larger number clock periods (N). Thus, jitter defined
100, following equation good maximum jitter:
J(N)
Figure Maximum Clock Jitter Approximation
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3.8.3
Characteristics
Table Characteristics
Rating reference frequency, crystal oscillator range
Symbol fREF fSCM fVCO |trk| |Lock| |unl| |unt| tstab tacq
Unit MHz/V
Self Clock Mode frequency locking range Lock Detector transition from Acquisition Tracking mode Lock Detection Un-Lock Detection Lock Detector transition from Tracking Acquisition mode PLLON Total Stabilization delay (Auto Mode) PLLON Acquisition mode stabilization delay PLLON Tracking mode stabilization delay Charge pump current acquisition mode Charge pump current tracking mode Jitter loop gain parameter Jitter loop frequency parameter Jitter parameter Jitter parameter
38.5 -100
VDDPLL Percentage deviation from target frequency stabilization delay highly dependent operational requirement external component values (for example, crystal filter component values). Notes show component values typical configurations. Appropriate filter values should chosen based operational requirement system. MHz, fSYS (REFDV 0x03, SYNR 0x01), MHz, fSYS (REFDV 0x00, SYNR 0x01),
3.8.4
Crystal Monitor Time-out
Table Crystal Monitor Time-Outs
18.5 Unit
time-out Table shows delay crystal monitor trigger when clock stops, either high level. corresponding clock period with ideal duty cycle twice this time-out value.
3.8.5
Clock Quality Checker
Table Maximum Clock Quality Check Timings
Clock Check Windows Check Window Timeout Window Value 20.0 0.46 Unit
timing clock quality check derived from oscillator frequency range Table These numbers define upper time limit individual check windows complete.
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3.8.6
Startup
Table summarizes several startup characteristics explained this section. Refer MAC7100 Microcontroller Family Reference Manual (MAC7100RM/D) detailed description startup behavior.
Table Startup Characteristics
release level assert level Reset input pulse width, minimum input time Startup from Reset Interrupt pulse width, edge-sensitive mode Wait recovery startup time Rating Symbol VPORR VPORA PWRSTL nRST PWIRQ tWRS 0.97 2.07 Unit tosc nosc tcyc
3.8.6.1
Power Voltage Reset (POR LVR)
release level VPORR assert level VPORA derived from VDD2.5 supply. assert level VLVRA derived from VDD2.5 supply. They also valid device powered externally. After releasing reset, oscillator clock quality check started. after time tCQOUT valid oscillation detected, will start using internal self-generated clock. fastest startup time possible given tuposc (refer Table 17).
3.8.6.2
SRAM Data Retention
SRAM contents integrity guaranteed PORF CRGFLG register following reset operation.
3.8.6.3
External Reset
When external reset asserted time greater than PWRSTL, module generates internal reset starts fetching reset vector without doing clock quality check, there stable oscillation before reset.
3.8.6.4
Stop Recovery
returned mode from stop mode external interrupt. clock quality check performed same manner before releasing clocks system.
3.8.6.5
Pseudo Stop Doze Recovery
Recovery from pseudo stop doze modes essentially same, since oscillator stopped either mode. controller returned mode internal external interrupts other wakeup events system. After twrs, fetches interrupt vector wakeup event interrupt, continues execute code wakeup event interrupt.
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External Timing Specifications
NOTE processor timings synchronous; that input setup/hold output delay with respect rising edge reference clock. reference clock CLKOUT output. other timing relationships derived from these values.
Table External Input Timing Specifications
Table lists processor input timings, which shown Figure Figure Figure
CLKOUT
Rating
Symbol tCYC
Unit
Control Inputs
Control input valid CLKOUT
high Data Inputs
tCVCH tCHCII tDIVCH tCHDII
CLKOUT high control inputs invalid Data input (DATA[15:0]) valid CLKOUT high CLKOUT high data input (DATA[15:0]) invalid
Timing specifications have been indicated taking into account full drive strength pads. pins being referred control inputs.
CLKOUT(45MHz) tSETUP
tHOLD
Input Setup Hold
Invalid
Valid
Invalid
Input Rise Time
tRISE
Input Fall Time
tFALL
CLKOUT
Inputs
Figure General Input Timing Requirements
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3.9.1
Read Write Cycles
Table External Output Timing Specifications
Table lists processor output timings. Read/write timings listed Table shown Figure Figure
Rating Control Outputs
Symbol
Unit
CLKOUT high chip selects valid
tCHCV tCHBV tCHOV tCHCOI tCHCI tCHAV tCHAI
0.5tCYC 0.5tCYC
0.5tCYC 0.5tCYC 0.5tCYC
CLKOUT high byte select (BS[1:0]) valid CLKOUT high output select (OE) valid
CLKOUT high control output (BS[1:0], invalid CLKOUT high chip selects invalid CLKOUT high address (ADDR[21:0]) control (R/W) valid CLKOUT high address (ADDR[21:0]) control (R/W) invalid Data Outputs CLKOUT high data output (DATA[15:0]) valid CLKOUT high data output (DATA[15:0]) invalid CLKOUT high data output (DATA[15:0]) high impedance
Address Attribute Outputs
tCHDOV tCHDOI tCHDOZ
transitions after falling edge CLKOUT. transitions after falling edge CLKOUT. transitions after falling edge CLKOUT.
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CLKOUT
ADDR[21:0]
BS[1:0]
DATA[15:0]
Figure Read/Write (Internally Terminated) Timing
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Electrical Characteristics
CLKOUT
ADDR[21:0]
BS[1:0]
DATA[15:0]
Figure Read Cycle Terminated
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Electrical Characteristics
3.10 Analog-to-Digital Converter Characteristics
Table Table show conditions under which operates. following constraints exist obtain full-scale, full range results: VSSA VDDA. This constraint exists because sample buffer amplifier cannot drive beyond power supply levels. input level goes outside this range will effectively clipped.
Table Operating Characteristics Range
Conditions shown Table unless otherwise noted Reference Potential Differential Reference Voltage Clock Frequency Cycles Rating High Symbol fATDCLK VSSA VDDA 4.50 5.00 VDDA VDDA 5.25 0.375 0.750 Unit Cycles Cycles
10-bit Conversion PeriodClock NCONV10 2.0MHz fATDCLK TCONV10 8-bit Conversion PeriodClock Cycles 2.0MHz fATDCLK Recovery Time (VDDA Reference Supply current module enabled Reference Supply current modules enabled NCONV8 TCONV8 tREC IREF IREF
Full accuracy guaranteed when differential voltage less than 4.50 Minimum time assumes final sample period clocks; maximum time assumes final sample period clocks.
Table Operating Characteristics Range
Conditions shown Table with VDDX ±10% temperature maximum +140°C unless otherwise noted.
Rating High
Symbol VRH-VRL fATDCLK Cycles
VSSA VDDA
VDDA VDDA 0.375 0.250
Unit Cycles Cycles
Reference Potential Differential Reference Voltage Clock Frequency
10-bit Conversion PeriodClock NCONV10 Conv, Time 2.0MHz Clock fATDCLK TCONV10 8-bit Conversion PeriodClock Cycles Conv, Time 2.0MHz Clock fATDCLK Recovery Time (VDDA=5.0 Reference Supply current module enabled Reference Supply current modules enabled NCONV8 TCONV8 tREC IREF IREF
Full accuracy guaranteed when differential voltage less than Minimum time assumes final sample period clocks; maximum time assumes final sample period clocks.
3.10.1 Factors Influencing Accuracy
Three factors source resistance, source capacitance current injection have influence accuracy ATD.
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Electrical Characteristics
3.10.1.1 Source Resistance
input leakage current specified Table conjunction with source resistance there will voltage drop from signal source input. maximum specified source resistance results error less than (2.5 maximum leakage current. device operating conditions less than worst case, leakage-induced errors acceptable, larger values source resistance allowed.
3.10.1.2 Source Capacitance
When sampling, additional internal capacitor switched input. This cause voltage drop charge sharing with external capacitance capacitance. maximum sampling error input voltage LSB, then external filter capacitor must calculated 1024 (CINS CINN).
3.10.1.3 Current Injection
There cases consider: current injected into channel being converted. channel being stressed conversion values 0x3FF (0xFF 8-bit mode) analog inputs greater than 0x000 values less than unless current higher than specified disruptive condition. Current injected into pins neighborhood channel being converted. portion this current picked channel (coupling ratio This additional current impacts accuracy conversion depending source resistance. additional input voltage error converted channel calculated VERR IINJ, with IINJ being currents injected into pins adjacent converted channel.
Table Electrical Characteristics
Conditions shown Table unless otherwise noted Rating Symbol CINN CINS -2.5 Unit
input Source Resistance Total Input Capacitance Sampling Sampling Disruptive Analog Input Current Coupling Ratio positive current injection Coupling Ratio negative current injection
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Electrical Characteristics
3.10.2 Accuracy
Table Table specify conversion performance excluding errors current injection, input capacitance source resistance.
Table Conversion Performance Range
Conditions shown Table unless otherwise noted. VREF 5.12 resulting count count fATDCLK MHz, VDDA
Rating
Symbol
-2.5 -0.5 -1.0 -1.5
±1.5 ±2.0 ±0.5 ±1.0
Unit Counts Counts Counts Counts Counts Counts
10-bit Resolution 10-bit Differential Nonlinearity 10-bit Integral Nonlinearity 10-bit Absolute Error 8-bit Resolution 8-bit Differential Nonlinearity 8-bit Integral Nonlinearity 8-bit Absolute Error
These values include quantization error which inherently count converter.
Table Conversion Performance Range
Conditions shown Table unless otherwise noted. VREF 5.12 resulting count count fATDCLK MHz, VDDA
Rating
Symbol
-1.5 -3.5 -0.5 -1.5 -1.5
3.25 ±1.5 ±2.0 ±1.0 ±1.0
Unit Counts Counts Counts Counts Counts Counts
10-bit Resolution 10-bit Differential Nonlinearity 10-bit Integral Nonlinearity 10-bit Absolute 8-bit Resolution 8-bit Differential Nonlinearity 8-bit Integral Nonlinearity 8-bit Absolute Error Error
These values include quantization error which inherently count converter.
following definitions also Figure Differential Non-Linearity (DNL) defined difference between adjacent switching steps.
Integral Non-Linearity (INL) defined DNLs:
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10-bit Absolute Error Boundary
0x3FF 0x3FE 0x3FD 0x3FC 0x3FB 0x3FA 0x3F9 0x3F8 0x3F7 10-bit Resolution 0x3F6 0x3F5 0x3F4 0x3F3 5055 5065 5075 5085 5095 5105 5115 5060 5070 5080 5090 5100 5110 5120 8-bit Transfer Curve 10-bit Transfer Curve Ideal Transfer Curve 0xFD 0xFE VI-1 8-bit Absolute Error Boundary 0xFF
Figure Accuracy Definitions
NOTE Figure shows only definitions, specification values refer Table
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8-bit Resolution
Electrical Characteristics
3.10.3 Electrical Specifications
Table lists electrical characteristics module. Table lists analog-to-digital conversion performance specifications.
Table Electrical Characteristics (Operating)
Rating Reference Potential High Voltage Difference Analog Input Voltage Digital Input Voltage Analog Supply Current High -40°C 25°C 85°C 105°C 125°C Pseudo Stop -40°C 25°C 85°C 105°C 125°C Stop -40°C 25°C 85°C 105°C 125°C
Symbol VINDC IDDArun
VSSA VDDA -0.3 VDDA VSSA
VDDA VDDA VDDA VDDA VDDA 10-4
Unit Counts Counts
IDDApseudo_stop
IDDAstop
(low power)
Reference Supply Current Input Injection Current Input Current, Channel Total Input Capacitance Coupling Ratio Sampling Sampling
IREF IINJ IOFF CINN CINS
-200
Disruptive Analog Input Current Incremental Error injection current (All channels with 100k)9 Incremental Error injection current (Channel under test Rs=10k, IINJ=±3mA) Incremental Capacitance during Sampling
CSAMP
voltages referred VSSA, 125oC, VDDA ±10% conversion rate unless otherwise noted. Refer Table additional operating conditions. obtain full-scale, full-range results, VSSA VINDC VDDA. Sample buffer cannot drive beyond power supply levels. input level goes outside this range, will effectively clipped. Full accuracy guaranteed when differential reference voltage less than 85°C, 105°C, 125°C refer "C", "V", Temperature Options, respectively. input injection current specified count error.
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Electrical Characteristics
Maximum leakage occurs maximum operating temperature. Current decreases approximately one-half each ambient temperature range Below disruptive current conditions, channel being stressed conversion values 0x3FF analog inputs greater than 0x000 values less than VRL. This assumes that VDDA AVRH VSSA presence sample amplifier. Other channels affected non-disruptive conditions. Coupling Ratio, defined ratio output current, IOUT, measured under test injection current, IINJ, when both adjacent pins overstressed with specified injection current. IOUT IINJ. input voltage error channel under test calculated Verr IINJ Total injection current determined number channels injecting (for example, 15), external injection voltage (VINJ VPOSCLAMP, VINJ VNEGCLAMP), external source impedance, wherein input channels have same values. determine error voltage converted channel, only adjacent channels expected contribute error voltage: Verrj (VINJ VCLAMP) maximum sampling error input voltage 1LSB, then external filter capacitor, 1024 CSAMP. value CSAMP design reduced, increased slightly.
Table Performance Specifications
Rating
Symbol
-2.5
Unit Counts Counts Counts
10-bit Resolution 10-bit Differential Nonlinearity 10-bit Integral Nonlinearity 10-bit Absolute Error input Source Impedance
voltages referred VSSA, VDDA V±10%, clock Mhz., Note: Count VREF 5.12 count 10-bit count These values include quantization error which inherently count converter. This value based error attributed specified leakage value resulting error less than (2.5 mV). operating conditions less than worst case leakage-induced error acceptable, larger values source resistance allowable.
3.10.4 Timing Specifications
Table Timing Specifications
Rating Symbol Fclk Fatdclk Clock Cycles Conv. Time NCONV10* TCONV10 25.0 Unit Cycles* µsec µsec Module Clock Frequency Conversion Clock Frequency 10-bit Conversion Period*
Stop Recovery Time (VDDA
Table External Trigger Timing Specifications
Parameter Symbol TPERIOD tDLY sample conv. clock Unit CYCLE ETRIG Minimum Period
ETRIG Minimum Pulse Width ETRIG Level Recovery Conversion Start Delay
Time prior conversion that ETRIG must deactivated that another conversion sequence does start.
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Edge Sensitive Falling Edge Active Coversion Activity ETRIG tDLY Frequency Level Sensitive Active Sequence Complete Flag ETRIG ASCIF tDLY Frequency ETRIG ASCIF tDLY tDLY tDLY tPERIOD
Coversion Activity Level Sensitive Active Sequence Complete Flag Coversion Activity
Figure External Trigger Timing Diagram
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3.11 Serial Peripheral Interface Electrical Specifications
3.11.1 Master Mode
Figure Figure illustrate master mode timing. Timing values shown Table
Table Master Mode Timing Characteristics
Conditions shown Table unless otherwise noted, CLOAD 200pF outputs Rating Symbol tsck tlead tlag twsck tbus 2048 1024 tbus Unit fbus tbus tsck tsck Operating Frequency Period tsck 1/fop
Enable Lead Time Enable Time Clock (SCK) High Time Data Setup Time (Inputs) Data Hold Time (Inputs) Data Valid (after Enable Edge)
Data Hold Time (Outputs) Rise Time Inputs Outputs Fall Time Inputs Outputs
numbers column labeled "Num" missing. This been done purpose consistent between Master Slave timing shown Table
3.11.2 Slave Mode
Figure Figure illustrate slave mode timing. Timing values shown Table
Table Slave Mode Timing Characteristics
Conditions shown Table unless otherwise noted, CLOAD 200pF outputs Rating Symbol tsck tlead tlag twsck tdis tcyc 2048 Unit fbus tbus tcyc tcyc tcyc tcyc
Operating Frequency Period tsck 1/fop Enable Lead Time Enable Time Clock (SCK) High Time Data Setup Time (Inputs) Data Hold Time (Inputs) Slave Access Time Slave Disable Time Data Valid (after Edge)
Data Hold Time (Outputs) Rise Time Inputs Outputs Fall Time Inputs Outputs
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PCSx (OUTPUT)
(CPOL (OUTPUT) (CPOL (OUTPUT)
(INPUT)
SOUT (OUTPUT)
configured output. LSBFE LSBFE order LSB, MSB.
Figure Master Timing (CPHA
PCSx (OUTPUT)
(CPOL (OUTPUT) (CPOL (OUTPUT)
(INPUT)
SOUT (OUTPUT)
Port Data
Master
Master
Port Data
configured output. LSBF LSBF order LSB, MSB.
Figure Master Timing (CPHA
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(INPUT)
(CPOL (INPUT) (CPOL (INPUT)
SOUT (OUTPUT)
Slave
Slave
(INPUT)
Figure Slave Timing (CPHA
(INPUT)
(CPOL (INPUT) (CPOL (INPUT)
SOUT (OUTPUT)
Slave
Slave
(INPUT)
Figure Slave Timing (CPHA
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3.12 FlexCAN Electrical Specifications
Table FlexCAN Wake-up Pulse Characteristics
Conditions shown Table unless otherwise noted Rating Symbol tWUP tWUP Unit
FlexCAN Wake-up dominant pulse filtered FlexCAN Wake-up dominant pulse passed
3.13 Program Flash Data Flash Timing Characteristics
NOTE Unless otherwise noted abbreviation (Non-Volatile Memory) used both program Flash data Flash.
3.13.1 timing
time base program erase operations derived from system clock divided (Fsys/2). minimum system frequency fNVMfsys required performing program erase operations. modules have means monitor frequency will prevent program erase operation frequencies above below specified minimum. Attempting program erase modules lower frequency full program erase transition assured. Flash Data Flash program erase operations timed using clock derived from system frequency using CFMCLKD register. frequency this clock must within limits specified fNVMOP. minimum program erase times shown Table calculated maximum fNVMOP maximum fbus. maximum times calculated minimum fNVMOP fbus MHz.
3.13.1.1 Single Word Programming
programming time single word programming dependant frequency well frequency fNVMOP calculated according following formula.
swpgm NVMOP
3.13.1.2 Burst Programming
This applies only Flash where words programmed consecutively using burst programming keeping command pipeline filled. time program consecutive word calculated
bwpgm NVMOP brpgm swpgm bwpgm
time program whole Burst programming more than times faster than single word programming.
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3.13.1.3 Sector Erase
Erasing byte Flash sector takes:
4000 NVMOP
setup time ignored this operation.
3.13.1.4 Mass Erase
Erasing block takes:
mass 20000 NVMOP
setup time ignored this operation.
3.13.1.5 Blank Check
time takes perform blank check Flash Data Flash dependant location first non-blank word starting relative address zero. takes cycle word verify plus setup command.
check location
Table Timing Characteristics
Rating
Symbol fNVMfsys fNVMOP tswpgm tbwpgm tbrpgm tera tmass tcheck tcheck
20.4
74.5 1035.5 26.7
Unit
System Clock/2 Operating Frequency Single Word Programming Time Flash Burst Programming consecutive word Flash Burst Programming Time Words Sector Erase Time Mass Erase Time Blank Check Time Flash block
frequency Programming Erase Operations fNVMBUS
678.4
32778 2058
tcyc tcyc
Blank Check Time Data Flash block
Conditions shown Table unless otherwise noted Restrictions oscillator crystal mode apply! Minimum programming times achieved under maximum operating frequency fNVMOP maximum frequency fbus. Maximum erase programming times achieved under particular combinations fNVMOP frequency fbus. Refer formulae Section 3.13.1.1, "Single Word Programming," through Section 3.13.1.4, "Mass Erase," more information. Minimum erase times achieved under maximum operating frequency fNVMOP. Minimum time, first word array blank Maximum time complete check erased block
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Electrical Characteristics
3.13.2 Reliability
reliability blocks guaranteed stress test during qualification, constant process monitors burn-in screen early life failures. failure rates data retention program/erase cycling specified operating conditions noted. program/erase cycle count sector incremented every time sector mass erase event executed.
Table Reliability Characteristics
Conditions shown Table unless otherwise noted. Rating 10,000 Unit Cycles Years
Program/Data Flash Program/Erase endurance (-40C +125C) Program/Data Flash Data Retention Lifetime
NOTE values shown Table target values subject characterization. Flash cycling performance, each Program operation must preceded erase.
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Device Assignments
Device Assignments
MAC7100 Family available 208-pin ball grid array (MAP BGA), 144-pin profile quad flat (LQFP), 112-pin LQFP, 100-pin LQFP package options. family devices offer pin-compatible packaged devices assist with system development accommodate direct application enhancement path. Refer Table comparison peripheral sets package options each device. Most pins perform more functions, which described more detail MAC7100 Microcontroller Family Reference Manual (MAC7100RM/D). Figure Figure Figure Figure Figure show assignments various packages.
MAC7141PV Assignments
TXD_A RXD_A TXD_B RXD_B VDD2.5 VSS2.5 PD10 PE15 AN15_A PE14 AN14_A PE13 AN13_A PE12 AN12_A PE11 AN11_A PE10 AN10_A VSSA VDDA VSSX VDDX PF15 PF14 PF13 PF12 PF11 PF10
CNTX_A CNRX_A CNTX_B CNRX_B
Figure Assignments MAC7141 100-pin LQFP
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eMIOS6 eMIOS5 eMIOS4 eMIOS3 eMIOS2 NEXPR eMIOS1 NEXPS eMIOS0 RESET VSSX VDDX RXD_D PG12 TXD_D PG13 VDD2.5 VSS2.5 VSSR VDDR VDDPLL VSSPLL EXTAL XTAL TEST PA15 MODB MODA
SIN_A SOUT_A SCK_A SS_A PCS0_A PCS1_A PCS2_A PCSS_A PCS5_A eMIOS15 eMIOS14 eMIOS13 eMIOS12 eMIOS11 eMIOS10 eMIOS9 eMIOS8 eMIOS7
MAC7141 LQFP
AN9_A AN8_A AN7_A AN6_A RDY' AN5_A MSEO' AN4_A MDO1' AN3_A MDO0' AN2_A EVTI' AN1_A EVTO' AN0_A MCKO' VDDX VSSX XIRQ XCLKS CLKOUT PB15 SIN_B PB14 SOUT_B PB13 SCK_B PB12 PCS1_B PB11 PCS2_B PB10 PCS5_B PCSS_B PCS0_B SS_B
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Device Assignments
MAC7121PV Assignments
TXD_A RXD_A TXD_B RXD_B PG15 TXD_C PG14 RXD_C VDD2.5 VSS2.5 PD10 PE15 AN15_A PE14 AN14_A PE13 AN13_A PE12 AN12_A PE11 AN11_A PE10 AN10_A VSSA VDDA CNTX_A CNRX_A CNTX_C CNRX_C CNTX_D CNRX_D CNTX_B CNRX_B
Figure Assignments MAC7121 112-pin LQFP
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eMIOS6 eMIOS5 eMIOS4 eMIOS3 eMIOS2 NEXPR eMIOS1 NEXPS eMIOS0 RESET VSSX VDDX RXD_D PG12 TXD_D PG13 VDD2.5 VSS2.5 VSSR VDDR VDDPLL VSSPLL EXTAL XTAL TEST PA15 PA14 PA13 MODB MODA SS_B PCS0_B
SIN_A SOUT_A SCK_A SS_A PCS0 PCS1_A PCS2_A PCSS_A PCS5_A eMIOS15 eMIOS14 eMIOS13 eMIOS12 eMIOS11 eMIOS10 eMIOS9 eMIOS8 eMIOS7
PG10 PG11 VSSX VDDX PF15 PF14 PF13 PF12 PF11 PF10
MAC7121 LQFP
AN9_A AN8_A AN7_A AN6_A RDY' AN5_A MSEO' AN4_A MDO1' AN3_A MDO0' AN2_A EVTI' AN1_A EVTO' AN0_A MCKO' PA10 PA11 PA12 PC15 VDDX VSSX XIRQ CLKOUT XCLKS PB15 SIN_B PB14 SOUT_B PB13 SCK_B PB12 PCS1_B PB11 PCS2_B
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Device Assignments
MAC7101PV Assignments
TXD_A RXD_A TXD_B RXD_B PG15 TXD_C PG14 RXD_C MCKO EVTO EVTI MDO0 MDO1 MSEO VDD2.5 VSS2.5 VSSX VDDX PE15 AN15_A PH15 AN15_B PE14 AN14_A PH14 AN14_B PE13 AN13_A PH13 AN13_B PE12 AN12_A PH12 AN12_B PE11 AN11_A PH11 AN11_B PE10 AN10_A VSSA VDDA
CNTX_A CNRX_A CNTX_C CNRX_C CNTX_D CNRX_D CNTX_B CNRX_B
SIN_A SOUT_A SCK_A SS_A PCS0_A PCS1_A PCS2_A PCSS_A PCS5_A eMIOS15 eMIOS14 eMIOS13 eMIOS12
Figure Assignments MAC7101 144-pin LQFP
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eMIOS6 eMIOS5 eMIOS4 eMIOS3 eMIOS2 NEXPR eMIOS1 NEXPS eMIOS0
PC10 PC11 RESET VSSX VDDX RXD_D PG12 TXD_D PG13 VDD2.5 VSS2.5 VSSR VDDR VDDPLL VSSPLL EXTAL XTAL TEST VSSX VDDX PA15 PA14 PA13 PD11 PD12 MODB MODA SS_B PCS0_B
eMIOS11 eMIOS10 eMIOS9 eMIOS8 eMIOS7
PG10 PG11 VSSX VDDX PF15 PF14 PF13 PF12 PF11 PF10
MAC7101 LQFP
PH10 AN10_B AN9_A AN9_B AN8_A AN8_B AN7_A AN7_B AN6_A RDY' AN6_B AN5_A MSEO' AN5_B AN4_A MDO1' AN4_B AN3_A MDO0' AN3_B AN2_A EVTI' AN2_B AN1_A EVTO' AN1_B AN0_A MCKO' AN0_B VDDX VSSX PD15 PD14 PD13 XIRQ CLKOUT XCLKS VSSX PB15 SIN_B PB14 SOUT_B PB13 SCK_B PB12 PCS1_B PB11 PCS2_B PB10 PCS5_B PCSS_B
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MAC7111PV Assignments
TXD_A RXD_A TXD_B RXD_B PG15 TXD_C PG14 RXD_C DATA0 MCKO DATA1 EVTO DATA2 EVTI DATA3 MDO0 DATA4 MDO1 DATA5 MSEO DATA6 VDD2.5 VSS2.5 VSSX VDDX PD10 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 PE15 AN15_A PE14 AN14_A PE13 AN13_A PE12 AN12_A PE11 AN11_A PE10 AN10_A VSSA VDDA
Figure Assignments MAC7111 144-pin LQFP
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eMIOS6 eMIOS5 eMIOS4 eMIOS3 eMIOS2 NEXPR eMIOS1 NEXPS eMIOS0 ADDR8 ADDR9 ADDR10 PC10 ADDR11 PC11 RESET VSSX VDDX RXD_D PG12 TXD_D PG13 VDD2.5 VSS2.5 VSSR VDDR VDDPLL VSSPLL EXTAL XTAL TEST VSSX VDDX DATA15 PA15 DATA14 PA14 DATA13 PA13 PD11 PD12 MODB MODA SS_B PCS0_B
CNTX_A CNRX_A CNTX_C CNRX_C CNTX_D PG10 CNRX_D PG11 CNTX_B CNRX_B ADDR0 ADDR1 ADDR2 ADDR3 VSSX VDDX SIN_A SOUT_A SCK_A SS_A PCS0_A PCS1_A PCS2_A PCSS_A PCS5_A eMIOS15 PF15 eMIOS14 PF14 eMIOS13 PF13 eMIOS12 PF12 ADDR4 ADDR5 ADDR6 ADDR7 eMIOS11 PF11 eMIOS10 PF10 eMIOS9 eMIOS8 eMIOS7
MAC7111 LQFP
AN9_A AN8_A AN7_A AN6_A RDY' AN5_A MSEO' AN4_A MDO1' AN3_A MDO0' AN2_A EVTI' AN1_A EVTO' AN0_A MCKO' DATA7 DATA8 DATA9 PA10 DATA10 PA11 DATA11 PA12 DATA12 ADDR16 PC15 ADDR15 PC14 ADDR14 PC13 ADDR13 PC12 ADDR12 VDDX VSSX PD15 PD14 PD13 XIRQ CLKOUT XCLKS PB15 SIN_B PB14 SOUT_B PB13 SCK_B PB12 PCS1_B PB11 PCS2_B PB10 PCS5_B PCSS_B
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Device Assignments
VSSX VSSX PF14 PF12 PF11 VSSX
MAC7131VF Assignments
VSSX VSSX PG11 PF13 PF10 VSSX VSSX VSSX PG10 PF15 VSSX PG14 PG15 VSSX VSSX VSSX VSSX VDDX VSSX VSSX VSSX VSSX VSSX VSSR VSSR VSS2.5 VSS2.5 VSSPLL VSSPLL VSSX PC10 VDDX VSS2.5 VDDR PG12 PG13 VSSX VDDX VSSX PA15 TEST VSSX PD11 PA13 PA14 VSSX VSSX VSSX VSSX VSSX VSSX VSSX VSSX VSSX VSSX VSSX VSSX VSSX VSSX VSSX VSSX TCLK PE15 PE14 PH15 PH14 PE13 PH13 VSSA PE12 PH12 PE11 VSSA PH11 PE10 VDDA PH10 PC13 PD13 VSSX VSSX PD12 PA12 PC12 PD14 PB11 VSSX PB10 VDDA PA11 PC14 PD15 VDDA PA10 PC15 VDDX
VSS2.5 VDDX
VSSX VSS2.5 VSS2.5 PD10
CLKOUT PB14 PB12 VSSX VSSX PB15 PB13 VSSX VSSX
PC11 RESET VSSPLL
EXTAL XTAL
Figure Assignments MAC7131 208-pin
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Mechanical Information
Mechanical Information
100-Pin LQFP Package
0.05
0.20
0.20
-A-,-B-,-DDETAIL
DETAIL
-D0.20
0.05 0.20 -CSEATING PLANE
DETAIL -HDATUM PLANE
0.20
VIEW ROTATED
SECTION
0.10
DATUM-HPLANE
DETAIL
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DATUM PLANE LOCATED BOTTOM LEAD COINCIDENT WITH LEAD WHERE LEAD EXITS PLASTIC BODY BOTTOM PARTING LINE. DATUMS -A-, DETERMINED DATUM PLANE -H-. DIMENSIONS DETERMINED SEATING PLANE -C-. DIMENSIONS INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION 0.25 SIDE. DIMENSIONS INCLUDE MOLD MISMATCH DETERMINED DATUM PLANE -H-. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.08 TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT LOCATED LOWER RADIUS FOOT.
MILLIMETERS 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 -0.25 0.13 0.23 0.65 0.95 12.35 0.13 0.17 0.325 0.13 0.30 16.95 17.45 0.13 -16.95 17.45 0.35 0.45
Figure 100-Pin LQFP Mechanical Dimensions (Case 983)
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IDENT
112-Pin LQFP Package
0.20
TIPS
0.20
VIEW
108X
X=L,
VIEW
0.13
BASE METAL
ROTATED °COUNTERCLOCKWISE NOTES: DIMENSIONING TOLERANCING ASME Y14.5M, 1994. DIMENSIONS MILLIMETERS. DATUMS DETERMINED SEATING PLANE, DATUM DIMENSIONS DETERMINED SEATING PLANE, DATUM DIMENSIONS INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION 0.25 SIDE. DIMENSIONS INCLUDE MOLD MISMATCH. DIMENSION DOES INCLUDE MILLIMETERS 20.000 10.000 20.000 10.000 1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 0.090 0.170 0.500 0.325 0.100 0.200 0.100 0.200 22.000 11.000 22.000 11.000 0.250 1.000 0.090 0.160
SECTION J1-J1
0.050
VIEW 0.10
112X
SEATING PLANE
0.25
GAGE PLANE
VIEW
Figure 112-Pin LQFP Mechanical Dimensions (Case 987)
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144-Pin LQFP Package
0.20
TIPS
0.20
IDENT
140X
X=L,
VIEW
NOTES:
VIEW
VIEW
144X
DIMENSIONS TOLERANCING ASME Y14.5M, 1994. DIMENSIONS MILLIMETERS. DATUMS DETERMINED SEATING PLANE, DATUM DIMENSIONS DETERMINED SEATING PLANE, DATUM DIMENSIONS INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION 0.25 SIDE. DIMENSIONS INCLUDE MOLD MISMATCH DETERMINED DATUM PLANE DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLWABLE DAMBAR PROTRUSION SHALL CAUSE DIMENSION EXCEED 0.35. MILLIMETERS 20.00 10.00 20.00 10.00 1.40 1.60 0.05 0.15 1.35 1.45 0.17 0.27 0.45 0.75 0.17 0.23 0.50 0.09 0.20 0.50 0.25 0.13 0.20 0.13 0.20 22.00 11.00 22.00 11.00 0.25 1.00 0.09 0.16
SEATING PLANE
PLATING
0.05
0.08
BASE METAL
0.25
GAGE PLANE
VIEW
SECTION J1-J1 (ROTATED
Figure 144-Pin LQFP Mechanical Dimensions (Case 918)
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Mechanical Information
208-Pin Package
LASER MARK IDENTIFICATION THIS AREA
NOTES: DIMENSIONS MILLIMETERS. INTERPRET DIMENSIONS TOLERANCES ASME Y14.5M, 1994. DIMENSION MEASURED MAXIMUM SOLDER BALL DIAMETER, PARALLEL DATUM PLANE DATUM (SEATING PLANE) DEFINED SPHERICAL CROWNS SOLDER BALLS. PARALLELISM MEASEMENT SHALL EXCLUDE EFFECT MARK SURFACE PACKAGE.
MILLIMETERS -2.00 0.40 0.60 1.00 1.30 0.50 0.70 17.00 17.00 1.00 0.50
208X
METALIZED MARK IDENTIFICATION THIS AREA
208X
VIEW
VIEW
(ROTATED CLOCKWISE)
Figure 208-Pin Mechanical Dimensions (Case 1159A-01)
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EUROPE Locations Listed: Motorola Literature Distribution P.O. 5405 Denver, Colorado 80217 1-800-521-6274 480-768-2130 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo, 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre King Street Industrial Estate N.T., Hong Kong 852-26668334 HOME PAGE:
Information this document provided solely enable system software implementers Motorola products. There express implied copyright licenses granted hereunder design fabricate integrated circuits integrated circuits based information this document. Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. MOTOROLA Stylized Logo registered U.S. Patent Trademark Office. other product service names property their respective owners. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. Motorola, Inc. 2003
MAC7100EC/D, Rev. 0.1,
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REACH
EUROPE Locations Listed: Motorola Literature Distribution P.O. 5405 Denver, Colorado 80217 1-800-521-6274 480-768-2130 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo, 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre King Street Industrial Estate N.T., Hong Kong 852-26668334 HOME PAGE:
Information this document provided solely enable system software implementers Motorola products. There express implied copyright licenses granted hereunder design fabricate integrated circuits integrated circuits based information this document. Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. MOTOROLA Stylized Logo registered U.S. Patent Trademark Office. other product service names property their respective owners. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. Motorola, Inc. 2003
MAC7100EC/D, Rev. 0.1,
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