32-Bit Proprietary Microcontroller FR60 MB91301 Series MB91301/30

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32-Bit Proprietary Microcontroller FR60 MB91301 Series MB91301/30

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DS07-16502-2E
32-Bit Proprietary Microcontroller
FR60 MB91301 Series MB91301/302A/V301/V301A
DESCRIPTION
MB91301 series line microcontrollers based 32-bit RISC core family) incorporating variety resources control mechanism embedded control that requires processing high-performance, fast well SDRAM interface that connect SDRAM directly chip. large address space supported 32-bit addressing means that operation primarily based external access although large internal area included high-speed execution instructions. MB91301 MB91V301 FR60 series products based FR30/40 series with enhanced access higher speed operation. device specifications include converter facilitate motor control ideal players that support fly-by transfer.
FEATURES
MB91301 series line with various programs embedded internal ROM.
variation Product name
Built-in real Built-in time version (Internal Program Loader) version
User version
Without version
MB91302A MB91301
(Continued)
PACKAGE
144-pin, Plastic LQFP 179-pin, Ceramic
(FPT-144P-M12)
(PGA-179C-A03)
MB91301 Series
32-bit RISC, load/store architecture, 5-stage pipeline internal operating frequency (Max) [external (Max) MHz] (when using with base frequency (Max) MHz) General purpose registers 16-bit fixed length instructions (basic instructions) instruction cycle Instruction optimized embedded applications: Memory-to-memory transfer, manipulation, barrel shift etc. Instructions adapted high-level languages Function entry/exit instructions, multiple-register load/store instructions Easier assembler coding Register interlock function Branch instructions with delay slots Reduced overhead time branch executions Built-in multiplier with instruction-level support Signed 32-bit multiplication cycles Signed 16-bit multiplication cycles Interrupt (PC, save) cycles, priority levels
interface
Operating frequency (when using SDRAM) Full 24-bit address output memory space) 8-bit, 16-bit 32-bit data input/output Built-in pre-fetch buffer Unused data address pins used general-purpose input/output ports. Eight fully independent chip select outputs, minimum units. Supports following memory interfaces Asynchronous SRAM, asynchronous ROM/Flash Page mode ROM/Flash (selectable page size Burst mode ROM/Flash (MBM29BL160D/161D/162D) SDRAM (FCRAM Type, Latency bank products.) Address/Data multiplex (only 8/16-bit width) Basic cycle cycles Automatic wait cycle generation function insert wait cycles, independently programmable each memory area. input external wait cycles Endian setting byte ordering (Big/Little) area only endian Prohibition setting write (only Read) Permission/prohibition setting fetch into built-in cache Permission/prohibition setting prefetch function supports fly-by transfer with independent wait control External arbitration used using BGRNT.
Built-in memory
DATA (MB91302A) MB91V301: Built-in DATA DATA/instruction MB91V301A: Built-in DATA RAM, DATA/instruction emulation
(Continued)
MB91301 Series
Instruction cache (MB91V301 only)
Size 2-way associative blocks/way, entries/block Lock function enables program code made cache-resident Areas used instruction cache used instruction 5-channel (2-channel external-to-external) transfer triggers External pin, internal peripheral, software Capable selecting internal peripheral transfer source freely each channel Addressing using 32-bit full addressing mode (increment, decrement, fixed) Transfer modes Demand transfer, burst transfer, step transfer, block transfer Supports fly-by transfer (between external memory) Selectable transfer data size 32-bit
DMAC (DMA Controller)
search module
Searches words from position first value change
Reload Timers
16-bit timer channels Internal clock clock cycle resolution, divide 2/8/32 selective
UART
Full duplex, double buffer UART Independent channels Data length bits bits (without parity) bits bits (with parity) Asynchronous (start-stop synchronized) CLK-synchronous communications selectable Multi-processor mode Built-in 16-bit timer (U-TIMER) baud rate generator generate arbitrary baud rates External clock used transfer clock Variety error detection functions (parity, frame, overrun)
Interrupt controller
External interrupt input non-maskable interrupt normal interrupt pins (INT0 INT7) Internal internal resources UART, DMAC, A/D, UTIMER, Delay interrupt, I2C, Free-run timer, I2C, Free-run timer only MB91302A MB91V301A. Programmable priorities levels) interrupts except non-maskable interrupt
converter
10-bit resolution, channels Successive approximation type, conversion time Built-in sample hold circuit Conversion modes Single conversion mode, scan conversion mode repeat conversion mode selectable Conversion triggers Software, external trigger built-in timer selectable
I2C* interface
Internal 2-ch master/slave transmit/receive Internal arbitration function, clock synch function interface function only MB91302A MB91V301A.
Free-run timer
1channel Free-run timer function only MB91302A MB91V301A.
(Continued)
MB91301 Series
(Continued)
Input capture
channel Input capture function only MB91302A MB91V301A.
Other interval timers
16-bit timer channels (U-TIMER) timer channels Watchdog timer channel
Other features
Reset resources watchdog timer/software reset/external reset (INIT pin) Power-saving modes Stop mode, sleep mode Clock control Gear function Allows arbitrary different operating clock frequencies peripherals. select gear clock factors 1/16. multiplication also selected. Note, however, that peripherals operate maximum MHz. Packages MB91301 FPT-144P-M12, MB91V301 PGA-179C-A03 CMOS technology 0.25 Power supply (analog power supply): (internal regulator used) Purchase Fujitsu components conveys license under Philips Patent Rights use, these components system provided that system conforms Standard Specification defined Philips.
MB91301 Series
PRODUCT LINEUP
MB91301 Type MB91V301 MB91302A Mask product (for volume production) (only data) non-ROM model, optimal real time internal model*1, (Internal Program Loader) internal model*2 adding user model. LQFP-144 (0.4 pitch) Currently production MB91V301A Evaluation version (For evaluation development) (data KB+8 Evaluation version External version (For evaluation (for volume production) development) (only data) (data KB+8
(RAM)
Package Other
LQFP-144 (0.4 pitch) Currently production
DSU4 PGA-179 Currently available
DSU4 PGA-179 Currently available
Fujitsu product real time REALOS/FR conforming µITORN stored optimized with MB91302A. stores (Internal Program Loader) Loading various programs executed from external system internal UART/SIO. Using this function, example, writing board Flash memory connected external executed.
MB91301 Series
ASSIGNMENTS
MB91301/MB91302A
(TOP VIEW)
Note SDA0, SCL0, SDA1 SCL1 ICU0 ICU3 FRCK function only MB91302A.
P91/MCLKE P92/MCLK P94/SRAS/LBA/AS P95/SCAS/BAA P96/SWE/WR P60/A16 P61/A17 P62/A18 P63/A19 P64/A20/SDA0 P65/A21/SCL0 P66/A22/SDA1 P67/A23/SCL1
P13/D11 P14/D12 P15/D13 P16/D14 P17/D15 P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23 P80/RDY P81/BGRNT P82/BRQ DQMUU/WR0(UUB) P85/DQMUL/WR1(ULB) P86/DQMLU/WR2(LUB) P87/DQMLL/WR3(LLB) P90/SYSCLK
D10/P12 D09/P11 D08/P10 D07/P07 D06/P06 D05/P05 D04/P04 D03/P03 D02/P02 D01/P01 D00/P00 CS7/PA7 CS6/PA6 CS5/PPG2/PA5 CS4/TRG2/PA4 CS3/PA3 CS2/PA2 CS1/PA1 CS0/PA0 INIT IORD/PB7 IOWR/PB6
DEOP1/PPG1/PB5 DACK1/TRG1/PB4 DREQ1/PB3 DEOP0/PB2 DACK0/PB1 DREQ0/PB0 TIN2/TRG3/PH2 TIN1/PPG3/PH1 TIN0/PH0 TRG0/PJ7 PPG0/PJ6 SCK1/PJ5 SOT1/PJ4 SIN1/PJ3 SCK0/PJ2 SOT0/PJ1 SIN0/PJ0 INT7/SCK2/PG7 INT6/SOT2/PG6 INT5/SIN2/PG5 INT4/ATG/PG4/FRCK INT3/PG3/ICU3 INT2/PG2/ICU2 INT1/PG1/ICU1 INT0/PG0/ICU0 AVSS/AVRL AVRH AVCC
(FPT-144P-M12)
MB91301 Series
MB91V301/MB91V301A (TOP VIEW)
INDEX
(PGA-179C-A03)
MB91301 Series
MB91V301 Table Name N.C. P13/D11 P14/D12 P15/D13 P16/D14 P17/D15 P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23
Name P80/RDY P81/BGRNT P82/BRQ DQMUU/WR0 (UUB) P85/DQMUL/WR1 (ULB) P86/DQMLU/WR2 (LUB) P87/DQMLL/WR3 (LLB) P90/SYSCLK P91/MCLKE P92/MCLK P94/SRAS/LABA/AS P95/SCAS/BAA P96/SWE/WR
Name P60/A16 P61/A17 P62/A18 P63/A19 SDA0/P64/A20 SDA0;MB91V301A SCL0/P65/A21 SCL0;MB91V301A SDA1/P66/A22 SDA1;MB91V301A SCL1/P67/A23 SCL1;MB91V301A EWR3 EWR2 EWR1 EWR0 EMRAM ICD3
(Continued)
MB91301 Series
Name ICD2 ICD1 ICD0 BREAK ICLK ICS2 ICS1 ICS0 TRST AVCC AVRH AVSS/AVRL INT0/PG0/ICU0 ICU0;MB91V301A INT1/PG1/ICU1 ICU1;MB91V301A INT2/PG2/ICU2 ICU2;MB91V301A INT3/PG3/ICU3 ICU3;MB91V301A INT4/ATG/PG4/FRCK FRCK;MB91V301A INT5/SIN2/PG5 INT6/SOT2/PG6 INT7/SCK2/PG7 SIN0/PJ0
Name SOT0/PJ1 SCK0/PJ2 SIN1/PJ3 SOT1/PJ4 SCK1/PJ5 PPG0/PJ6 TRG0/PJ7 TIN0/PH0 TIN1/PPG3/PH1 TIN2/TRG3/PH2 DREQ0/PB0 DACK0/PB1 DEOP0/PB2 DREQ1/PB3
Name INIT CS0/PA0 CS1/PA1 CS2/PA2 CS3/PA3 CS4/TRG2/PA4 CS5/PPG2/PA5 CS6/PA6 CS7/PA7 D00/P00 D01/P01 D02/P02 D03/P03 D04/P04 D05/P05 D06/P06 D07/P07 D08/P10 D09/P11 D10/P12
DACK1/TRG1/PB4 DEOP1/PPG1/PB5 IOWR/PB6 IORD/PB7
MB91301 Series
DESCRIPTIONS
Except Power supply, GND, Tool pins
MB91301/ MB91V301/ 302A V301A 169, name
circuit type MB91301, MB91V301 MB91302A, MB91V301A Function External data bits available external mode. used ports 8-bit 16-bit external mode. External data bits available external mode. used ports 8-bit 16-bit external mode. External data bits available external mode. used ports 8-bit external mode. External data bits available external mode. [RDY] External ready input. this function when external ready input enabled. [P80] General purpose input/output port. this function when external ready input disabled. [BGRNT] Acknowledge output external release. Outputs when external released. this function when output enabled. [P81] General purpose input/output port. this function when output disabled external release acknowledge. [BRQ] External release request input. Input request release external bus. this function when input enabled. [P82] General purpose input/output port. this function when external release request input disabled. [RD] External read strobe output.
144, 180,
BGRNT
(Continued)
MB91301 Series
MB91301/ MB91V301/ 302A V301A name
circuit type MB91301, MB91V301 MB91302A, MB91V301A Function [WR0] External write strobe output. When used write strobe, this becomes byte-enable (UUB). Select signal (DQMUU) using SDRAM. [WR1] External write strobe output. this function when output enabled. When used write strobe, this becomes byte-enable (ULB). Select signal (DQMUL) using SDRAM. [P85] General purpose input/output port. this function when external write-enable output disabled. [WR2] External write strobe output. this function when output enabled. When used write strobe, this becomes byte-enable (LUB). Select signal (DQMLU) using SDRAM. [P86] General purpose input/output port. this function when external write-enable output disabled. [WR3] External write strobe output. this function when output enabled. When used write strobe, this becomes byte-enable (LLB). Select signal (DQMLL) using SDRAM. [P87] General purpose input/output port. this functions when external write-enable output disabled. [SYSCLK] System clock output. this function when system clock output enabled. This outputs same clock external operating frequency. (Output halts stop mode.) [P90] General purpose input/output port. this function when system clock output disabled.
WR0/ (UUB) DQMUU
WR1/ (ULB) /DQMUL
WR2/ (LUB) /DQMLU
WR3/ (LLB) /DQMLL
SYSCLK
(Continued)
MB91301 Series
MB91301/ MB91V301/ name 302A V301A MCLKE
circuit type MB91301, MB91V301 MB91302A, MB91V301A Function [MCLKE] Clock enable signal memory. [P91] General purpose input/output port. this function when clock enable output disabled. [MCLK] Memory clock output. this function when memory clock output enabled. This outputs same clock external operating frequency. (Output halts sleep mode.) [P92] General purpose input/output port. this function when memory clock output disabled. [P93] General purpose input/output port. [AS] Address strobe output. this function when port function register enabled "1". [LBA] Address strobe output burst flash ROM. this function when port function register enabled "1". SRAS [SRAS] single SDRAM. This this function when port function register enabled "1". [P94] General purpose input/output port. this function when port function register general purpose port. [BAA] Address advance output burst Flash ROM. this function when BAAE port function register enabled. [SCAS] signal SDRAM. This this function when BAAE port function register enabled. [P95] General purpose input/output port. this function when BAAE port function register general purpose port.
MCLK
SCAS
(Continued)
MB91301 Series
MB91301/ MB91V301/ name 302A V301A
circuit type MB91301, MB91V301 MB91302A, MB91V301A Function [WR] Memory write strobe output. This this function when WEXE port function register enabled. [SWE] Write output SDRAM. This this function when WEXE port function register enabled. [P96] General purpose input/output port. This this function when WEXE port function register general purpose port. External address External address External address available external mode. used ports when external address used. [SDA0] Data input function. This function enable when typical operation enable. port output must remains unless intentionally turned (Open drain output) (This function only MB91302A, MB91V301A.) [A20] External address This function enable during prohibited operation using external bus. [P64] General-purpose port. This function enable during prohibited nonused external address bus. [SCL0] input I2Cbus function. This function enable when typical operation enable. port output must remains unless intentionally turned (open drain output) (This function only MB91302A, MB91V301A.) [A21] External address This function enable during prohibited operation using external bus. [P65] General-purpose port. This function enable during prohibited nonused external address bus.
SDA0
SCL0
(Continued)
MB91301 Series
MB91301/ MB91V301/ name 302A V301A
circuit type MB91301, MB91V301 MB91302A, MB91V301A Function [SDA1] DATA input function. This function enable when typical operation enable. output must remains unless intentionally turned (open drain output) (This function only MB91302A, MB91V301A.) [A22] External address This function enable during prohibited operation using external bus. [P66] General-purpose port. This function enable during prohibited nonused external address bus. [SCL1] input function. This function enable when typical operation enable. port output must remains unless intentionally turned (open drain output) (This function only MB91302A, MB91V301A.) INT0 INT3 [A23] External address This function enable during prohibited operation using external bus. [P67] General-purpose port. This function enable during prohibited operation nonused external address bus. Analog input pin. [INT0 INT3] External interrupt inputs. These inputs used continuously when corresponding external interrupt enabled. this case, output these ports unless doing intentionally. [PG0 PG3] General purpose input/ output ports. [ICU0 ICU3] Input capture input pins. These inputs used continuously when selected input capture inputs. this case, output these ports unless doing intentionally. (This function only MB91302A MB91V301A.)
SDA1
SCL1
ICU0 ICU3
(Continued)
MB91301 Series
MB91301/ MB91V301/ name 302A V301A
circuit type MB91301, MB91302A, MB91V301 MB91V301A
Function [INT4] External interrupt input. These inputs used continuously when corresponding external interrupt enabled. this case, output these ports unless doing intentionally. [ATG] External trigger input converter. This input used continuously when selected converter start trigger. this case, output this port unless doing intentionally. [PG4] General purpose input/output ports. [FRCK] External clock input free-run timer. This input used continuously when selected external clock input free-run timer. this case, output this port unless doing intentionally. (This function only MB91302A MB91V301A.) [INT5] External interrupt input. These inputs used continuously when corresponding external interrupt enabled. this case, output these ports unless doing intentionally. [SIN2] UART2 data input pin. This input used continuously when UART2 performing input. this case, output this port unless doing intentionally. [PG5] General purpose input/output port. [INT6] External interrupt input. This input used continuously when corresponding external interrupt enabled. this case, output these ports unless doing intentionally. [SOT2] UART2 data output pin. this function when UART2 data output enabled. [PG6] General purpose input/output port. [INT7] External interrupt input. This input used continuously when corresponding external interrupt enabled. this case, output these ports unless doing intentionally. [SCK2] UART2 clock input/output pin. this function when UART2 clock output enabled. [PG7] General purpose input/output port. (Continued)
INT4
FRCK
INT5 SIN2
INT6 SOT2
INT7 SCK2
MB91301 Series
MB91301/ MB91V301/ name 302A V301A
circuit type MB91301, MB91V301 MB91302A, MB91V301A Function [SIN0] UART0 data input pin. This input used continuously when UART0 performing input. this case, output this port unless doing intentionally. [PJ0] General purpose input/output port. [SOT0] UART0 data output pin. this function when UART0 data output enabled. [PJ1] General purpose input/output port. [SCK0] UART0 clock input/output pin. this function when UART0 clock output enabled. [PJ2] General purpose input/output port. [SIN1] UART1 data input pin. This input used continuously when UART1 performing input. this case, output this port unless doing intentionally. [PJ3] General purpose input/output port. [SOT1] UART1 data output pin. this function when UART1 data output enabled. [PJ4] General purpose input/output port. [SCK1] UART1 clock input/output pin. this function when UART1 clock output enabled. [PJ5] General purpose input/output port. [PPG0] timer output. This this function when PPG0 output enabled. [PJ6] General purpose input/output port. [TRG0] External trigger input timer. This input used continuously when corresponding timer input enabled. this case, output this port unless doing intentionally. [PJ7] General purpose input/output port. [TIN0] Reload timer input. This input used continuously when corresponding timer input enabled. this case, output this port unless doing intentionally. [PH0] General purpose input/output port.
SIN0
SOT0 SCK0
SIN1
SOT1 SCK1 PPG0
TRG0
TIN0
(Continued)
MB91301 Series
MB91301/ MB91V301/ name 302A V301A TIN1 PPG3 TIN2
circuit type MB91301, MB91V301 MB91302A, MB91V301A Function [TIN1] Reload timer input. This input used continuously when corresponding timer input enabled. this case, output this port unless doing intentionally. [PPG3] timer output. this function when PPG3 output enabled. [PH1] General purpose input/output port. [TIN2] Reload timer input. This input used continuously when corresponding timer input enabled. this case, output this port unless doing intentionally. TRG3 [TRG3] External trigger input timer. This input used continuously when corresponding timer input enabled. this case, output this port unless doing intentionally. [PH2] General purpose input/output port. [DREQ0] External input transfer requests. This input used continuously when selected activation trigger. this case, output this port unless doing intentionally. [PB0] General purpose input/output port. [DACK0] External acknowledge output transfer requests. this function when outputting transfer request acknowledgement enabled. [PB1] General purpose input/output port. [DEOP0] Completion output external transfer. this function when outputting transfer completion enabled. [PB2] General purpose input/output port.
DREQ0
DACK0 DEOP0
(Continued)
MB91301 Series
MB91301/ MB91V301/ name 302A V301A
circuit type MB91301, MB91V301 MB91302A, MB91V301A Function [DREQ1] External input transfer requests. This input used continuously when selected activation trigger. this case, output this port unless doing intentionally. [PB3] General purpose input/output port. this function when completion output stop input disabled transfer. [DACK1] External acknowledge output transfer requests. this function when outputting transfer request acknowledgement enabled. TRG1 [TRG1] External trigger input timer. This input used continuously when corresponding timer input enabled. this case, output this port unless doing intentionally. [PB4] General purpose input/output port. [DEOP1] Completion output external transfer. this function when outputting transfer completion enabled. [PPG1] timer output. this function when PPG1 enabled. [PB5] General purpose input/output port. [IOWR] Write strobe output fly-by transfer. this function when outputting write strobe fly-by transfer enabled. [PB6] General purpose input/output port. this function when outputting write strobe fly-by transfer disabled. [IORD] Read strobe output fly-by transfer. this function when outputting read strobe fly-by transfer disabled. [PB7] General purpose input/output port. this function when outputting write strobe fly-by transfer disabled. Clock (oscillation) input.
DREQ1
DACK1
DEOP1 PPG1 IOWR
IORD
(Continued)
MB91301 Series
MB91301/ MB91V301/ name 302A V301A INIT
circuit type MB91301, MB91V301 MB91302A, MB91V301A Function Clock (oscillation) output. [MD0 MD2] Mode pins levels applied these pins basic operating mode. Connect VSS. External reset input (Reset initialize settings) ("L" active) (Non Maskable Interrupt) input ("L" active) [CS0] Chip select output. this function when chip select output enabled. [PA0] General purpose input/output port. this function when chip select output disabled. [CS1] Chip select output. this function when chip select output enabled. [PA1] General purpose input/output port. this function when chip select output disabled. [CS2] Chip select output. this function when chip select output enabled. [PA2] General purpose input/output port. this function when chip select output disabled. [CS3] Chip select output. this function when chip select output enabled. [PA3] General purpose input/output port. this function when chip select output disabled. [CS4] Chip select output. this function when chip select output enabled. [TRG2] External trigger input timer. This input used continuously when corresponding timer input enabled. this case, output this port unless doing intentionally. [PA4] General purpose input/output port. this function when chip select output disabled.
TRG2
(Continued)
MB91301 Series
(Continued)
MB91301/ MB91V301/ name 302A V301A PPG2
circuit type MB91301, MB91V301 MB91302A, MB91V301A Function [CS5] Chip select output. this function when chip select output enabled. [PPG2] timer output. this function when PPG2 enabled. [PA5] General purpose input/output port. this function when chip select output timer outputare disabled. [CS6] Chip select output. this function when chip select output enabled. [PA6] General purpose input/output port. this function when chip select output disabled. [CS7] Chip select output. this function when chip select output enabled. [PA7] General purpose input/output port. this function when chip select output disabled.
Shaded pins only present MB91V301.
Power supply pins
MB91301 101, 114, 130, MB91V301 131, 142, 145, 154, 164, 170,
name
Function pins. Connect pins same potential.
119, 141, 111, 115, 146, 150, 151, 155, 165, 121, 131, 171, 102,
power supply pins. Connect pins same potential. Analog power supply converter Reference power supply converter Capacitor coupling converter Analog converter Open pin. open Capacitor coupling internal regulator
AVCC AVRH AVSS/AVRL OPEN
MB91301 Series
Tool pins
MB91301 MB91V301
name ICLK TRST ICS2 ICS0 ICD3 ICD0 BREAK EMRAM EWR3 EWR0
circuit type Clock output Tool reset
Function
Device status output (during TRC) DSU4 operation status output (during EML) Trace information output (during TRC) Program/data (duuring EML) DSU4 break reqest input Emulation memory detection Chip select emuration memory Write strobe emuration memory
MB91301 Series
CIRCUIT TYPE
Type
Circuit
Remarks Oscillation feedback resistance approx. Clock input
Standby control CMOS hysteresis input with pull-up resistor Pull-up resistor approx. (Typ)
Digital input CMOS level with standby control
Digital output Digital output
Digital input Standby control Analog input With switch
Analog input Control
(Continued)
MB91301 Series
Type
Circuit
Remarks CMOS level output standby control
Digital input Pull-up control Digital output Digital output With Pull-up control Pull-up resistor value approx. (Typ) CMOS level with standby control With Pull-up control
Digital input Standby control Pull-up control Digital output Digital output With Pull-up control Pull-up resistor value approx. (Typ) CMOS level output CMOS level hysteresis input with standby control
Digital input Standby control Pull-up control Digital output Digital output With Pull-up control Pull-up resistor value approx. (Typ) CMOS level output CMOS level hysteresis input standby control
Digital input CMOS level hysteresis input standby control
Digital input
(Continued)
MB91301 Series
Type
Circuit
Remarks Output buffer CMOS level output
Digital output Digital output
Digital input
Input buffer CMOS level input Input buffer with pull-down Pull-down resistor value approx. (Typ)
Digital input
Input buffer with Pull-up Pull-up resistor value approx. (Typ) Digital input
Digital output Digital output
buffer with pull-down CMOS level output Pull-up resistor value approx. (Typ)
Digital input buffer CMOS level output
Digital output Digital output
Digital input
(Continued)
MB91301 Series
(Continued) Type
Circuit Pull-up control Digital output with open-drain control Digital output
Remarks open-drain output CMOS level with standby control Without pull-up control Pull-up resistor value approx. (Typ)
Digital input
STANDBY CONTROL
Digital output Digital output Digital input
STANDBY CONTROL
CMOS level output CMOS level hysteresis input with standby control tolerant
Digital output Digital output Digital input
CMOS level output CMOS level hysteresis input with standby control tolerant
MB91301 Series
HANDLING DEVICES
rMB91301 series Operation start-up Always apply settings initialization (INIT) INIT immediately after turning power. Also, order provide delay while oscillator circuits stabilize immediately after start-up, maintain level input INIT required stabilization delay time. (The initialization processing (INIT) triggered INIT initializes oscillation stabilization delay time minimum setting.) External clock input start-up power-on start-up, always input clock signal until oscillation stabilization delay time ended. Output indeterminate power-on time When power turned output remain indeterminate until internal power supply becomes stable. Built-in DC/DC regulator This device built-in regulator, requiring input bypass capacitor approximately connected regulator.
AVCC AVRH 0.05 AVSS/AVRL MB91301 series
Note built-in DC/DC regulator
Note converter MB91301 series contains converter, sure supply power AVcc insert capacitor least 0.05 between AVss/AVRL pin.
AVCC AVRH AVSS/AVRL MB91301 series
0.05
Note Converter
MB91301 Series
Preventing Latchup When CMOS integrated circuit devices subjected applied voltages higher than input output pins, voltages lower than VSS, well when voltages excess rated levels applied between VSS, phenomenon known latchup occur. When latchup condition occurs, supply current increase dramatically destroy semiconductor elements. using semiconductor devices, always take sufficient care avoid exceeding maximum ratings. Power supply pins Devices with multiple supply pins designed prevent problems such latchup occurring providing internal connections between pins same potential. However, order reduce unwanted radiation, prevent abnormal operation strobe signals rise ground level, maintain total output current ratings, such pins should always connected externally power supply ground. Also, ensure that impedance connections power supply possible. addition, recommended that bypass capacitor approximately 0.1µF connected between VSS. Connect capacitor close pins. Crystal oscillators Noise proximity pins cause abnormal operation this device. Printed circuit boards should designed that pins, crystal ceramic) oscillator, bypass capacitor connected ground placed close together possible. Also, ensure stable operation, strongly recommended that printed circuit board work designed such that pins surrounded ground. Treatment OPEN pins Pins marked "NC" "OPEN" must left open-circuit. Treatment unused input pins unused input pins left open, abnormal operation result. unused input pins should connected pull-up pull-down resistors. Mode pins (MD0 MD2) These pins should connected directly VSS. prevent device erroneously switching test mode noise, design printed circuit board such that distance between mode pins short possible connection impedance low. Remarks External Clock Operation When external clock selected, supply generally, simultaneously opposite phase clock must supplied pin. However, this case stop mode must used (because stops output stop mode) When operating 12.5 less, microcontroller used with clock signal supplied only "Using external clock (normal) (12.5 MHz) shows examples MB91301 uses external clock.
MB91301 Series
MB91301 series
Note: Stop mode (oscillation stop mode) used. Using external clock (normal)
OPEN
MB91301 series
Using external clock (12.5 Max)
Notes during operation clock mode clock mode selected, microcontroller attempt working with self-oscillating circuit even when there external oscillator external clock input stopped. Performance this operation, however, cannot guaranteed. Clock control block L-level input INIT pin, allow regulator settling time oscillation settling time. search module 0-detection, 1-detection, transition-detection data registers (BSD0, BSD1, BSDC) only wordaccessible. port access Byte access only access port Shared port function switching switch that also serves port, port function register (PFR). Note, however, that pins switched depending external settings. D-bus memory code area D-bus memory. instruction fetch performed D-bus. Instruction fetches D-bus area result incorrect data interpreted code, which cause microcontroller lose control. data area I-bus memory.
MB91301 Series
I-bus memory stack area vector table I-bus memory. cause hang during processing (including RETI). Recovery from hang requires reset. perform transfer I-bus memory. Low-power consumption modes enter standby mode, synchronous standby mode (set with SYNCS TBCR, time-base counter control register) sure following sequence: (LDI #value_of_standby, (LDI #_STCR, R12) @R12 Write standby control register (STCR) LDUB @R12, Read STCR synchronous standby LDUB @R12, Read STCR again dummy read timing adjustment I-flag registers branch interrupt handler when interrupt handler triggers microcontroller return from standby mode. monitor debugger, follow precautions below: breakpoint within above array instructions. single-step above array instructions. Prefetch When accessing prefetch-enabled little endian area, word access only (access bits). Byte halfword access results wrong data read. MCLK SYSCLK MCLK causes stop SLEEP/STOP mode while SYSCLK causes stop only STOP mode. either depending each application. Pull-up control When function pins listed specifications (such external control pins) have pull-up control, enabling pull-up resistor causes actual load conditions change. specifications this device were measured under condition pull-up resistors disabled, values guaranteed specifications when pull-up resistors enabled. Even pull-up resistor enabled pin, standby control register (STCR) specifies setting output pins high impedance during stop mode (HIZ changing stop mode (STOP causes pull-up resistor disabled.
MB91301 Series
(General purpose register) When following instructions executed, SSP* USP* value used R15, resulting incorrect value written memory. R15, ANDH R15, ANDB R15, R15, R15, R15, R15, EORH R15, EORB R15, XCHB @Rj, virtual register. When program attempts access R15, accessed depending status flag flag. When coding above instructions using assembler, specify general-purpose register other than R15. RETI instruction Please neither control register instruction cache data access instruction cache immediately before instruction RETI. Notes register Since some instructions manipulate register earlier, following exceptions cause interrupt handler break flag update display setting when debugger being used. microcontroller designed carry reprocessing correctly upon returning from such event, performs operations before after specified either case. following operations performed when instruction immediately followed DIVOU/DIVOS instruction halted user interrupt NMI, single-stepped, breaks response data event emulator menu: flags updated earlier. handler (user interrupt/NMI emulator) executed. Upon returning from EIT, DIVOU/DIVOS instruction executed flags updated same values those above. following operations performed when ORCCR/STILM/MOV instructions executed enable interruptions when user interrupt trigger event occurred. register updated earlier. handler (user interrupt/NMI emulator) executed. Upon returning from EIT, above instructions executed register updated same value that above. converter When device turned returns from reset stop, takes time external capacitor charged, requiring converter wait least Watchdog timer watchdog timer function this model monitors that program delays reset within certain period time resets program fails delay example, because program runs control. Once watchdog timer function enabled, therefore, watchdog timer countinues operate until reset takes place. exception, example during stop, sleep transfer modes, automatic delaying reset under condition which stops program execution. Note, however, that watchdog reset occur above state caused when system runs control. this case, external INIT cause reset (INIT)
MB91301 Series
rUnique evaluation chip MB91V301 Tool reset evaluation board, chip with INIT TRST connected together. Simultaneous occurrences software break user interrupt/NMI When software break user interrupt /NMI take place same time, emulator debugger cause following phenomena: debugger stops pointing location other than programmed breakpoints. halted program re-executed correctly. these phenomena occur, hardware break instead software break. monitor debugger been used, avoid setting break relevant location. Single-stepping RETI instruction interrupt occurs frequently during single stepping, execute only relevant processing routine repeatedly after single-stepping RETI. This will prevent main routine low-interrupt-level programs from being executed. single-step RETI instruction avoidance purposes. When debugging relevant interrupt routine becomes unnecessary, perform debugging with that interrupt disabled. Operand break stack pointer placed area operand break cause malfunction. apply data event break access area containing address system stack pointer. startup sequence When using ICE, when start debugging, ensure that configuration correctly area being used before downloading. After turning power target, states pins undefined until perform above setting. Accordingly, include enabling pull-up part startup sequence. using these pins general-purpose ports, output ports prevent conflict with output signals during time states undefined. External width name (P85) (P86) (P87) output ports.
Pull-up Pull-up Pull-up Pull-up Pull-up
Pull-up Pull-up Pull-up
Pull-up Pull-up
MB91301 Series
Configuration batch file example batch file below sets mode vector sets configuration register download area. values appropriate hardware wait, timing, other settings. MODR (0x7fd) =Enable memory+16 External mem/byte 0x7fd=0x5 ASR0 (0x640) 0x0010_0000 0x002f_ffff mem/halfword 0x640=0x0010 ACR0 (0x642) [3:0]=0101:2 MByte [1:0]=01:16 width, automatically from MODR [1:0]=00:1 burst SREN=0:Disable PFEN=1:Enable fetch buffer WREN=1:Enable Write operation LEND=0: endian TYPE [3:0]=0010:WEX: Disable mem/harfword 0x642=0x5462 AWR0 (0x660) W15-12=0010:auto wait=2 WR07, 06=01:RD, delay=1cycle W05, 04=01:WR->WR delay=1cycle (for WEX) =1:MCLK->RD/WR delay=0.5cycle :for async Memory =0:ADR->CS delay=0 =0:ADR->RD/WR setup 0cycle =RD/WR->ADR hold 0cycle mem/halfword 0x660=0x2058 Emulation memory SRAM emulation memory built target board, SRAM accessed signal, +BYTE control signal used. (The external initialized mode accessing after reset.)
MB91301 Series
BLOCK DIAGRAM
MB91301, MB91V301
Core
I-Cache
DREQ0, DREQ1 DACK0, DACK1 DEOP0, DEOP1 IOWR IORD
search (stack) Converter
DMAC
INIT
Adapter Clock control
External memory
BGRNT SYSCLK MCLK MCLKE SRAS SCAS DQMUU, DQMLU,L PPG0 PPG3 TRG0 TRG3
Interrupt controller
SDRAM INT0 INT7 SIN0 SIN2 SOT0 SOT2 SCK0 SCK2
External interrupts
UART
timer
U-TIMER
PORT
AVR, AVRH, AVCC AVSS/AVRL TIN0 TIN2
PORT
Reload timer
MB91301 Series
MB91302A, MB91V301A
Core
I-Cache
DREQ0, DREQ1 DACK0, DACK1 DEOP0, DEOP1 IOWR IORD
search
MB91302A MB91V301A (stack)
DMAC
MB91302A MB91V301A
Converter
INIT
Adapter
External memory
Clock control
BGRNT SYSCLK MCLK MCLKE SRAS SCAS DQMUU, DQMLU,L PPG0 PPG3 TRG0 TRG3
Interrupt controller
SDRAM INT0 INT7 SIN0 SIN2 SOT0 SOT2 SCK0 SCK2
External interrupts
UART
timer
U-TIMER
PORT
AVRH, AVCC AVSS/AVRL TIN0 TIN2
Reload timer
PORT
SDA0, SDA1 SCL0, SCL1
Free Timer
FRCK
ICU0 ICU3
non-ROM model, optimal real time internal model, (Internal Program Loader) internal model adding user model.
MB91301 Series
Memory Space
family (232 addresses) logical address space with linear access from CPU. Direct Addressing Areas following areas address space used operations. These areas called direct addressing areas, which address operand specified directly during instruction. direct areas differ according size data accessed, follows. byte data access 000H 0FFH half word data access 000H 1FFH word data access 000H 3FFH
MB91301 Series
Memory
(MB91302A) (Single chip mode) (MB91302A) Internal External mode (MB91301/302A) (MB91V301A) (MB91V301) External Internal Internal External External mode External mode mode (MODR register (MODR register ROAM ROMA (MB91V301/ V301A) External External mode
0000 0000H
Direct addre ssing area "sI/O MAP"
Direct addre ssing area "sI/O MAP"
Direct addre ssing area "sI/O MAP"
Direct addre ssing area "sI/O MAP"
Direct addre ssing area "sI/O MAP"
Direct addre ssing area "sI/O MAP"
0000 0400H
0001 0000H 0002 0000H
I-RAM
I-RAM
I-RAM
I-RAM
I-RAM
I-RAM
0003 E000H
Access prohibited
Internal Kbytes
Access prohibited
Internal Kbytes
Access prohibited
Internal Kbytes
Access prohibited
Access prohibited
Access prohibited
0003 F000H
Internal Kbytes Internal Kbytes Access prohibited
Internal Kbytes Internal Kbytes Access prohibited External area
Internal Kbytes
0004 0000H
0004 2000H
External area
0006 0000H 000E 0000H
Access prohibited Access prohibited
External area External area
External area
000F E000H
000F F000H
Internal Kbytes*2
0010 0000H
Internal Kbytes*2
Internal Kbytes emulation
Access prohibited
FFFF FFFFH
External area
External area
External area
External area
External area
MB91302A non-ROM model, optimal real time internal model, (Internal program Loader) internal model adding user model. specific area between 10000H 2000H, Kbyte used. Refer "sINSTRUCTION CACHE". real time internal model stores real time kernel. program loader internal model stores program loader. Non-ROM model supports external external mode only. Note Internal emulation only MB91V301A Note Each mode depending mode vector fetch after INIT negated. (For mode setting, "sMODE SETTINGS".)
MB91301 Series
Registers
series types registers: application-specific registers general purpose registers memory. Dedicated registers Program counter (PC) Program status (PS) Table base register (TBR) Return pointer (RP) System stack pointer (SSP) User stack pointer (USP) Multiplication division result register (MDH/MDL)
32-bit register. Stores current instruction address. 32-bit register. Contains register pointer condition code. Stores address vector table used (exception/interrupt/ trap) function. Stores subroutine return address. Points system stack area. Points user stack area. 32-bit registers used multiplication division.
Initial value Program counter Program status Table base register Return pointer System stack pointer User stack pointer Multiplication division result register
000F FC00H XXXX XXXXH 0000 0000H XXXX XXXXH XXXX XXXXH XXXX XXXXH XXXX XXXXH
(Program Counter) program counter stores address currently executing instruction.
Table base register (TBR) table base register stores address vector table used function.
MB91301 Series
Return pointer (RP) return pointer stores subroutine return address.
System stack pointer (SSP) system stack pointer functions when flag "0".
User stack pointer (USP) user stack pointer functions when flag "1".
Multiplication division result register (MDH/MDL) MDH/MDL 32-bit registers used multiplication division. Remainder Quotient
Multiplication division result register
MB91301 Series
Program status (PS) This register holds program status divided into ILM, SCR, CCR. position
Condition code register (CCR) flag Specifies which stack pointer R15. flag Enables disables user interrupt requests. flag Indicates sign when operation result represented complement integer. flag Indicates whether operation result zero. flag Indicates whether overflow occurred operation result when operation operand represented complement integer. flag Indicates whether operation resulted borrow carry from most significant bit.
Initial Value
00XXXXB
System condition code register (SCR) flags Stores intermediate data stepwise multiplication operations. flags flag specifying whether step trace trap function enabled not.
Initial Value XX0B
Interrupt level mask register(ILM) ILM4 ILM0 This register stores interrupt level mask value. value register used level mask. Only interrupt requests that have interrupt level that higher than level specified accepted. ILM4 ILM3 ILM2 ILM1 ILM0 Interrupt Level High (Medium) Initial Value 01111B
MB91301 Series
GENERAL PURPOSE REGISTERS
General purpose registers used CPU. registers used accumulator memory access pointers operations. 32-bit
Initial Value
XXXX XXXXH
(Accumulator) (Frame Pointer) (Stack Pointer)
XXXX XXXXH 0000 0000H
following three registers treated having special meanings enhance operation some instructions. Virtual accumulator (AC) Frame pointer (FP) Stack pointer (SP) values after reset undefined. initialized 0000 0000H (SSP value)
MB91301 Series
MODE SETTINGS
series, mode mode pins (MD2, mode register (MODR).
Mode Pins
MD2, MD1, pins specify mode vector fetch performed. Mode Pins Reset vector access Mode name area Internal vector mode External vector mode Internal External
Remarks
Single-chip mode* width specified mode register.
Values other than those listed table prohibited. Single chip mode able only MB91302A.
Mode Register (MODR)
Details mode register (MODR) data written mode register mode vector fetch operation (see "3.11.3 reset sequences") called mode data. After data mode register (MODR), device operates with operating mode specified this data. mode register types reset. register cannot written user programs.
<Details mode register (MODR)
Operation mode setting bits
ROMA WTH1 WTH0
Initial Value
Address
XXXXXXXXB
<Details mode data>
Operation mode setting bits
ROMA WTH1 WTH0
Initial Value
Address
XXXXXXXXB
[bit31 bit27] Reserved bits These bits should always "00000." other value, stable operation assured.
MB91301 Series
Operating mode mode Single chip Internal external External external
Access mode 32-bit width 16-bit width 8-bit width
Single chip internal external mode able only MB91302A MB91V301A. mode mode controls operations internal external access function. specified with mode setting pins (MD2, MD1, MD0) ROMA mode data. Access mode access mode controls external data width. specified with WTH1 WTH0 bits mode register DBW1 DBW0 bits area configuration registers (ACR0 ACR7). Modes family three modes: mode (single-chip mode), mode (internal-ROM, external-bus mode), mode (external-ROM, external-bus mode). MB91301 supports only mode (external-ROM, external-bus mode). Memory Space" sCPU details. mode0 (single chip mode) (only MB91302A) internal I/O, Dbus RAM, Fbus (FRAM) Fbus valid, while access other areas invalid under this mode. function external peripheral general-purpose port. used pin. mode (internal external mode) (only MB91302A, MB91V301A) internal I/O, Dbus RAM, Fbus (FRAM) Fbus valid, access areas where external access enabled will access external space under this mode. part external terminal functions terminal. mode (External-ROM, external-bus mode) This mode enables internal D-bus RAM, which access access external space. Some external pins serve pins.
MB91301 Series
This shows location various peripheral resource registers memory space. [How read table] address 000000H register PDR0 [R/W] XXXXXXXX PDR1 [R/W] XXXXXXXX PDR2 [R/W] XXXXXXXX PDR3 [R/W] XXXXXXXX block T-unit Port Data Register
Read/write attribute, Access type Initial value after reset Register name (Address column register address column register 4n+2, etc.) Location left-most register (When using word access, register column side data.)
Note Initial values register bits represented follows Initial value"1" Initial value"0" Initial value"X" physical register this location
MB91301 Series
Address 000000H 000004H 000008H 00000CH 000010H 000014H 00003CH 000040H 000044H 000048H 00004CH 000050H 000054H 000058H 00005CH
Register PDR0 [R/W] XXXXXXXX PDR8 [R/W] XXXXXXXX PDR1 [R/W] XXXXXXXX PDR9 [R/W] XXXXXXX PDRG [R/W] XXXXXXXX PDRH [R/W] EIRR [R/W] ENIR [R/W] 00000000 00000000 DICR [R/W] HRCL [R/W] 11111 TMRLR0 XXXXXXXX XXXXXXXX TMRLR1 XXXXXXXX XXXXXXXX TMRLR2 XXXXXXXX XXXXXXXX ELVR [R/W] 00000000 TMR0 XXXXXXXX XXXXXXXX TMCSR0 [R/W] XX0000 00000000 TMR1 XXXXXXXX XXXXXXXX TMCSR1 [R/W] XX0000 00000000 TMR2 XXXXXXXX XXXXXXXX TMCSR2 [R/W] XX0000 00000000 PDRJ [R/W] XXXXXXXX PDR2 [R/W] XXXXXXXX PDR6 [R/W] XXXXXXXX PDRA [R/W] XXXXXXXX PDRB [R/W] XXXXXXXX
Block
T-unit Port Data Register
R-bus Port Data Register Reserved
DLYI/I-unit
Reload Timer
Reload Timer
Reload Timer
000060H
SIDR0 SSR0 [R/W] SCR0 [R/W] SMR0 [R/W] SODR0 00001000 00000100 XXXXXXXX UTIM0 (UTIMR0 00000000 00000000 DRCL0 -UTIMC0 [R/W] 00001
UART0
000064H
U-TIMER
000068H
SIDR1 SSR1 [R/W] SCR1 [R/W] SMR1 [R/W] SODR1 00001000 00000100 XXXXXXXX UTIM1 (UTIMR1 00000000 00000000 DRCL1 -UTIMC1 [R/W] 00001
UART1
00006CH
U-TIMER
(Continued)
MB91301 Series
Address
Register SIDR2 SSR2 [R/W] SCR2 [R/W] SMR2 [R/W] SODR2 00001000 00000100 XXXXXXXX UTIM2 (UTIMR2 00000000 00000000 ADCR 000000XX XXXXXXXX ADCR0 XXXXXXXX ADCR1 XXXXXXXX IBCR0 [R/W] 00000000 IBSR0 00000000 ITBA0 [R/W] 00000000 00000000 DRCL2 -UTIMC2 [R/W] 00001
Block
000070H
UART2
000074H 000078H 00007CH 000080H 000090H 000094H 000098H 00009CH 0000A0H 0000A4H 0000A8H 0000B0H 0000B4H 0000B8H 0000BCH 0000C0H 0000C4H 0000C8H 0000D0H 0000D4H 0000D8H
U-TIMER
ADCS [R/W] 00000000 00000000 ADCR2 XXXXXXXX
Converter ADCR3 Sequential Comparator XXXXXXXX Reserved
ITMK0 [R/W] 00111111 11111111
ISMK0 [R/W] ISBA0 [R/W] 01111111 00000000 interface0*1
IDAR0 [R/W] ICCR0 [R/W] IDBL0 [R/W] 00000000 00011111 00000000 Reserved*1
Reserved ITBA1 [R/W] 00000000 00000000
IBCR1 [R/W] 00000000
IBSR1 00000000
ITMK1 [R/W] 00111111 11111111
ISMK1 [R/W] ISBA1 [R/W] 01111111 00000000 interface1*1
IDAR1 [R/W] ICCR1 [R/W] IDBL1 [R/W] 00000000 00011111 00000000 Reserved*1 TCCS [R/W] Free 00000000 Timer*1 ICU*1
TCDT [R/W] 00000000 00000000 IPCP1 [R/W] XXXXXXXX_XXXXXXXX
IPCP0 [R/W] XXXXXXXX_XXXXXXXX
(Continued)
MB91301 Series
Address 0000DCH 0000E0H 0000E4H 000114H 000118H 000011CH 000120H 000124H 000128H 00012CH 000130H 000134H 000138H 00013CH 000140H 0001FCH 000200H 000204H 000208H 00020CH 000210H
Register IPCP3 [R/W] XXXXXXXX_XXXXXXXX ICS23 [R/W] 00000000 GCN10 [R/W] 00110010 00010000 PTMR0 11111111 11111111 PDUT0 XXXXXXXX XXXXXXXX PTMR1[R] 11111111 11111111 PDUT1 XXXXXXXX XXXXXXXX PTMR2 11111111 11111111 PDUT2 XXXXXXXX XXXXXXXX PTMR3[R] 11111111 11111111 PDUT3 XXXXXXXX XXXXXXXX DMACA0 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB0 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA1 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB1 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA2 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX PCSR0 XXXXXXXX XXXXXXXX PCNH0 [R/W] 00000000 PCNL0 [R/W] 000000X0 GCN20 [R/W] 00000000 IPCP2 [R/W] XXXXXXXX_XXXXXXXX ICS01 [R/W] 00000000
Block
ICU*1
Reserved
timer Reserved
PPG0
PCSR1 XXXXXXXX XXXXXXXX PCNH1 [R/W] 00000000 PCNL1 [R/W] 000000X0
PPG1
PCSR2 XXXXXXXX XXXXXXXX PCNH2 [R/W] 00000000 PCNL2 [R/W] 000000X0
PPG2
PCSR3 XXXXXXXX XXXXXXXX PCNH3 [R/W] 00000000 PCNL3 [R/W] 000000X0
PPG3
Reserved
DMAC
DMAC
(Continued)
MB91301 Series
Address 000214H 000218H 00021CH 000220H 000224H 000228H 00023CH 000240H 000244H 000300H 000304H 000308H 0003E0H 0003E4H 0003E8H 0003EFH 0003F0H 0003F4H 0003F8H 0003FCH
Register DMACB2 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA3 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB3 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACA4 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX DMACR [R/W] 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX BSD0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDRG [R/W] 00000000 DDRH [R/W] DDRJ [R/W] 00000000 ICHCR [R/W] 000000 ISIZE [R/W]
Block
DMAC
Reserved
DMAC
Reserved
I-Cache
Reserved
I-Cache
Reserved
Search Module
000400H
R-bus Data Direction Register
(Continued)
MB91301 Series
Address 000404H 00040CH 000410H 000414H 00041CH
Register PFRG [R/W] PFRH [R/W] PFRJ [R/W]
Block
Reserved R-bus Port Function Register Reserved R-bus Pull-up Resistance Control Register Reserved
000420H
PCRG [R/W] 00000000
PCRH [R/W]
PCRJ [R/W] 00000000
000424H 00043CH 000440H 000444H 000448H 00044CH 000450H 000454H 000458H 00045CH 000460H 000464H 000468H
ICR00 [R/W] ICR01 [R/W] ICR02 [R/W] ICR03 [R/W] 11111 11111 11111 11111 ICR04 [R/W] ICR05 [R/W] ICR06 [R/W] ICR07 [R/W] 11111 11111 11111 11111 ICR08 [R/W] ICR09 [R/W] ICR10 [R/W] ICR11 [R/W] 11111 11111 11111 11111 ICR12 [R/W] ICR13 [R/W] ICR14 [R/W] ICR15 [R/W] 11111 11111 11111 11111 ICR16 [R/W] ICR17 [R/W] ICR18 [R/W] ICR19 [R/W] 11111 11111 11111 11111 ICR20 [R/W] ICR21 [R/W] ICR22 [R/W] ICR23 [R/W] 11111 11111 11111 11111 ICR24 [R/W] ICR25 [R/W] ICR26 [R/W] ICR27 [R/W] 11111 11111 11111 11111 ICR28 [R/W] ICR29 [R/W] ICR30 [R/W] ICR31 [R/W] 11111 11111 11111 11111 ICR32 [R/W] ICR33 [R/W] ICR34 [R/W] ICR35 [R/W] 11111 11111 11111 11111 ICR36 [R/W] ICR37 [R/W] ICR38 [R/W] ICR39 [R/W] 11111 11111 11111 11111 ICR40 [R/W] ICR41 [R/W] ICR42 [R/W] ICR43 [R/W] 11111 11111 11111 11111
Interrupt Controller
(Continued)
MB91301 Series
Address 00046CH 000470H 00047CH
Register ICR44 [R/W] ICR45 [R/W] ICR46 [R/W] ICR47 [R/W] 11111 11111 11111 11111 RSRR [R/W] 10000000 (INIT) (INIT) (RST) CLKR [R/W] 00000000 (INIT) XXXXXXXX (RST) STCR [R/W] TBCR [R/W] 00110011 (INIT) 00111111 (HST) 00XXXX00 (INIT) 0011XX11 (INIT) 00XXXXXX (RST) 00X1XXX (RST) XXXXXXXX (INIT) XXXXXXXX (RST)
Block
Interrupt Controller
000480H
CTBR XXXXXXXX (INIT) XXXXXXXX (RST)
000484H 000488H 0005FCH 000600H 000604H 000608H 00060CH 000610H 000614H 000618H 00061CH 000620H 000624H 000628H 00062CH
DIVR0 [R/W] DIVR1 [R/W] 00000011 (INIT) 00000000 (INIT) XXXXXXXX (RST) XXXXXXXX (RST)
Clock Control unit
Reserved DDR2 [R/W] 00000000 DDR6 [R/W] 00000000 DDRB [R/W] 00000000 T-unit Data Direction Register
DDR0 [R/W] 00000000 DDR8 [R/W] 00000000
DDR1 [R/W] 00000000
DDR9 [R/W] 0000000
DDRA [R/W] 00000000
PFR8 [R/W] PFRB2 [R/W] PCR0 [R/W] 00000000 PCR8 [R/W] 00000000
PFR9 [R/W] 0000111 PCR1 [R/W] 00000000
PFR6 [R/W] 11111111 PFRA1 [R/W] 11111111 PFRA2 [R/W] -0-PCR2 [R/W] 00000000 PCR6 [R/W] 00000000
PFR61 [R/W] 0000 PFRB1 [R/W] 00000000 PCRB [R/W] 00000000
T-unit Port Function Register
PCR9 [R/W]
PCRA [R/W] 00000000
T-unit Pull-up Resistance Control Register
(Continued)
MB91301 Series
Address 000630H 00063CH 000640H 000644H 000648H 00064CH 000650H 000654H 000658H 00065CH 000660H 000664H 000668H 00066CH 000670H 000674H 000678H 00067CH 000680H
Register ASR0 [R/W] 00000000 00000000 ASR1 [R/W] XXXXXXXX XXXXXXXX ASR2 [R/W] XXXXXXXX XXXXXXXX ASR3 [R/W] XXXXXXXX XXXXXXXX ASR4 [R/W] XXXXXXXX XXXXXXXX ASR5 [R/W] XXXXXXXX XXXXXXXX ASR6 [R/W] XXXXXXXX XXXXXXXX ASR7 [R/W] XXXXXXXX XXXXXXXX AWR0 [R/W] 01111111 11111011 AWR2 [R/W] XXXXXXXX XXXXXXXX AWR4 [R/W] XXXXXXXX XXXXXXXX AWR6 [R/W] XXXXXXXX XXXXXXXX MCRA [R/W] MCRB [R/W] XXXXXXXX XXXXXXXX IOWR0 [R/W] IOWR1 [R/W] IOWR2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX CSER [R/W] CHER [R/W] 00000001 11111111 [R/W] 00XXXXXX XXXX0XXX [R/W] 00000000 (INIT) 0000XXXX (RST) ACR0 [R/W] 1111XX00 00000000 ACR1 [R/W] XXXXXXXX XXXXXXXX ACR2 [R/W] XXXXXXXX XXXXXXXX ACR3 [R/W] XXXXXXXX XXXXXXXX ACR4 [R/W] XXXXXXXX XXXXXXXX ACR5 [R/W] XXXXXXXX XXXXXXXX ACR6 [R/W] XXXXXXXX XXXXXXXX ACR7 [R/W] XXXXXXXX XXXXXXXX AWR1 [R/W] XXXXXXXX XXXXXXXX AWR3 [R/W] XXXXXXXX XXXXXXXX AWR5 [R/W] XXXXXXXX XXXXXXXX AWR7 [R/W] XXXXXXXX XXXXXXXX
Block
Reserved
T-unit
000684H
(Continued)
MB91301 Series
Address 00068CH 0007F8H 0007FCH 000800H 000AFCH 000B00H 000B04H 000B08H 000B0CH 000B10H 000B14H 000B1CH 000B20H 000B24H 000B28H 000B2CH 000B30H 000B34H 000B38H 000B3CH 000B40H 000B44H
Register MODR XXXXXXXX ESTS0 [R/W] X0000000 ECTL0 [R/W] 0X000000 ECNT0 XXXXXXXX ESTS1 [R/W] XXXXXXXX ECTL1 [R/W] 00000000 ECNT1 XXXXXXXX ESTS2 1XXXXXXX ECTL2 000X0000 EUSA XXX00000 ECTL3 [R/W] 00X00X11 EDTC 0000XXXX
Block
Reserved
T-unit
Reserved
EWPT 00000000 00000000 EDTR0 XXXXXXXX XXXXXXXX
ECTL4 ([R/W]) ECTL5 ([R/W]) 0X00000 000X EDTR1 XXXXXXXX XXXXXXXX
EIA0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA2 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA3 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA4 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA5 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA6 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA7 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDTA [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ED[R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX (Evaluation chip only)
(Continued)
MB91301 Series
Address 000B48H 000B4CH 000B50H 000B54H 000B58H 000B5CH 000B60H 000B64H 000B68H 000B6CH 000B70H 000FFCH 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH 001020H
Register EOA0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOA1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPCR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPSR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM0/EODM0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM1/EODM1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOD0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOD1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA2 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Block
(Evaluation chip only)
Reserved
DMAC
(Continued)
MB91301 Series
(Continued)
Address 001024H 001028H 001FFCH Register DMADA4 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Block DMAC
Reserved
used 00094H 000A7H 000B4H 000E3H MB91301 MB91V301 exist register 000420H 000423H MB91302A MB91V301A exist register 000617H MB91301and MB91V301 Byte access permitted lower bits DMAC0 DMAC4 (DTC15 DTC0) This register accessed through mode vector fetch; cannot accessed normal mode.
MB91301 Series
INTERRUPT VECTORS
Interrupt Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction Instruction break exception Operand break trap Step trace trap request (tool) Undefined instruction exception request External interrupt External interrupt External interrupt External interrupt External interrupt External interrupt External interrupt External interrupt Reload timer Reload timer Reload timer UART0 completed) UART1 completed) UART2 completed) UART0 completed) UART1 completed) UART2 completed) Interrupt Interrupt level*1 (FH) fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H 37CH default address*2 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 000FFF7CH
(Continued)
MB91301 Series
Interrupt DMAC0 (end, error) DMAC1 (end, error) DMAC2 (end, error) DMAC3 (end, error) DMAC4 (end, error) PPG0 PPG1 PPG2 PPG3 System reserved U-TIMER0 U-TIMER1 U-TIMER2 Time base timer overflow I/F0*
Interrupt
Interrupt level*1 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
Offset 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H 2F4H
default address*2 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3FH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H 000FFEF4H
I/F1*3 System reserved*3 System reserved* ICU0 (load) ICU1 (load) ICU2 (load) ICU3 (load)
Free Timer*
System reserved System reserved System reserved System reserved System reserved System reserved Delay interrupt System reserved (Used REALOS) System reserved (Used REALOS) System reserved
(Continued)
MB91301 Series
(Continued)
Interrupt System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used instruction Interrupt Interrupt level*1 Offset 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH 000H default address*2 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH 000FFC00H
ICRs registers built interrupt controller interrupt levels individual interrupt requests. ICRs provided different interrupt levels. register holding start address vector table. value offset value preset each source added together vector address. address system reserved MB91301, MB91V301. Note: 1-KB area from address vector area. vector size bytes relationship between vector number vector address expressed follows: Vctadr vctofs (3FCH vct) vctadr vector address vctofs vector offset vector number
MB91301 Series
INSTRUCTION CACHE
instruction cache fast local memory temporary storage. Once instruction code accessed from external slower memory, instruction cache holds instruction code inside increase speed accessing same code from then setting mode, instruction cache data made directly read/write-accessible software. Configuration family's basic instruction length bytes Block layout Two-way associative Blocks blocks bytes block sub-blocks) bytes sub-block access unit) Instruction Cache Configuration
bytes
bytes
bytes
bytes
bytes
Cash block Cash Cash
block
block
block
block
block
block
block
block
block
block
block
block
block
block
block
block
Cash
block
block
block
block
block
MB91301 Series
Instruction Cache Tags
Vacancy
Address
SBV3 SBV2 SBV1 SBV0
TAGV
Vacancy
Vacancy
ETLK
Address
SBV3 SBV2 SBV1 SBV0
TAGV
ETLK
Vacancy
[bit Address address stores upper bits memory address instruction cached corresponding block. example, memory address instruction data stored sub-block block obtained from following equation: address address used check match with instruction address requested access CPU. cache behave follows depending result check: When requested instruction data exists cache (hit), cache transfers data within cycle. When requested instruction data does exist cache (miss), cache obtain data loaded external access same time.
[bit bit4] SBV3 SBV0 Sub-block validation When SBVn contains "1", corresponding sub-block holds current instruction data address located tag. Each sub-block usually holds instructions (excluding immediate-value transfer instructions). [bit TAGV validation This indicates whether address value valid. When contains "0", corresponding block invalid regardless settings sub-block validation bits. (The when cache flushed.) [bit (only This exists only instruction cache indicates containing last entry accessed selected set. When "1", indicates that entry last entry accessed. When "0", indicates that last entry accessed. [bit ETLK Entry lock This used lock entries block corresponding cache. When ETLK "1", entries locked updated when cache miss occurs. Note, however, that invalid sub-blocks updated. cache miss occurs with both ways entry lock states, access external memory takes place after losing cycle used evaluating cache miss.
MB91301 Series
Control Registers Cache Size Register (ISIZE) Address 00000307H
SIZE1 SIZE0
Initial value
Instruction Cache Control Register (ICHCR) instruction cache (I-cache) control register (ICHCR) controls operations instruction cache. Writing value ICHCR effect caching instruction fetched within three cycles that follow.
Address 000003E7H
GBLK
ALFL
EOLK
ELKR
FLSH
ENAB
Initial value 000000B
Address 00010000 00010200 00010400 00010600 00010800 00010FFFH 00014000 00014200 00014400 00014600 00014800 00014FFFH 00018000 00018200 00018400 00018600 00018800 00018FFFH 0001C000H 0001C200H 0001C400H 0001C600H 0001C800H 0001CFFFH
Cache
Cache TAG1
Cache
Cache Cache TAG1
Cache Cache TAG1 <TAG1>
Cache TAG1 <TAG1> <TAG1> <TAG1> <TAG1> TAG2 <TAG2> <TAG2> <TAG2> <TAG2> $RAM1
<TAG1> TAG2
<TAG1> TAG2
<TAG1> TAG2 <TAG2>
<TAG2> IRAM1 IRAM1
<TAG2> $RAM1 IRAM1
<TAG2> $RAM1 IRAM1 <$RAM1> $RAM2 IRAM2 IRAM2 <$RAM2> IRAM2 <IRAM2> IRAM1 <IRAM1>
IRAM1 <$RAM1> $RAM2 IRAM2 <$RAM2>
<IRAM1> IRAM2
<IRAM1> IRAM2
<$RAM1> $RAM2
<IRAM1>
<IRAM2>
<IRAM2>
<$RAM2>
<IRAM2>
00010000 00010004 00010008 0001000CH 00010010 00010014
TAG1 (way1) $RAM1 Cache (way1) TAG2 (way2) $RAM2 Cache (way2) Mirror area on/offRAM Cache Entry address 00018000 00018004 Mirror Entry address Mirror
00018008 0001800C 00018010 00018014
IRAM1 I-Bus (way1) IRAM1 I-Bus (way2)
Instruction address (SBV0) Instruction address (SBV1) Instruction address (SBV2) Instruction address (SBV3) Instruction address (SBV0) Instruction address (SBV1)
MB91301 Series
Address 000H 200H 400H 600H 000H 200H 400H 600H
Cache
Cache $RAM1
Cache $RAM1 IRAM1 $RAM2 IRAM2
Cache
$RAM1 IRAM1 $RAM2 $RAM2 IRAM2
IRAM1
IRAM2
ROMA (ROM absent) Address 00000000
Direct area
00010000 00020000 00030000 00040000 00100000 FFFFFFFFH IRAM
ROMA (ROM present)
Direct area
IRAM
(Even D-bus area cashed, when transferred IA-Bus.) Internal ROM/RAM area should cached. Each chip-select area non-cache area.
Cache area
Internal memory
Cache area
MB91301 Series
PERIPHERAL RESOURCES
External Interface Controller
External Interface Controller Features Maximum output address width 32-bit memory space) Various different types external memory (8-bit, 16-bit, 32-bit devices) directly connected controller support multiple devices with different access timings. Asynchronous SRAM, asynchronous ROM/FLASH memory (supports multiple write strobe access byteenable access) Page mode ROM/FLASH memory page size) Burst mode ROM/FLASH memory Address/data multiplexed (8-bit 16-bit width only) Synchronous memory (built-in ASIC memory, etc.) Note: Synchronous SRAM cannot directly connected. Memory divided into eight independent banks (chip select areas) with separate chip select output each bank. size each area Kbyte increments (the size each chip select area range from Kbyte Gbyte) Each area located anywhere physical address space (subject boundary limitations based area size) following functions independently each chip select area Chip select area enable/disable (Access performed disabled areas) Setting access timing type support each type memory (For SDRAM, only areas connected.) Detailed access timing settings (wait cycles similar settings each access type) Data width (8-bit, 16-bit, 32-bit) Byte-ordering setting (big little endian) Note: area must endian. Write-prohibit setting (read-only areas) Enable disable loading into built-in cache Enable disable prefetch function Maximum burst length setting Different detailed timing settings each timing type Even same type, different settings used each chip select area. auto-wait cycles specified. (For asynchronous SRAM, ROM, Flash, areas) cycle extended external input. (For asynchronous SRAM, ROM, Flash, areas) Fast access wait page wait settings supported (For burst/page mode Flash areas) Idle cycles, recovery cycles, setup delays, similar inserted. Capable setting timing values such latency RAS-CAS delay (SDRAM area) Capable controlling distributed/centralized auto-refresh, self-refresh, other refresh timings (SDRAM area) supports fly-by transfer Transfer between memory performed single access. Memory wait cycles synchronized with wait period during fly-by transfer. Hold times maintained extending access data source only. Separate idle recovery cycle settings specified fly-by transfer. Supports external arbitration using BGRNT. Pins used external interface general purpose ports.
MB91301 Series
Block Diagram Internal address Internal data
External data
write buffer
switch
read buffer
switch
DATA BLOCK ADDRESS BLOCK
External address
address buffer
comparator
SDRAM control
SRAS, SCAS, SWE, MCLKE, DQMUU, DQMUL, DQMLU, DQMLL under flow
refresh counter
External controller block control
registers control
WR0, WR1, WR2, WR3,
BGRNT
MB91301 Series
External interface (Some pins general purpose pins.) following shows pins each interface. Normal interface A00, (AD15 AD00) CS0, CS1, CS2, CS3, CS4, CS5, CS6, SYSCLK, MCLK, (UUB) (ULB) (ULB) (LLB) RDY, BRQ, BGRNT Memory interface MCLK, MCLKE MCLKI (for SDRAM) (for burst ROM/FLASH) SRAS, SCAS, (for SDRAM) DQMUU, DQMUL, DQMLU, DQMLL (for SDRAM WR0, WR1, WR2, WR3) interface IOWR, IORD DACK0, DACK1 DREQ0, DREQ1 DEOP0, DEOP1
MB91301 Series
Register List
ASR0 ASR1 ASR2 ASR3 ASR4 ASR5 ASR6 ASR7 AWR0 AWR2 AWR4 AWR6 MCRA Reserved IOWR0 Reserved CSER Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved (MODR) MCRB Reserved IOWR1 Reserved CHER ACR0 ACR1 ACR2 ACR3 ACR4 ACR5 ACR6 ACR7 AWR1 AWR3 AWR5 AWR7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Area select registers (ASR0 ASR7) Area configuration registers (ACR0 ACR7)
Area weight register (AWR0 AWR7)
Memory setting register (For SDRAM/FCRAM auto-precharge mode) (MCRA) Memory setting register (For FCRAM auto-precharge mode) (MCRB) DMAC wait registers (IOWR0 IOWR1) Chip-select area enable register (CSER) Cache fetch enable register (CHER) Terminal timing control register (TCR) Refresh control register (RCR)
Notes Reserved indicates reserved register. When writing, always "0". MODR register cannot accessed user program.
MB91301 Series
Ports
MB91301 series pins used ports when external interface various peripheral functions. port (with pull-up resistor) block diagram
Port
read
Peripheral input
Pull-up resistor (approx.
Peripheral output
pull-up resistor pull-up resistor
Port Data Register Data Direction Register Port Function Register Pull-up Control Register
Note port output, pull-up resistor disabled irrespective setting. ports with pull-up resistors have following registers (Port Data Register) (Data Direction Register) (Port Function Register) (Pull-up Control Register) ports have three following modes When port input mode (PFR "0") read Reads level corresponding external pin. write Writes value PDR. When port output mode (PFR "1") read Reads value. write Outputs value corresponding external pin. When port peripheral output mode (PFR "X") Reads value corresponding peripheral output. write Writes value PDR.
MB91301 Series
Notes byte access access ports. external function priority port port when these used external pins. Accordingly, writing effect input/output setting while pins operating external pins. value becomes meaningful when register modified pins general purpose ports. stop mode (HIZ pull-up resistor control register setting used. stop mode (HIZ pull-up resistor control register setting ignored during hardware standby. Using pull-up resistors prohibited when these pins used external pins. this case, write corresponding pull-up control register (PCR).
MB91301 Series
Port Data Register (PDR) PDR0 Address 00000000H PDR1 Address 00000001H PDR2 Address 00000002H PDR6 Address 00000006H PDR8 Address 00000008H PDR9 Address 00000009H PDRA Address 0000000AH PDRB Address 0000000BH PDRG Address 00000010H PDRH Address 00000011H PDRJ Address 00000013H
Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXB Initial value XXXXXXXXB
PDR0 PDR2, PDR6, PDR8 PDRB, PDRG, PDRH PDRJ data registers pots. corresponding PDR0 DDRJ PFR6 PFRJ registers control input/output. P07, have (port function register).
MB91301 Series
Data Direction Register (DDR) DDR0 Address 00000600H DDR1 Address 00000601H DDR2 Address 00000602H DDR6 Address 00000606H DDR8 Address 00000608H DDR9 Address 00000609H DDRA Address 0000060AH DDRB Address 0000060BH DDRG Address 00000400H DDRH Address 00000401H DDRJ Address 00000403H
Initial value 00000000B Initial value 00000000B Initial value 00000000B Initial value 00000000B Initial value 00000000B Initial value 0000000B Initial value 00000000B Initial value 00000000B Initial value 00000000B Initial value 000B Initial value 00000000B
DDR0 DDR2, DDR6, DDR8 DDRB, DDRG, DDRH DDRJ control direction (input output) each corresponding port. When Port input Port output When Peripheral input Peripheral output
MB91301 Series
Pull-up Resistor Control Register (PCR) PCR0 00000620H
Address
Initial value 00000000B
Address
PCR1 00000621H
Initial value 00000000B
Address
PCR2 00000622H
Initial value 00000000B
Address
PCR6 00000626H
Initial value 00000000B
Address
PCR8 00000628H
Initial value 00000000B
Address
PCR9 00000629H
Initial value
Address
PCRA 0000062AH
Initial value 00000000B
Address
PCRB 0000062BH
Initial value 00000000B
Address
PCRG 00000420H
Initial value 00000000B
Address
PCRH 00000421H
Initial value 000B
Address
PCRJ 00000423H
Initial value 00000000B
PCR0 PCR2, PCR6, PCR8 PCRB, PCRG, PCRH PCRJ control pull-up resistors corresponding port. pull-up resistor pull-up resistor Note There PCRG register RCRJ register MB91302A MB91V301A.
MB91301 Series
Port Function Register (PFR)
Address
PFR6 00000616H
A23E
A22E
A21E
A20E ASXE
A19E
A18E BRQE
A17E
A16E SYSE
Initial value 11111111B
Address
PFR8 00000618H WR3XE WR2XE WR1XE
WRXE BAAE
Initial value
Address
PFR9 00000619H
MCKE MCKEE
Initial value 0000111B
Address
PFRA1 0000061AH CS7XE CS6XE CS5XE CS4XE CS3XE CS2XE CS1XE CS0XE
AK12 DWRE SOE2 PPE0 AK11 PPE1 PPE2 SCE1 AK10 SOE1 DES0 TEST1 AK02 SCE0 TEST0 AK01 AKH1 PPE3 SOE0 I2CE1 AK00 AKH0 I2CE0
Initial value 11111111B
Address
PFRB1 0000061BH
DES1
Initial value 00000000B
Address
PFRB2 0000061CH
DRDE
Initial value 0000
Address
PFRA2 0000061EH
Initial value
Address
PFRG 00000410H
SCE2
Initial value
Address
PFRH 00000411H
Initial value
Address
PFRJ 00000413H
Initial value
Address
PFR61 00000617H
Initial value 0000
PFR6, PFR8 PFRB, PFRA2, PFRG, PFRH PFRJ control output corresponding external interface peripheral output bit. Always write unused bits PFR. Note There PFR61 register MB91301 MB91V301.
MB91301 Series
Interrupt Controller
interrupt controller receives processes interrupts. Hardware Configuration interrupt controller consists following register Interrupt priority determination circuit Interrupt level interrupt number (vector) generator Hold request removal request generator Principal Functions main functions interrupt controller follows Detect interrupt requests Prioritize interrupts (according level number) Notify interrupt level selected interrupt request CPU) Notify interrupt number selected interrupt request CPU) interrupt request with interrupt level other than "11111B" occurs, notify recovery from stop mode CPU) Generate hold request removal requests master Block Diagram ("1" when LEVEL 11111B) ("1" when LEVEL 11111B)
UNMI
WAKEUP
Determine order priority Determine order ofof priority processing processing
LEVEL4 LEVEL40
LEVEL LEVEL determination determination
RI00 ICR00
VECTOR VECTOR determination determination
LEVEL, LEVEL, VECTOR VECTOR generageneration tion
HLDREQ HLDREQ removal removal request request
MHALTI
VCT5 VCT50
ICR47 RI47 (DLYIRQ)
R-bus
MB91301 Series
Register List
ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0
Address 00000440H Address 00000441H Address 00000442H Address 00000443H Address 00000444H Address 00000445H Address 00000446H Address 00000447H Address 00000448H Address 00000449H Address 0000044AH Address 0000044BH Address 0000044CH Address 0000044DH Address 0000044EH Address 0000044FH Address 00000450H Address 00000451H Address 00000452H Address 00000453H Address 00000454H Address 00000455H Address 00000456H Address 00000457H Address 00000458H Address 00000459H Address 0000045AH Address 0000045BH Address 0000045CH Address 0000045DH Address 0000045EH Address 0000045FH
ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31
(Continued)
MB91301 Series
(Continued)
ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR4 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR3 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR2 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR1 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0 ICR0
Address 00000460H Address 00000461H Address 00000462H Address 00000463H Address 00000464H Address 00000465H Address 00000466H Address 00000467H Address 00000468H Address 00000469H Address 0000046AH Address 0000046BH Address 0000046CH Address 0000046DH Address 0000046EH Address 0000046FH
ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
Address
0000045H
MHALTI
LVL4
LVL3
LVL2
LVL1
LVL0
HRCL
MB91301 Series
External Interrupt/NMI Control Block
external interrupt control block controls external interrupt requests input INT0 INT7 pins. interrupt trigger level selected from "H", "L", "rising edge", "falling edge" (except NMI). Block Diagram
R-bus
Interrupt enable register
INT0 INT7
Interrupt request
Gate
Request
Edge detection circuit
Interrupt request register
Interrupt level setting register
Register List External interrupt enable register (ENIR)
External interrupt request register (EIRR)
Request level setting register (ELVR)
MB91301 Series
Delay Interrupt Module
delay interrupt module used generate interrupts task switching. This module used generate cancel interrupts software. Block Diagram
R-bus
DLYI
Interrupt request
Register List Delay interrupt control register (DICR)
DLYI
MB91301 Series
Timer
timer output highly precise waveforms efficiently. MB91301 series contains four channels timer. Features Timer Each channel consists 16-bit down counter, 16-bit data register with cycle setting buffer, 16-bit compare register with duty setting buffer, control section. count clocks 16-bit down counter selected from following four types Internal clock /16, counter initialized "FFFFH" reset counter borrow. Each channel output. Register outline Cycle setting register: Reload data register with buffer Duty setting register: Compare register with buffer Transfer from buffer takes place upon counter borrow. control overview duty match sets control section (Preferential) counter borrow resets output value mode available, which each output "H"). polarity also specified. interrupt request generated combination following events Activation timer Counter borrow (cycle match) Duty match Counter borrow (cycle match) duty match transfer initiated above interrupt request. possible simultaneous activation more channels means software another interval timer. Restarting during operation also set. request level detected selected from among "rising edge", "falling edge", "both edges".
MB91301 Series
Block diagram
16-bit reload timer 16-bit reload timer
input timer
PPG0
General control register
General control register (resource select)
input timer
PPG1
input timer input timer
PPG2
External TRG0 TRG3
PPG3
Block diagram channel
PCRS
PDUT
Prescaler
Load
16-bit down counter Start Borrow
mask
output
Peripheral clock
Conversion
Enable input Edge detection Soft trigger
Interrupt selection
MB91301 Series
Register List
GCN10
General control register
GCN20
General control register
PTMR0 PCSR0 PDUT0 PCNH0 PCNL0
timer register cycle setting register duty setting register control status register
PTMR1 PCSR1 PDUT1 PCNH1 PCNL1
timer register cycle setting register duty setting register control status register
PTMR2 PCSR2 PDUT2 PCNH2 PCNL2
timer register cycle setting register duty setting register control status register
PTMR3 PCSR3 PDUT3 PCNH3 PCNL3
timer register cycle setting register
duty setting register
control status register
MB91301 Series
16-Bit Reload Timer
16-bit timer consists 16-bit down-counter, 16-bit reload register, prescaler generating internal count clock, control register. clock source selected from three internal clock signals (machine clock divided external event. interrupt used initiate transfer. MB91301 series three 16-bit reload timer channels. Block Diagram
16-bit reload register (TMRLR)
Reload
16-bit down counter (TMR)
RELD
Count enable
CTL.
INTE CNTE
Re-trigger Clock selector
CSL1
CSL0
EXCK
CTL.
Prescaler clear
MOD0 MOD1
External trigger selection
External trigger input (TI)
CLKP input
MOD2
MB91301 Series
Register List Control status register (TMCSR)
OUTL RELD CSL1 INTE CSL0 MOD2 CNTE MOD1
MOD0
16-bit timer register (TMR)
16-bit reload register (TMRLR)
MB91301 Series
U-TIMER timer UART baud rate generation)
U-TIMER 16-bit timer used generate baud rate UART. desired baud rate using combination chip operating frequency U-TIMER reload value. U-TIMER also used interval timer generating interrupt from count underflow event. MB91301 series three U-TIMER channels. When used interval timer, U-TIMER channels connected cascade maximum count interval Cascade connection only available channel channel channel channel Block Diagram
UTIMR (reload register) load UTIM (timer)
clock underflow
(CLKP) (Peripheral clock)
Channel only
control
f.f.
UART
under flow U-TIMER
MB91301 Series
Register List
UTIM UTIMR UTIMC
U-TIMER (UTIM)
Address 000064H (ch.0) 00006CH (ch.1) 000074H (ch.2)
Initial value 00000000 00000000B
UTIM contains timer value. 16-bit transfer instruction access register. Reload register (UTIMR) Address 000064H (ch.0) 00006CH (ch.1) 000074H (ch.2)
Initial value 00000000 00000000B
UTIMR register that contains value reloaded UTIM when UTIM causes underflow. 16-bit transfer instruction access register.
MB91301 Series
UART
UART serial port asynchronous (start-stop synchronized) synchronized transmission. MB91301 series three UART channels. UART Features Full duplex double buffer Asynchronous (start-stop synchronized) synchronized transmission Supports multi-processor mode Fully programmable baud rate internal timer desired baud rate (see U-TIMER" description) Variable baud rate input from external clock. Error detection functions (parity, framing, overrun) Transmission signal format interrupt used initiate transfer. DMAC interrupt cleared writing DRCL register.
MB91301 Series
Block Diagram Control signal interrupt CPU) (clock) From U-TIMER Clock selection circuit clock clock interrupt CPU)
External clock control circuit (Receive data) Start detect circuit Receive counter Receive parity counter control circuit start circuit Send counter Send parity counter (Send data)
Receive status decision circuit
shifter
complete
SIDR
shifter
start
SODR
Receive error signal DMAC)
register
SCKE
register
register
RDRF TDRE
Control signal
MB91301 Series
Register List
SIDR (R)/SODR (R/W) (R/W)
DRCL
Serial input data register Serial output data register (SIDR/SODR)
Serial status register (SSR)
RDRF
TDRE
Serial mode register (SMR)
SCKE
Serial control register (SCR)
DRCL register (DRCL)
MB91301 Series
Converter (Successive Approximation Type)
converter converts analog input voltages digital values. Converter Features Peripheral clock (CLKP) clock cycle Minimum conversion time µs/ch (for machine clock CLKP) Built-in sample hold circuit Resolution 10-bit channel program-selectable analog inputs Single conversion mode Convert specified channel Scan conversion mode Continuous conversion multiple channels. Conversion specified channels. Single, continuous, stop conversion operation supported. Single conversion mode Convert specified channel then stop. Continuous conversion mode Perform continuous conversion selected channel. Stop conversion mode Perform conversion channel, then wait next activation trigger (synchronizes conversion start timing) transfer initiated interrupt. Selectable conversion activation trigger: Software, external trigger (falling edge), reload timer (rising edge)
MB91301 Series
Block Diagram
AVCC
AVRH AVSS
Internal voltage generator Sample hold circuit
Input switch
Successive approximation register Data register (ADCR bit)
Upper COPY
Data register (ADCR0 ADCR7 Channel decoder Timing generation circuit Machine clock (CLKP) (External trigger) Reload timer (internal connection) Register List Control status register (ADCS)
BUSY
control register (ADCS)
Prescaler
INTE ANS2
ANS1
STS1 ANS0
STS0 ANE2
STRT ANE1
ANE0
Data register (ADCR)
Conversion result register (ADCR0 ADCR3)
MB91301 Series
DMAC (DMA Controller)
controller used perform (direct memory access) transfer series device. Using transfer under control controller improves system performance enabling data transferred high speed independently CPU. Hardware Configuration Independent channels independent access control circuits 32-bit address register (Supports reloading channel) 16-bit transfer count register (Supports reloading channel) 4-bit block count register channel) External transfer request input pins DREQ0, DREQ1 (ch0, only) External transfer request acknowledge output pins DACK0, DACK1 (ch0, only) completion output pins DEOP0, DEOP1 (ch0, only) fly-by transfer (memory memory) (ch0, only) Two-cycle transfer Main Functions Controller Supports independent data transfer multiple channels channels) Priority order (ch.0 ch.1 ch.2 ch.3 ch.4) Order reversed DMAC activation triggers Input from dedicated external (edge detection/level detection, ch0,1 only) Request from built-in peripheral (shared interrupt request, including external interrupts) Software request (register write) Transfer modes Demand transfer, burst transfer, step transfer, block transfer Addressing mode: Full 32-bit address (increment/decrement/fixed) (address increment range-255 +255) Data type byte/half-word/word Single-shot reload operation selectable
MB91301 Series
Block Diagram
Counter
Write back
transfer request controller
Buffer Selector
two-stage register DTCR
start trigger selection circuit request acknowledge control
Peripheral start request/ Stop input External start request/Stop input
Counter Buffer
Read Write
[3:0]
Priority circuit
interrupt controller
Read/write control Selector
Selector
register
[4:0] MCLREQ
ERIR, EDIR
control block
Counter buffer
control Selector DSAD two-stage register
SDAM, SASZ [7:0] SADR
Access address
Address counter
Write back Selector
Counter buffer
DDAD two-stage register
DADM, DASZ [7:0] DADR
Write back 5-channel DMAC block diagram
control block
DDNO
DDNO register
controller
X-bus
Status transition circuit
Clear peripheral interrupt
TYPE, MOD,
MB91301 Series
Register List
(bit)
ch.0 control/status ch.0 control/status ch.1 control/status ch.1 control/status ch.2 control/status ch.2 control/status ch.3 control/status ch.3 control/status ch.4 control/status ch.4 control/status Overall control register ch.0 transfer source address register
register DMACA0 0000200H register DMACB0 0000204H register DMACA1 0000208H register DMACB1 000020CH register DMACA2 0000210H register DMACB2 0000214H register DMACA3 0000218H register DMACB3 000021CH register DMACA4 0000220H register DMACB4 0000224H
(bit)
0000240
DMASA0 0001000 DMADA0 0001004 DMASA1 0001008 DMADA1 000100CH DMASA2 0001010 DMADA2 0001014 DMASA3 0001018 DMADA3 000101CH DMASA4 0001020 DMADA4 0001024
ch.0 transfer destination address register ch.1 transfer source address register ch.1 transfer destination address register ch.2 transfer source address register ch.2 transfer destination address register ch.3 transfer source address register ch.3 transfer destination address register ch.4 transfer source address register ch.4 transfer destination address register
MB91301 Series
Interface
interface serial port that support INTER functions master/slave device bus. features below. Master/slave transmission reception Arbitration function Clock synchronization Slave address/general call address detection function Forwarding direction detection function function generating/detecting repeat "START" conditions. error detection function 10-bit/7-bit slave address Control slave address receiving master mode support multiple slave address interrupt transmitting mirror normal mode (Max Kbps) /fast mode (Max Kbps)
MB91301 Series
Block Diagram
ICCR IDBL ICCR IBSR IBCR BEIE
Interrupt request
operating enable Clock enable Clock dividing
2345 Sync CLKP
Shift clock generation
Clock select (1/12) busy Repeat start
Last
Transmission/ reception
Shift clock edge change timing
Start/stop condition detection Error
First Byte
Arbitration lost detection
SCL0/1 SDA0/1
INTE IBCR GCAA
Start Master enable GC-ACK enable
Start/stop condition generation
IDAR IBSR ISMK FNSB ITMK ENTB ITBA ITMK ISBA ISMK
Slave Global call Slave address comparison
MB91301 Series
Register List control register (IBCR0/1) address 000094H/0000B4H
BEIE GCAA INTE
Initial value status register (IBCR0/1) address 000095H/0000B5H
Initial value 10-bit slave address register (ITBA0/1) address 000096H/0000B6H Initial value address 000097H/0000B7H Initial value
(Continued)
MB91301 Series
(Continued)
10-bit slave address mask register (ITMK0/1) address 000098H/0000B8H Initial value address 000099H/0000B9H
ENTB
Initial value 7-bit slave address register (ISBA0/1) address 00009BH/0000BBH
Initial value 7-bit slave address mask register (ISMK0/1) address 00009AH/0000BAH Initial value register (IDAR0/1) address 00009DH/0000BDH
ENSB
Initial value control register (ICCR0/1) address 00009EH/0000BEH
TEST
Initial value disable register (IDBL0/1) address 00009FH/0000BFH Initial value
MB91301 Series
Free Timer
16-bit free-run timer consists 16-bit counter control status register. timer count value used base timer output compare input capture. count clock selected from four different clocks. generated interrupt counter over-flow. Setting mode enables initialization counter thruough compare-match operation with value compare clear register0 output compare.
MB91301 Series
Diagram
Interrupt
ECLK IVFE STOP MODE CLK1 CLK0
Prescaler
F-bus
FRCK
Clock selector 16-bit Free Timer (TCDT)
Clock
internal circuit (T15 T00) Comparator0
List
Timer data register (upper) (TCDT) Timer data register (lower) (TCDT) Timer control status register (lower) (TCCS)
ECLK
IVFE
STOP
MODE
CLK1
CLK0
MB91301 Series
Input Capture
This module functiion that detects rising edge, falling edge both edges holds value 16-bit free-run timer register time detection. also generate interrupt when detecting edge. input capture consist input capture control registers. Each input capture have correspondedt external input pins. valid edge external input selected from three types Rising edge Falling edge Both edges generate interrupt when detects valid edge external input. MB91302A MB91V301A only have built-in input capture
MB91301 Series
Diagram
16-bit timer count value (T15 T00) Capture data register IN0, input
Edge detection
EG11 R-bus EG31
EG10 EG30
EG01 EG21
EG00 EG20
16-bit timer count value (T15 T00) Capture data register IN1, input
Edge detection
ICP1 ICP3
ICP0 ICP2
ICE1 ICE3
ICE0 ICE2
Interrupt Interrupt
MB91301 Series
List
CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08
Input capture data register (upper) (IPCP) Input capture data register (lower) (IPCP) Capture control register (ICS23) Capture control register (ICS01)
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
ICP3
ICP2
ICE3
ICE2
EG31
EG30
EG21
EG20
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01
EG00
MB91301 Series
Clock Generation Control
internal operating clock generated follows MB91301 series. Source clock selection Selects clock source. Base clock generation base clock generated dividing source clock using PLL. Generation each internal block base clock divided generate operating clock each block.
MB91301 Series
Block Diagram [Clock generator] DIVR0, register
Selector
clock division Peripheral clock division External clock division CLKR register
Stop control
clock (CLKB) Peripheral clock (CLKP) External clock (CLKT)
tion circuit
Internal interrupt Internal reset
[Stop/sleep controller] Stop state
STCR register State transition control circuit
Selector
Oscilla-
Selector
Selector
SLEEP state Reset Reset Internal reset (RST) Internal reset (INIT)
[Reset circuit] INIT RSRR register [Watchdog controller]
register
Watchdog Timebase counter
CTBR register
Selector
Count clock
TBCR register
Overflow detection
Interrupt enable
Timebase timer interrupt request
MB91301 Series
Register List
RSRR Reset initiation register/Watchdog timer control register
address 00000480H Initial value (INIT pin) Initial value (INIT) Initial value (RST)
INIT
WDOG
SRST
STCR Standby control register
address 00000481H Initial value (INIT pin) Initial value (INIT) Initial value (RST)
STOP
SLEEP
SRST
OSCD1
TBCR Timebase counter control register
address 00000482H Initial value (INIT) Initial value (RST)
TBIF
TBIE
TBC2
TBC1
TBC0
SYNCR SYNCS
CTBR Timebase counter clear register
address 00000483H Initial value (INIT) Initial value (RST)
CLKR Clock source control register
address 00000484H Initial value (INIT) Initial value (RST)
PLL1S2 PLL1S1 PLL1S0
PLL1EN CLKS1
CLKS0
(Continued)
MB91301 Series
(Continued)
Watchdog reset generation delay register
address 00000485H Initial value (INIT) Initial value (RST)
DIVR0 Base clock division setting register
address 00000486H Initial value (INIT) Initial value (RST)
DIVR1 Base clock division setting register
address 00000487H Initial value (INIT) Initial value (RST)
Changes depending what triggered reset. initialized
MB91301 Series
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Rating AVCC AVCC 1000 +150 (VSS AVSS Unit Remaeks
Parameter Supply voltage Analog supply voltage Analog reference voltage Input voltage Analog input voltage Output voltage level maximum output current level average output current level total maximum output current level total average output current level maximum output current level average output current level total maximum output current level total average output current Power consumption Operating temperature Storage temperature
Symbol AVCC AVRH, AVRL IOLAV IOLAV IOHAV IOHAV TSTG
must lower than AVCC, AVRH AVRL should exceed VCC+0.3 including power-on. AVRH AVRL should exceed AVCC. Also AVRL should exceed AVRH. maximum output current peak value single pin. average output current average current single over period 100ms. total average output current average current pins over period 100ms.
WARNING: Semiconductor devices permanently damaged application stress (voltage, current, temperature, etc.) excess absolute maximum ratings. exceed these ratings.
MB91301 Series
Recommended Operating Conditions
Value AVSS AVSS AVCC AVRH
(VSS AVSS Unit Remarks Normal operation
Parameter Supply voltage Analog supply voltage Analog reference voltage Operating temperature
Symbol AVCC AVRH AVRL
<Notes turning power maximum power rising slope (V/t) must 0.05 V/µs when power supply turned takes about until power supply becomes stable after power supply becomes stable. Keep INIT input during that interval. WARNING: recommended operating conditions required order ensure normal operation semiconductor device. device's electrical characteristics warranted when device operated within these ranges. Always semiconductor devices within their recommended operating condition ranges. Operation outside these ranges adversely affect reliability could result device failure. warranty made with respect uses, operating conditions, combinations represented data sheet. Users considering application outside listed conditions advised contact their FUJITSU representatives beforehand.
MB91301 Series
Characteristics
Parameter Symbol VIHS VILS name Non-hysteresis input Hysteresis input Non-hysteresis input Hysteresis input output pins output pins
(VCC AVSS Condition Value Unit Hysteresis input Hysteresis input Remarks
level input voltage
level input voltage level output voltage level output voltage Input leak current (Hi-Z output leak current) Pull-up resistance
-4.0
input pins*1 0.45 With pins Pull- settings 0.45
When operating CLKB CLKT CLKP multiplier) When sleeping CLKP sleep mode stop mode
Power supply current*2 ICCS ICCH Except AVCC AVSS AVRH
(160)
(220)
(75) (300)
(130)
Input capacitance
Excludes pins with internal pull-up resistor (INIT, TRST), pins with pull-up resistor PCR. Values enclosed brackets MB91V301.
MB91301 Series
Characteristics
Clock Timing Ratings Parameter Clock frequency Clock cycle time Clock frequency Internal operation clock frequency Internal operation clock cycle time Sym- name fCPP fCPT tCPP tCPT Condition (VCC AVSS Value 12.5 0.78* 0.78* 0.78* 14.7 29.4 14.7 58.8 1280* 1280* 1280* Unit Remarks Using (When operating internal frequency MHz) self-oscillation with PLL) Self-oscillation (1/2 division input)
Peripherals External Peripherals External
Values minimum clock frequency (12.5 MHz) input oscillation circuit uses PLL, gear ratio 1/16. Conditions measuring clock timing ratings
Output
Warranted operation range
Warranted operation range Power supply
fCPP represented shaded area.
0.78
fCPP (MHz)
Internal clock
MB91301 Series
External/internal clock setting range
fcp, fcpt
multiplier (CPU)
multiplier (CPU)
multiplier (CPU)
fcpp
multiplier, divide (CPU, peripheral)
multiplier, divide (CPU, peripheral) multiplier, divide (CPU, peripheral) multiplier, divide (CPU, peripheral) multiplier, divide (CPU, peripheral)
22.7
multiplier, divide (CPU, peripheral)
divide
12.5
Notes using PLL, input external clock range 12.5 MHz. Allow oscillation stabilization time gear ratio internal clock within values shown "(1) Clock Timing Ratings" table.
MB91301 Series
Clock Output Timing Symbol tCYC tCHCL tCLCH
(VCC AVSS name SYSCLK, MCLK SYSCLK, MCLK SYSCLK, MCLK Condition Value tCPT tCYC-2.35 tCYC-2.35 tCYC+2.65 tCYC+2.65 Unit Remarks
Parameter Cycle time SYSCLKSYSCLK SYSCLKSYSCLK
tCYC tCHCL tCLCH
SYSCLK MCLK
tCYC frequency clock cycle after gearing. following ratings gear ratio ratings when gear ratio between 1/2, 1/8, substitute 1/2, following equation. tCYC 2.35 tCYC 2.65 following rating gear ratio tCYC 2.35 tCYC 2.65 Reset Tool Reset Input Ratings Symbol
(VCC AVSS Condition Value Unit Remarks
Parameter Init input time power-on) Init input time other than power-on) Init input time (recovery from stop)
name
tINTL
INIT, TRST
tINTL
INIT TRST
MB91301 Series
Normal Access Read/Write Operation Symbol tCSLCH tCHCSH tASCH Address setup tASWL tASRL tCHAX Address hold tWHAX tRHAX Valid address Valid data input time delay time delay time minimum pulse width Data setup Data hold time delay time delay time Valid data input time Data setup time Data hold time minimum pulse width setup hold UUB/ULB/LUB/LLB UUB/ULB/LUB/LLB hold tAVDV tCHWL tCHWH tWLWH tDSWH tWHDX tCHRL tCHRH tRLDV tDSRH tRHDX tRLRH tASLCH tCHASH tBLCH tCHBH SYSCLK, SYSCLK, UUB/ ULB/LUB/LLB
(VCC AVSS Condition Value tCYC tCYC tCYC tCYC tCYC tCYC tCYC tCYC tCYC tCYC Unit Remarks
Parameter setup
hold
name SYSCLK, SYSCLK, WR3, SYSCLK, WR3, A00, SYSCLK, WR3, SYSCLK,
When delayed automatic wait insertion input, (tCYC number wait cycles) rated values.
MB91301 Series
tCYC
MCLK SYSCLK
tASLCH
tCHASH
(LBA)
tCSLCH tCHCSH
tASCH
tCHAX
tCHRL
tCHRH tRLRH
tASRL tRLDV tDSRH tAVDV tRHDX
tRHAX
tCHWL tWLWH tCHWH tASWL
tWHAX tWHDX
WR-control)
tDSWH tBLCH
Write
tCHBH
(UUB, ULB, LUB, LLB)
WR-control)
MB91301 Series
Timing Symbol tCHBAH tCHBAL
(VCC AVSS name SYSCLK, Condition Value tCYC Unit Remarks
Parameter setup hold
tCYC
MCLK SYSCLK
tCHBAL tCHBAH
MB91301 Series
Ready Input Timings Symbol tRDYS tRDYH
(VCC AVSS name SYSCLK SYSCLK Condition Value Unit Remarks
Parameter setup time SYSCLK SYSCLK hold time
tCYC
SYSCLK MCLK
tRDYS
tRDYH
tRDYS
tRDYH
(Wait specified RDY)
wait specified RDY)
MB91301 Series
Hold Timing Symbol tCHBGL tCHBGH tXHAL tHAHV
(VCC AVSS name SYSCLK, BGRNT BGRNT, each pins Condition Value tCYC tCYC tCYC tCYC Unit Remarks
Parameter BGRNT delay time BGRNT delay time floating BGRNT time BGRNT valid time
Note time from receiving BGRNT changing cycle more.
tCYC
SYSCLK MCLK
tCHBGL
tCHBGH tHAHV
BGRNT
tHXAL
Other pins High-Z
MB91301 Series
SDRAM Timing
(VCC AVSS Symbol tCYCSD tCHSD tCLSD tODSDCKE tOHSDCKE tODSDRAS tOHSDRAS tODSDCAS tOHSDCAS tODSDWE tOHSDWE tODSDCS tOHSDCS tODSDA tOHSDA tODSDDQM tOHSDDQM tODSDD tOHSDD tISSDD tIHSDD DQMUU, DQMUL, DQMLU, DQMLL CS6, SCAS SRAS MCLKE MCLK name Condition Value Unit Remarks
Parameter Output clock cycle time level clock pulse width level clock pulse width MCLKO output delay time Output hold time MCLKO output delay time Output hold time MCLKO output delay time Output hold time MCLKO output delay time Output hold time MCLKO output delay time Output hold time MCLKO output delay time Output hold time MCLKO output delay time Output hold time MCLKO output delay time Output hold time Data input setup time Data input hold time
MB91301 Series
tCYCSD
MCLKO
tCHSD
tCLSD
MCLKO
MCLKE SRAS SCAS DQMUU DQMUL DQMLU DQMLL
tODSDCKE tODSDRAS tODSDCAS tODSDWE tODSDCS tODSDA tODSDDQM
tOHSDCKE tOHSDRAS tOHSDCAS tOHSDWE tOHSDCS tOHSDA tOHSDDQM
tODSDD
output
tOHSDD
input
tISSDD tIHSDD
MB91301 Series
UART Timing Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
(VCC AVSS name SCK0 SCK2 SCK0 SCK2, SOT0 SOT2 SCK0 SCK2, SIN0 SIN2 SCK0 SCK2, SIN0 SIN2 SCK0 SCK2 SCK0 SCK2 SCK0 SCK2, SOT0 SOT2 SCK0 SCK2, SIN0 SIN2 SCK0 SCK2, SIN0 SIN2 External shift clock mode Internal shift clock mode Condition Value tCYCP tCYCP tCYCP Unit Remarks
Parameter Serial clock cycle time delay time Valid valid hold time Serial clock pulse width Serial clock pulse width delay time Valid SINSCK valid hold time
Notes These ratings synchronous mode. tCYCP peripheral clock cycle time.
MB91301 Series
Internal shift clock mode
tSCYC
SCK0,
tSLOV
SOT0,
tIVSH tSHIX
SIN0,
External shift clock mode
tSLSH tSHSL tSLOV
SCK0,
SOT0,
tIVSH tSHIX
SIN0,
MB91301 Series
(10) Reload Timer Clock Timer Input Timings (VCC AVSS Parameter Symbol tTIWH tTIWL name TIN0 TIN2, PPG0 PPG3, TRG0 TRG3 Condition Value tCYCP Unit Remarks
Input pulse width
Note tCYCP peripheral clock cycle time.
TIN0 TIN2 PPG0 PPG3 TRG0 TRG3
tTIWH tTIWL
(11) Trigger Input Timing Symbol tATGL
(VCC AVSS name Condition Value tCYCP Unit Remarks
Parameter activation trigger input time
Note tCYCP peripheral clock cycle time.
tATGL
MB91301 Series
(12) Controller Timing
(VCC AVSS edge detection (Block/step transfer mode, burst transfer mode) Value SymParameter name Condition Unit Remarks DREQ input pulse width tDRWL DREQ DREQ1 tCYC Note When fCPT fCP, tCYC becomes same level detection (Demand transfer mode) Parameter DSTP setup time DSTP hold time Symbol tDREQS tDREQH name SYSCLK, DREQ DREQ1 SYSCLK, DREQ DREQ1 Condition Value Unit Remarks
operation modes Parameter DACK delay time DEOP delay time IORD delay time IOWR delay time Symbol tCLDL tCLDH tCLEL tCLEH tCLIRL tCLIRH tCLIWL tCLIWH name SYSCLK, DACK DACK1 SYSCLK, DEOP DEOP1 SYSCLK, IORD SYSCLK, IOWR Condition Value Unit Remarks
MB91301 Series
tCYC
SYSCLK MCLK
tCLDL
tCLDH
DACK0, DACK1
tCLEL
tCLEH
DEOP0, DEOP1
tCLIRL
tCLIRH tCLIWL tCLIWH
IORD
IOWR
tDRWL tDREQS tDREQH
DREQ0, DREQ1
DREQ0, DREQ1
MB91301 Series
(13) Timing master mode operation (AVCC AVSS Parameter clock frequency Symbol fSCL SCL0, SCL1 SCL0, SCL1 SCL0, SCL1 SDA0, SDA1 SCL0, SCL1, SDA0, SDA1 SCL0, SCL1, SDA0, SDA1 SCL0, SCL1, SDA0, SDA1 SCL0, SCL1, SDA0, SDA1 pF*4 Conditions Typical mode Fast mode*3 Unit After that, first clock pulse generated. Remarks
period clock tLOW period clock tHIGH free time between "STOP condition" "START condition" SCLSDA output delay time Setup time "repeat START condition" SCLSDA Hold time "repeat START condition" SDASCL Setup time "STOP condition" SCLSDA data

32-Bit Proprietary Microcontroller FR60 MB91301 Series MB91301/30

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