VOLTAGE/LOW SKEW, PCI/PCI-X ZERO DELAY CLOCK GENERATOR Fully inte

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ICS87608I
VOLTAGE/LOW SKEW, PCI/PCI-X ZERO DELAY CLOCK GENERATOR
Fully integrated LVCMOS/LVTTL outputs, typical output impedance Selectable crystal oscillator interface LVCMOS/LVTTL REF_IN clock input Maximum output frequency: 166.67MHz Maximum crystal input frequency: 38MHz Maximum REF_IN input frequency: 41.67MHz Individual banks with selectable output dividers generating 33.333MHz, 66.66MHz, 100MHz 133.333MHz Separate feedback control generating PCI-X frequencies from 16.66MHz 20MHz crystal, 25MHz 33.33MHz reference frequency range: 200MHz 500MHz Cycle-to-cycle jitter: 120ps (maximum) Period jitter, RMS: 20ps (maximum) Output skew: 250ps (maximum) Bank skew: 60ps (maximum) Static phase offset: 160ps 160ps Voltage Supply Modes: (core/inputs), VDDA (analog supply PLL), VDDOA (output bank VDDOB (output bank REF_OUT, FB_OUT) VDD/VDDA/VDDOA/VDDOB 3.3/3.3/3.3/3.3 3.3/3.3/2.5/3.3 3.3/3.3/3.3/2.5 3.3/3.3/2.5/2.5 Lead-Free package available -40°C 85°C ambient operating temperature
VDDOB
GENERAL DESCRIPTION
ICS87608I selectable REF_CLK crystal input. REF_CLK input accepts HiPerClockSLVCMOS LVTTL input levels. ICS87608I fully integrated along with frequency configurable clock feedback outputs multiplying regenerating clocks with "zero delay".
ICS87608I PCI/PCI-X Clock Generator member HiPerClockSfamily high performance clock solutions from ICS. ICS87608I selectable REF_CLK crystal input. REF_CLK input accepts LVCMOS LVTTL input levels. ICS87608I fully integrated along with frequency configurable clock feedback outputs multiplying regenerating clocks with "zero delay". PLL's operating range 250MHz-500MHz, allowing this device used variety general purpose clocking applications. PCI/PCI-X applications particular, frequency should 400MHz. This accomplished supplying 33.33MHz, 25MHz, 20MHz, 16.66MHz reference clock crystal input selecting ÷12, ÷16, ÷20, ÷24, respectively feedback divide value. dividers each output banks then independently configured generate 33.33MHz (÷12), 66.66MHz (÷6), 100MHz (÷4), 133.33MHz (÷3). ICS87608I characterized operate with core supply 3.3V each bank supply 3.3V 2.5V. ICS87608I packaged small 7x7mm body LQFP, making ideal space-constrained applications.
ASSIGNMENT
REF_IN VDDOA XTAL2 XTAL1
VDDOA DIV_SELA0
DIV_SELA1 DIV_SELB0 DIV_SELB1 FBDIV_SEL0 FBDIV_SEL1 FB_IN
ICS87608I
32-Lead LQFP 1.4mm package body package View
XTAL_SEL
PLL_SEL
VDDA
VDDOB REF_OUT FB_OUT
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VOLTAGE/LOW SKEW, PCI/PCI-X ZERO DELAY CLOCK GENERATOR
BLOCK DIAGRAM
DIV_SELA0 DIV_SELA1
XTAL_SEL
REF_IN XTAL1
XTAL2
FB_IN
PLL_SEL
D_SELB1 D_SELB0
REF_OUT FB_OUT
FBDIV_SEL1 FBDIV_SEL0
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VOLTAGE/LOW SKEW, PCI/PCI-X ZERO DELAY CLOCK GENERATOR
Type Output Power Power Input Description Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Power supply ground.
TABLE DESCRIPTIONS
Number Name QA0, QA1, QA2, VDDOA DIV_SELA0, DIV_SELA1, DIV_SELB0, DIV_SELB1 FBDIV_SEL0, FBDIV_SEL1 FB_IN FB_OUT REF_OUT VDDOB QB3, QB2, QB1, PLL_SEL VDDA XTAL_SEL XTAL1, XTAL2 REF_IN
Output supply pins Bank outputs. Active HIGH Master Reset. When logic HIGH, internal dividers Pulldown reset causing outputs low. When logic LOW, internal dividers outputs enabled. LVCMOS LVTTL interface levels. Pulldown Selects divide value clock outputs described Table LVCMOS LVTTL interface levels.
Input
Input Power Input Output Output Power Output Input Power Input Input Input
Pulldown
Selects divide value reference clock output feedback output. LVCMOS LVTTL interface levels. Core supply pin. Feedback input phase detector generating clocks with Pulldown "zero delay". LVCMOS LVTTL interface levels. Feedback output. Connect FB_IN. LVCMOS LVTTL interface levels. Reference clock output. LVCMOS LVTTL interface levels. Output supply pins Bank REF_OUT, FB_OUT outputs. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Selects between bypass mode. When HIGH, selects PLL. When LOW, selects reference clock. LVCMOS LVTTL interface levels. Analog supply pin. Applications Note filtering. Selects between ystal oscillator reference clock reference source. Selects XTAL inputs when HIGH. Selects REF_IN when LOW. LVCMOS LVTTL interface levels. ystal oscillator interface. XTAL1 input. XTAL2 output. Pulldown Reference clock input. LVCMOS LVTTL interface levels.
Pullup
Pullup
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output); NOTE Output Impedance VDD, VDDA, VDDOX 3.465V VDD, VDDA 3.465V; VDDOX 2.625V Test Conditions Minimum Typical Maximum Units
VDDOX denotes VDDOA VDDOB.
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VOLTAGE/LOW SKEW, PCI/PCI-X ZERO DELAY CLOCK GENERATOR
TABLE OUTPUT CONTROL FUNCTION TABLE
Inputs QA0:QA3 Active Outputs QB0:QB3, FB_OUT, REF_OUT Active
TABLE OPERATING MODE FUNCTION TABLE
Inputs PLL_SEL Operating Mode Bypass
TABLE INPUT FUNCTION TABLE
Inputs XTAL_SEL Input REF_IN XTAL Oscillator
TABLE CONTROL FUNCTION TABLE
Inputs FBDIV_ SEL1 FBDIV_ SEL0
Bank Bank Bank Bank
Outputs PLL_SEL DIV_ SELA0 Reference Frequency Range (MHz) 16.67 41.67 16.67 41.67 16.67 41.67 16.67 41.67 12.5 31.25 12.5 31.25 12.5 31.25 12.5 31.25 8.33 20.83 8.33 20.83 8.33 20.83 8.33 20.83 QX0:QX3 5.33 2.667 1.33 6.667 3.33 1.66 Frequency QX0:QX3 (MHz) 66.68 166.68 33.34 83.34 16.67 41.67 66.63 166.56 33.34 83.34 16.63 41.56 66.67 166.68 33.30 83.25 16.60 41.50 66.64 166.64 33.32 83.32 16.66 41.66 FB_OUT (MHz) 16.67 41.67 16.67 41.67 16.67 41.67 16.67 41.67 12.5 31.25 12.5 31.25 12.5 31.25 12.5 31.25 8.33 20.83 8.33 20.83 8.33 20.83 8.33 20.83
DIV_ SELB1
DIV_ SELB0
DIV_ SELA1
NOTE: frequency range configurations above 200MHz 500MHz.
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VOLTAGE/LOW SKEW, PCI/PCI-X ZERO DELAY CLOCK GENERATOR
4.6V -0.5V -0.5V VDDO 0.5V 47.9°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VDDA 3.3V±5%, VDDOX 3.3V±5% 2.5V±5%, -40°C 85°C
Symbol VDDA VDDOX IDDA IDDOA IDDOB Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
VDDOX denotes VDDOA, VDDOB.
TABLE LVCMOS/LVTTL CHARACTERISTICS, VDDA 3.3V±5%, VDDOX 3.3V±5% 2.5V±5%, -40°C 85°C
Symbol Parameter DIV_ SELx0, DIV_SELx1, FBDIV_SEL0, FBDIV_SEL1, Input High Voltage XTAL_SEL, FB_IN, PLL_SEL REF_IN DIV_ SELx0, DIV_SELx1, FBDIV_SEL0, FBDIV_SEL1, Input Voltage XTAL_SEL, FB_IN, PLL_SEL REF_IN DIV_ SELx0, DIV_SELx1, FBDIV_SEL0, FBDIV_SEL1, Input High Current FB_IN XTAL_SEL, PLL_SEL DIV_ SELx0, DIV_SELx1, FBDIV_SEL0, FBDIV_SEL1, Input FB_IN Current XTAL_SEL, PLL_SEL Output High Voltage; NOTE Test Conditions Minimum -0.3 -0.3 3.465V 3.465V 3.465V, 3.465V, 3.465V 2.625V -150 Typical Maximum Units
Output Voltage; NOTE NOTE Outputs terminated with VDDOX/2. Parameter Measurement Information section, "3.3V Output Load Test Circuit".
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VOLTAGE/LOW SKEW, PCI/PCI-X ZERO DELAY CLOCK GENERATOR
Test Conditions Minimum Typical Maximum Units
TABLE CRYSTAL CHARACTERISTICS
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance
Fundamental
TABLE INPUT REFERENCE CHARACTERISTICS, VDDA VDDOX 3.3V±5%, -40°C 85°C
Symbol fREF Parameter Reference Frequency Test Conditions Minimum 8.33 Typical Maximum 41.67 Units
TABLE CHARACTERISTICS, VDDA VDDOX 3.3V±5%, -40°C 85°C
Symbol fMAX sk(b) sk(o) Parameter Output Frequency Static Phase Offset; NOTE Bank Skew; NOTE Output Skew; NOTE Cycle-to-Cycle Jitter; Period Jitter, RMS; NOTE Slew Rate Lock Time Output Rise/Fall Time FREF 25MHz Test Conditions Minimum Typical Maximum 166.67 Units v/ns
tjit(cc) tjit(per) sl(o)
Output Duty Cycle; NOTE parameters measured with feedback output dividers unless otherwise noted. NOTE Defined time difference between input reference clock average feedback input signal when locked input reference frequency stable. Measured VDD/2. NOTE Defined skew within bank outputs same voltages with equal load conditions. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured VDDOX/2. NOTE Jitter performance using LVCMOS inputs. NOTE Measured using REF_IN. XTAL input, refer Application Note. NOTE This parameter defined accordance with JEDEC Standard NOTE This parameter defined value.
TABLE CHARACTERISTICS, VDDA 3.3V±5%, VDDOX 2.5V±5%, -40°C 85°C
Symbol fMAX Parameter Output Frequency Static Phase Offset; NOTE Bank Skew; NOTE Output Skew; NOTE Cycle-to-Cycle Jitter; Period Jitter, RMS; NOTE Slew Rate Lock Time Output Rise/Fall Time
Test Conditions FREF 25MHz
Minimum -365
Typical -105
Maximum 166.67
Units v/ns
sk(b) sk(o) tjit(cc) tjit(per) tsl(o)
Output Duty Cycle; NOTE Table notes.
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VOLTAGE/LOW SKEW, PCI/PCI-X ZERO DELAY CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V±5% 2.05V±5% 1.25V±5%
VDD, VDDA,VDDOX
SCOPE
VDD, VDDA
SCOPE
VDDOX
LVCMOS
LVCMOS
-1.65V±5%
-1.25V±5%
3.3V OUTPUT LOAD TEST CIRCUIT
(Where denotes outputs same Bank)
3.3V/2.5V OUTPUT LOAD TEST CIRCUIT
DDOX
VDDOX
DDOX
sk(o)
sk(b)
VDDOX
OUTPUT SKEW
BANK SKEW
DDOX
DDOX
DDOX
QAx, QAx, QBx, FB_OUT, REF_OUT
87608AYI
REF_IN
tcycle
1000 Cycles
CYCLE-TO-CYCLE JITTER
VDDOX PERIOD VDDOX VDDOX
STATIC PHASE OFFSET
Clock Outputs
PERIOD
OUTPUT PULSE WIDTH/PULSE WIDTH PERIOD
OUTPUT RISE/FALL TIME
REV. JANUARY 2005
jit(cc) tcycle -tcycle
tcycle
FB_IN
ICS87608I
VOLTAGE/LOW SKEW, PCI/PCI-X ZERO DELAY CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS87608I provides separate power supplies isolate high switching noise from outputs internal PLL. VDD, VDDA, VDDOX should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VDDA.
3.3V .01µF .01µF
FIGURE POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
ICS87608I been characterized with 18pF parallel resonant crystals. capacitor values, shown Figure below were determined using 25MHz, 18pF parallel resonant crystal were chosen minimize frequency error. optimum values slightly adjusted optimum frequency accuracy.
XTAL2
18pF Parallel stal
XTAL1
Figure CRYSTAL INPUt INTERFACE
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VOLTAGE/LOW SKEW, PCI/PCI-X ZERO DELAY CLOCK GENERATOR RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
LEAD LQFP
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS87608I 5495
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VOLTAGE/LOW SKEW, PCI/PCI-X ZERO DELAY CLOCK GENERATOR
LEAD LQFP
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.30 0.09 MINIMUM NOMINAL -1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 -0.75 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
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ICS87608I
VOLTAGE/LOW SKEW, PCI/PCI-X ZERO DELAY CLOCK GENERATOR
Marking ICS87608AYI ICS87608AYI ICS87608AYIL ICS87608AYIL Package Lead LQFP Lead LQFP Lead LQFP Lead LQFP Shipping Packaging tray 1000 tape reel tray 1000 tape reel Temperature -40°C 85°C -40°C 85°C -40°C 85°C -40°C 85°C
TABLE ORDERING INFORMATION
Part/Order Number ICS87608AYI ICS87608AYIT ICS87608AYILF ICS87608AYILFT
aforementioned trademark, HiPerClockSis trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 87608AYI
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ICS87608I
VOLTAGE/LOW SKEW, PCI/PCI-X ZERO DELAY CLOCK GENERATOR
REVISION HISTORY SHEET
Table
Page
Description Change Corrected Block Diagram. Parameter Measurement Information 3.3V Outpt Load Test Circuit diagram corrected from "-1.165V±5%" "-1.65V±5%". Ordering Information Table added Lead-Free number. Characteristics Table changed tjit(cc) from 120ps 170ps max.
Date 4/6/04 4/23/04 10/11/04 1/28/05
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VOLTAGE/LOW SKEW, PCI/PCI-X ZERO DELAY CLOCK GENERATOR Fully inte

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