Volt Communications Clock VCXO MK2049-34A VCXO Phased Locked Loop

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Volt Communications Clock VCXO MK2049-34A VCXO Phased Locked Loop

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MK2049-34A
Volt Communications Clock VCXO
MK2049-34A VCXO Phased Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With clock input reference, MK2049-34A generates ISDN, xDSL, other communications frequencies. This allows generation clocks frequency-locked phase-locked backplane clock, simplifying clock synchronization communications systems. MK2409-34 also accept input clock provide same output loop timing. outputs frequency locked together input. This part also jitter-attenuated Buffer capability. this mode, MK2049-34A ideal filtering jitter from video clocks other clocks with high jitter. customize these devices many other different frequencies.
Features
Packaged 20-pin SOIC operation Fixed phase relationship selections Meets TR62411, ETS300 011, GR-1244 specification MTIE, Pull-in/Hold-in Range, Phase Transients, Jitter Generation Stratum Timing frequencies,
Accepts multiple inputs: backplane clock, Loop Locks (External mode) Buffer Mode allows jitter attenuation
input x1/x0.5 x2/x4 outputs
Exact internal ratios enable zero error Output clock rates include ISDN,
xDSL, submultiples
MK2049-01, -02, more selections
Block Diagram
EXTERNAL PULLABLE CRYSTAL
(external loop filter)
INPUT REFERENCE CLOCK (TYPICALLY 8KHZ)
VCXO-BASED (MASTER CLOCK GENERATOR)
FREQUENCY MULTIPLYING
CLOCK OUTPUT CLOCK OUTPUT (REGENERATED)
FREQUENCY SELECT
2049-34A
Integrated Circuit Systems, Inc.
Race Street, Jose, 95126 (408) 297-1201
Revision 032504
www.icst.com
MK2049-34A Volt Communications Clock VCXO
Assignment
FCAP CLK/2 CAP2 CAP1 ICLK
20-pin (300) SOIC
Descriptions
Number
Name
FCAP CLK/2 ICLK CAP1 CAP2
Type
Input Power Power Power Output Output Output Input Input Input Power Power Loop Filter Power Loop Input
Frequency select Determines input/outputs table page Crystal connection. Connect crystal shown table page Crystal connection. Connect crystal shown table page Power supply. Connect +3.3 Filter capacitor. Connect 1000 ceramic capacitor ground. Power supply. Connect +3.3 Connect ground Clock output determined status FS3:0 tables page Clock output determined status FS3:0 tables page Always CLK. Recovered clock output. Frequency select Determines input/outputs tables page Frequency select Determines input/outputs tables page Input clock connection. Connect backplane clock. Connect ground. Power Supply. Connect +3.3 Connect loop filter ceramic capacitors resistor between this CAP2. Connect ground. Connect loop filter ceramic capacitors resistor between this Connect 10-200k resistor ground. Contact telecom@icst.com recommended value your application. Frequency select Determines input/outputs table page
2049-34A
Integrated Circuit Systems, Inc.
Race Street, Jose, 95126 (408) 297-1201
Revision 032504
www.icst.com
MK2049-34A Volt Communications Clock VCXO
Output Decoding Table External Mode (MHz)
ICLK CLK/2 1.544 2.048 22.368 17.184 19.44 16.384 17.664 18.688 7.68 10.752 10.24 38.88 3.088 4.096 44.736 34.368 38.88 32.768 35.328 37.376 15.36 21.504 20.48 77.76 Crystal Used (MHz) 12.352 12.288 11.184 11.456 9.72 8.192 17.664 9.344 15.36 10.752 10.24 9.72 1544 1536 1398 1432 1215 1024 2208 1168 1920 1344 1280 1215
Output Decoding Table Loop Timing Mode (MHz)
ICLK 1.544 2.048 CLK/2 1.544 2.048 3.088 4.096 Crystal 12.352 12.288
Output Decoding Table Buffer Mode (MHz)
ICLK CLK/2 ICLK/2 2*ICLK ICLK 4*ICLK Crystal ICLK/2 ICLK
connect directly ground, connect directly Crystal connected pins clock input applied
Operating Modes
MK2049-34A three operating modes: External, Loop Timing, Buffer. Although each mode uses input clock generate various output clocks, there important differences their input crystal requirements.
External Mode
MK2049-34 accepts external clock will produce number common communication clock frequencies. input clock does need have duty cycle; "high" "on" pulse narrow acceptable. MK2049-34, rising edges CLK/2 both aligned with rising edge ICLK; refer Figure page more details.
Loop Timing Mode
This mode used remove jitter from standard high-frequency communication clocks. inputs, CLK/2 output will same input frequency, with twice input frequency.
2049-34A
Integrated Circuit Systems, Inc.
Race Street, Jose, 95126 (408) 297-1201
Revision 032504
www.icst.com
MK2049-34A Volt Communications Clock VCXO
Buffer Mode
Unlike other modes that accept only single specified input frequency, Buffer Mode will accept wider range input clocks. input jitter attenuated outputs CLK/2 also provide option getting input frequency. example, this mode used remove jitter from clock, generating low-jitter 13.5 outputs.
Input Output Synchronization
shown tables page MK2049-34A offers Zero Delay feature selections. There internal feedback path between ICLK output clocks, providing fixed phase relationship between input output, requirement many communication systems. rising edge ICLK will aligned with rising edges CLK/2 used this illustration, same true selections Loop Timing Buffer Modes).
Measuring Zero Delay MK2049
MK2049-34 produces low-jitter output clocks. addition, this part very bandwidth order Hertz. Since most input clocks will have high jitter, this make measuring input-to-output skew (zero delay feature) very difficult. MK2049 designed reject input jitter; when input output clocks both displayed oscilloscope, they appear locked because scope trigger point constantly changing with input jitter. fact, input output clocks probably locked MK2049 will have zero delay average position input clock. order this clearly, jitter input clock necessary. Most frequency sources SUITABLE this since they have high jitter frequencies.
Frequency Locking Input
modes, output clocks frequency-locked input. outputs will remain specified output frequency long combined variation input frequency crystal does exceed ppm. example, crystal vary (initial accuracy temperature aging), then input frequency vary still have output clock remain frequency-locked.
2049-34A
Integrated Circuit Systems, Inc.
Race Street, Jose, 95126 (408) 297-1201
Revision 032504
www.icst.com
MK2049-34A Volt Communications Clock VCXO
Board Layout
proper board layout critical successful MK2049-34A. particular, CAP1 CAP2 pins very sensitive noise leakage (CAP2 most sensitive). Traces must short possible capacitors resistor must mounted next device shown below. capacitor shown between pins between pins power supply decoupling capacitors. high frequency output clocks pins should have series termination connected close pin. Additional improvements will come from keeping components same side board, minimizing vias through other signal layers, routing other signals away from MK2049. also refer application note MAN05 additional suggestions layout crystal selection. crystal traces should include pads small capacitors from ground. These used adjust stray capacitance board match crystal load capacitance. typical telecom reference frequency accurate much less than ppm, MK2049-34A lock properly even board capacitance adjusted with these fixed capacitors. However, recommends that adjustment capacitors included minimize effects variation individual crystals, temperature, aging. value these capacitors (typically determined once given board layout, using procedure found application note MAN05
Cutout ground power plane. Route traces away from this area. Optional text
resist
resist
resist
connect connect
resist
Figure Typical MK2049-34 Layout
2049-34A
Integrated Circuit Systems, Inc.
Race Street, Jose, 95126 (408) 297-1201
Revision 032504
www.icst.com
MK2049-34A Volt Communications Clock VCXO
External Component Selection
MK2049-34A requires minimum number external components proper operation. Decoupling capacitors 0.01µF must connected between pins close chip (especially pins 17), series terminating resistors should used clock outputs with traces longer than inch (assuming traces). selection additional external components described following sections.
Loop Filter
Information configure external loop filter, connected between pins CAP1 CAP2, found
Crystal Operation
MK2049-34A operates phase locking input signal VCXO which consists recommended pullable VCXO crystals integrated VCXO oscillator circuit MK2049-34A. achieve best performance reliability, layout guidelines shown previous page should closely followed. frequency oscillation quartz crystal determined load capacitors connected MK2049-34A variable load capacitors on-chip which "pull" change frequency crystal. External stray capacitance must kept minimum ensure maximum pullability crystal. achieve this, layout should short traces between MK2049-34A crystal. VCXO operate correctly, pullable crystal must used. more information, including list approved crystals, please refer application note MAN05
Absolute Maximum Ratings
Stresses above ratings listed below cause permanent damage MK2049-34A. These ratings, which standard values commercially rated parts, stress ratings only. Functional operation device these other conditions above those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect product reliability. Electrical parameters guaranteed only over recommended operating temperature range.
Item
Supply Voltage, Inputs Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature
Rating
-0.5 VDD+0.5 +85°C +150°C 175°C 250°C
2049-34A
Integrated Circuit Systems, Inc.
Race Street, Jose, 95126 (408) 297-1201
Revision 032504
www.icst.com
MK2049-34A Volt Communications Clock VCXO
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured respect GND)
Min.
+3.15
Typ.
+3.3
Max.
+3.45
Units
Electrical Characteristics
Unless stated otherwise, ±5%, Ambient Temperature +85°C
Parameter
Operating Voltage Input High Voltage Input Voltage Output High Voltage (CMOS Level) Output High Voltage Output Voltage Operating Supply Current Short Circuit Current Input Capacitance
Symbol
Conditions
Min.
3.15
Typ.
Max.
3.45
Units
Load, VDD=3.3 Each Output FS3:0
VDD-0.4
Electrical Characteristics
Unless stated otherwise, ±5%, Ambient Temperature +85°
Parameter
Input Frequency Input Clock Pulse Width Propagation Delay Output-Output Skew Output Clock Rise Time Output Fall Time Output Clock Duty Cycle, High Time Actual mean frequency error versus target
Symbol
Conditions
External Mode, Note ICLK
Min.
Typ.
Max. Units
ICLK ICLK CLK/2 VDD/2, except clock selection
Note loop timing modes buffer modes, tables page required input clock frequencies
2049-34A
Integrated Circuit Systems, Inc.
Race Street, Jose, 95126 (408) 297-1201
Revision 032504
www.icst.com
MK2049-34A Volt Communications Clock VCXO
Package Outline Package Dimensions (20-pin SOIC, Mil. Wide Body)
Package dimensions kept current with JEDEC Publication
Millimeters
Inches
Symbol
INDEX AREA
-2.65 0.10 -0.33 0.51 0.18 0.32 12.60 13.00 7.40 7.60 1.27 BASIC 10.00 10.65 0.25 0.75 0.40 1.27
-.104 .0040 -.013 .020 .007 .013 .496 .512 .291 .299 0.050 BASIC .394 .419 .010 .029 .016 .050
SEATING PLANE
(.004)
Ordering Information
Part Order Number
MK2049-34SAI MK2049-34SAITR
Marking
MK2049-34SAI MK2049-34SAI
Shipping packaging
Tubes Tape Reel
Package
20-pin SOIC 20-pin SOIC
Temperature
+85° +85°
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments.
2049-34A
Integrated Circuit Systems, Inc.
Race Street, Jose, 95126 (408) 297-1201
Revision 032504
www.icst.com

Volt Communications Clock VCXO MK2049-34A VCXO Phased Locked Loop

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