SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER Fully
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ICS87951I
SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER
Fully integrated single ended 3.3V LVCMOS/LVTTL outputs Selectable single ended CLK0 differential CLK1, nCLK1 inputs single ended CLK0 input accept following input levels: LVCMOS LVTTL input levels CLK1, nCLK1 supports following input types: LVDS, LVPECL, LVHSTL, SSTL, HCSL Output frequency range: 25MHz 180MHz range: 200MHz 480MHz External feedback "zero delay" clock regeneration Cycle-to-cycle jitter: ±100ps (typical) Output skew: 375ps (maximum) reference zero delay: 350ps window (maximum) 3.3V operating supply -40°C 85°C ambient operating temperature compatible with MPC951
GENERAL DESCRIPTION
ICS87951I voltage, skew 1-to-9 Differential-to-LVCMOS/LVTTL Cock Generator HiPerClockSand member HiPerClockSfamily High Performance Clock Solutions from ICS. ICS87951I selectable clock inputs. single ended clock input accepts LVCMOS LVTTL input levels. CLK1, nCLK1 pair accept most standard differential input levels. With output frequencies 180MHz, ICS87951I targeted high performance clock applications. Along with fully integrated PLL, ICS87951I contains frequency configurable outputs external feedback input regenerating clocks with "zero delay".
ASSIGNMENT
CLK_SEL PLL_SEL CLK0 VDDO
VDDA EXT_FB DIV_SELA DIV_SELB DIV_SELC DIV_SELD CLK1
nCLK1 MR/nOE VDDO VDDO
VDDO VDDO
ICS87951I
32-Lead LQFP 1.4mm package body package View
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REV. JULY 2003
ICS87951I
SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER
BLOCK DIAGRAM
DIV_SELA Internal Pulldown PLL_SEL Internal Pulldown CLK0 Internal Pulldown CLK_SEL
Internal Pulldown
nCLK1 CLK1
Internal Pulldown/ Pullup
PHASE DETECTOR 200-480MHz
EXT_FB Internal Pullup DIV_SELB Internal Pulldown
DIV_SELC Internal Pulldown MR/nOE Internal Pulldown
POWER-ON RESET
DIV_SELD Internal Pulldown
87951AYI
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ICS87951I
SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER
Type Power Input Input Input Input Input Power Input Input Input Pullup Pullup Pulldown Pulldown Pulldown Pulldown Description Analog supply pin. Feedback input phase detector regenerating clocks with "zero delay". LVCMOS LVTTL interface levels. Selects divide value Bank output described Table LVCMOS LVTTL interface levels. Selects divide value Bank output described Table LVCMOS LVTTL interface levels. Selects divide value Bank outputs described Table LVCMOS LVTTL interface levels. Selects divide value Bank outputs described Table LVCMOS LVTTL interface levels. Power supply ground. Non-inver ting differential clock input.
TABLE DESCRIPTIONS
Number Name VDDA EXT_FB DIV_SELA DIV_SELB DIV_SELC DIV_SELD CLK1 nCLK1 MR/nOE
Pulldown Inver ting differential clock input. Active HIGH Master Reset. Active output enable. When logic HIGH, internal dividers reset outputs tri-stated Pulldown (HiZ). When logic LOW, internal dividers outputs enabled. LVCMOS LVTTL interface levels. Output supply pins. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Bank clock output. typical output impedance. LVCMOS LVTTL interface levels. Bank clock output. typical output impedance. LVCMOS LVTTL interface levels. Pulldown LVCMOS LVTTL phase detector reference clock input. Selects between reference clock input Pulldown dividers. When HIGH, selects PLL. When LOW, selects reference clock. LVCMOS LVTTL interface levels. Clock select input. When HIGH, selects CLK0. When LOW, Pulldown selects CLK1, nCLK1. LVCMOS LVTTL interface levels.
VDDO QD4, QD3, QD2, QD1, QC1, CLK0 PLL_SEL CLK_SEL
Power Output Output Output Output Input Input Input
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance VDDA, VDDO 3.47V Test Conditions Minimum Typical Maximum Units
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SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER
Outputs
TABLE OUTPUT CONTROL FUNCTION TABLE
Inputs MR/nOE Enabled Enabled QC0, Enabled QD0:QD4 Enabled
TABLE OPERATING MODE FUNCTION TABLE
Inputs PLL_SEL Operating Mode Bypass
TABLE INPUT FUNCTION TABLE
Inputs CLK_SEL Input CLK1, nCLK1 CLK0
TABLE PROGRAMMABLE OUTPUT FREQUENCY FUNCTION TABLE
Inputs DIV_SELA DIV_SELB DIV_SELC DIV_SELD VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/8 VCO/8 VCO/8 VCO/8 VCO/4 VCO/4 VCO/4 VCO/4 VCO/8 VCO/8 VCO/8 VCO/8 Outputs VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8
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SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER
4.6V -0.5V VDDA -0.5V VDDO 0.5V 42.1°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol VDDA VDDO IDDO IDDA Parameter Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current pins Test Conditions Minimum 3.135 3.135 Typical Maximum 3.465 3.465 Units
TABLE CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter CLK0 DIV_SELA:DIV_SELD, PLL_SEL, CLK_SEL, EXT_FB, MR/nOE CLK0 DIV_SELA:DIV_SELD, PLL_SEL, CLK_SEL, EXT_FB, MR/nOE Test Conditions Minimum -0.3 -0.3 -40mA 40mA ±120 Typical Maximum 1000 0.85 Units
Input High Voltage
Input Voltage
VCMR
Peak-to-Peak CLK1, nCLK1 Input Voltage Common Mode Input Voltage; NOTE Output High Voltage Output Voltage
Input Current NOTE Common mode voltage defined VIH. NOTE single ended applications, maximum input voltage CLK1 nCLK1 VDDA+ 0.3V.
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SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER
Test Conditions Minimum Typical Maximum Units
TABLE INPUT REFERENCE CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol fREF Parameter Input Reference Frequency
TABLE CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol fMAX fVCO Parameter Output Frequency Lock Range CLK0 Static Phase Offset; CLK1, NOTE nCLK1 Output Skew; NOTE fREF 50MHz, Feedback VCO/8 Same Frequencies Test Conditions QA/QB -185 -445 -265 Minimum Typical Maximum ±100 tcycle/2 1000 tcycle/2 1000 Units
tsk(o)
Different Frequencies QAfMAX 150MHz QAfMAX 150MHz
tjit(cc)
tLOCK tPZL tPLZ, tPHZ
Cycle-to-Cycle Jitter; NOTE Lock Time; NOTE Output Rise Time Output Fall Time Output Pulse Width Output Enable Time Output Disable Time
parameters measured fMAX unless noted otherwise. NOTE Defined time difference between input reference clock averaged feedback input signal, when locked input reference frequency stable. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured VDDO/2. NOTE This parameter defined accordance with JEDEC Standard
87951AYI
REV. JULY 2003
ICS87951I
SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V±5% VDDA VDDO
SCOPE
nCLK1
LVCMOS
Cross Points
CLK1
-1.65V±5%
3.3V OUTPUT LOAD TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
tcycle
jit(cc) tcycle -tcycle
1000 Cycles
CYCLE-TO-CYCLE JITTER
0.8V
Clock Outputs
OUTPUT RISE/FALL TIME
VDDO VDDO PERIOD VDDO
mean Phase Jitter mean Static Phase Offset
(where random sample, mean average sampled cycles measured controlled edges)
QCx,
PERIOD
tPERIOD
87951AYI
PHASE JITTER
QCx,
tcycle
tsk(o)
OUTPUT SKEW
nCLK1
VDDO
CLK0, CLK1
0.8V
EXT_FB
STATIC PHASE OFFSET
REV. JULY 2003
ICS87951I
SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER APPLICATION INFORMATION
WIRING DIFFERENTIAL INPUT ACCEPT SINGLE ENDED LEVELS
Figure shows differential input wired accept single ended levels. reference voltage V_REF VDD/2 generated bias resistors This bias circuit should located close possible input pin. ratio
might need adjusted position V_REF center input voltage swing. example, input clock swing only 2.5V 3.3V, V_REF should 1.25V R2/R1 0.609.
Single Ended Clock Input V_REF nCLK 0.1u
FIGURE SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS87951I provides separate power supplies isolate high switching noise from outputs internal PLL. VDDA, VDDO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VDDA pin.
3.3V .01µF .01µF
FIGURE POWER SUPPLY FILTERING
87951AYI
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ICS87951I
SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER
here examples only. Please consult with vendor driver component confirm driver termination requirements. example Figure input termination applies HiPerClockS LVHSTL drivers. using LVHSTL driver from another vendor, their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
CLK1 /nCLK1 accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL other differential signals. Both VSWING must meet VCMR input requirements. Figures show interface examples HiPerClockS CLK1/nCLK1 input driven most common driver types. input interfaces suggested
3.3V 3.3V 3.3V 1.8V nCLK LVHSTL HiPerClockS LVHSTL Driver LVPECL HiPerClockS Input nCLK HiPerClockS Input
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN HIPERCLOCKS LVHSTL DRIVER
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V nCLK LVPECL HiPerClockS Input
3.3V 3.3V LVDS_Driv
nCLK
Receiv
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
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ICS87951I
SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS87951I 2674
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SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.30 0.09 MINIMUM NOMINAL -1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 -0.75 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
87951AYI
REV. JULY 2003
ICS87951I
SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER
Marking ICS87951AYI ICS87951AYI Package Lead LQFP Lead LQFP Tape Reel Count tray 1000 Temperature -40°C 85°C -40°C to85°C
TABLE ORDERING INFORMATION
Part/Order Number ICS87951AYI ICS87951AYIT
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 87951AYI
REV. JULY 2003
ICS87951I
SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER
REVISION HISTORY SHEET Description Change Description Table revised MR/nOE description. Characteristics Table changed max. typical. Added ROUT row. Characteristics changed CLK0 from 3.6V 0.3V added CLK0 row. Updated Single Ended Signal Driving Differential Input diagram. Added CLK/nCLK Input Interface section. Date
Table
Page
7/10/03
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REV. JULY 2003
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