8-bit GSPS TS8388BGL Applications Digital Sampling Oscillosc

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

8-bit GSPS TS8388BGL Applications Digital Sampling Oscillosc

Datasheet Thumbnail

Top Searches for this datasheet

8-bit Resolution Gain Adjust Full Power Input Bandwidth GSPS (min) Sampling Rate SFDR dBc, SINAD 44.3 (7.2 Effective Bits), GSPS, SFDR dBc, SINAD 42.9 (7.0 Effective Bits), GSPS, SFDR dBc, SINAD 40.3 (6.8 Effective Bits), GSPS, 1000 2-tone IMD: (489 MHz, MHz) GSPS lsb, Error Rate (10-13) GSPS Very Input Capacitance: mVpp Differential Single-ended Analog Inputs Differential Single-ended Compatible Clock Inputs LVDS/HSTL Output Compatibility Data Ready Output with Asynchronous Reset Gray Binary Selectable Output Data; Output Mode Power Consumption: 3.9W 70°C Typical Dual Power Supply: Evaluation board: TSEV8388BGL Detailed Specification Request Demultiplexer: TS81102G0: Companion Device Available
8-bit GSPS TS8388BGL
Applications
Digital Sampling Oscilloscopes Satellite Receiver Electronic Countermeasures/Electronic Warfare Direct Down-conversion
Screening
Atmel Standard Screening Level Temperature Range: +90°C -40°C +110°C
Description
TS8388BGL monolithic 8-bit analog-to-digital converter, designed digitizing wide bandwidth analog signals very high sampling rates GSPS. TS8388BGL uses innovative architecture, including on-chip Sample Hold (S/H), fabricated with advanced high-speed bipolar process. on-chip full power input bandwidth, providing excellent dynamic performance undersampling applications (High digitizing).
Rev. 2145A-BDC-03/02
Functional Description
Block Diagram
following figure shows simplified block diagram.
Figure Simplified Block Diagram
GAIN
MASTER/SLAVE TRACK HOLD AMPLIFIER VIN, VINB RESISTOR CHAIN ANALOG ENCODING BLOCK INTERPOLATION STAGES
REGENERATION LATCHES ERROR CORRECTION DECODE LOGIC CLOCK BUFFER OUTPUT LATCHES BUFFERS DRRB GORB DATA, DATAB
CLK, CLKB
Functional Description
TS8388BGL 8-bit GSPS based advanced high-speed bipolar technology featuring cutoff frequency GHz. TS8388BGL includes front-end master/slave Track Hold stage (S/H), followed analog encoding stage interpolation circuitry. Successive banks latches regenerate analog residues into logical data before entering error correction circuitry resynchronization stage followed differential output buffers. TS8388BGL works fully differential mode from analog inputs digital outputs. TS8388BGL features full-power input bandwidth dB). control GORB provided select either Gray Binary data output format. gain control provided order adjust gain. Data Ready output asynchronous reset (DRRB) available TS8388BGL. TS8388BGL uses only vertical isolated transistors together with oxide isolated polysilicon resistors, which allow enhanced radiation tolerance performance drift measured kRad total dose).
TS8388BGL
2145A-BDC-03/02
TS8388BGL
Specifications
Absolute Maximum Ratings
Table Absolute Maximum Ratings
Parameter Positive supply voltage Digital negative supply voltage Digital positive supply voltage Negative supply voltage Maximum difference between negative supply voltages Analog input voltages Maximum difference between VINB Digital input voltage Digital input voltage Digital output voltage Clock input voltage Maximum difference between VCLK VCLKB Maximum junction temperature Storage temperature Lead temperature (soldering 10s) Note: Symbol DVEE VPLUSD DVEE VINB VINB VCLK VCLKB VCLK VCLKB Tstg Tleads GORB DRRB Comments Value -5.7 -0.3 -0.3 +0.3 -0.3 +0.9 VPLUSD VPLUSD -0.5 +1.5 +135 +150 +300 Unit
Absolute maximum ratings limiting values (referenced 0V), applied individually, while other parameters within specified operating conditions. Long exposure maximum rating affect device reliability. thermal heat sink mandatory. "Typical Characterization Results" page
Recommended Operating Conditions
Table Recommended Operating Conditions
Recommended Value Parameter Positive supply voltage Positive digital supply voltage Positive digital supply voltage Negative supply voltages Symbol VPLUSD VPLUSD VEE, DVEE output compatibility LVDS output compatibility Comments 4.75 +1.4 -5.25 +2.4 5.25 +2.6 -4.75 Unit
2145A-BDC-03/02
Table Recommended Operating Conditions (Continued)
Recommended Value Parameter Differential analog input voltage (Full Scale) Clock input power level Operating temperature range Symbol VIN, VINB VINB PCLK, PCLKB Comments differential single-ended single-ended clock input Commercial grade: Industrial grade: ±113 ±125 ±137 Unit mVpp
Electrical Operating Characteristics
DVEE -5V; +5V; -VINB mVpp Full Scale differential input; Digital outputs differentially terminated; (typical) 70°C.
Table Electrical Specifications
Test Level Value Unit Note
Parameter Power Requirements Positive supply voltage Analog Digital (ECL) Digital (LVDS) Positive supply current Analog Digital Negative supply voltage Negative supply current Analog Digital Nominal power dissipation Power supply rejection ratio Resolution Analog Inputs Full Scale Input Voltage range (differential mode) common mode voltage) Full Scale Input Voltage range (single-ended input option) (See Application Notes) Analog input capacitance Input bias current Input Resistance
Symbol
VPLUSD VPLUSD IPLUSD AIEE DIEE PSRR
-5.5
-4.5
bits
VINB VINB
-125 -125 -250
TS8388BGL
2145A-BDC-03/02
TS8388BGL
Table Electrical Specifications (Continued)
Test Level Value Unit Note
Parameter Full Power input Bandwidth Small signal input Bandwidth (10% full scale) Clock Inputs Logic compatibility clock inputs (See Application Notes) Clock inputs voltages (VCLK VCLKB): Logic voltage Logic voltage Logic current Logic current Clock input power level into termination Clock input power level Clock input capacitance
Symbol FPBW SSBW
CCLK
specified clock input power level -1.1 into -1.5
(10)
Digital Outputs Single-ended differential input mode, clock duty cycle (CLK, CLKB), Binary output data format, (typical) 70°C. Full temperature range: +90°C. Logic compatibility digital outputs (Depending value VPLUSD) (See Application Notes) Differential output voltage swings (assuming VPLUSD 0V): open transmission lines (ECL levels) differentially terminated differentially terminated Output levels (assuming VPLUSD open transmission lines: Logic voltage Logic voltage Output levels (assuming VPLUSD differentially terminated: Logic voltage Logic voltage Output levels (assuming VPLUSD differentially terminated: Logic voltage Logic voltage LVDS
(1)(6)
0.70 0.54 -0.88 -1.07 -1.16
1.620 0.825 0.660 -1.62 -0.8 -1.41 -1.40 -1.10
-1.54 -1.34 -1.32
2145A-BDC-03/02
Table Electrical Specifications (Continued)
Test Level Value Unit mV/°C Note
Parameter Differential Output Swing Output level drift with temperature
Symbol
Accuracy Single-ended differential input mode, clock duty cycle (CLK, CLKB), Binary output data format (typical) 70°C. Differential linearity Differential linearity Integral linearity Integral linearity missing codes Gain Input offset voltage Gain error drift Offset error drift Transient Performance Error Rate GSPS, 62.5 settling time -VINB mVpp Overvoltage recovery time 1E-12 Error/ sample
(2)(4)
DNLDNL+ INLINL+
-0.6 -1.2
-0.4 -0.7
(2)(3)
(2)(3)
Guaranteed over specified temperature range ppm/°C ppm/°C
Performance Single-ended differential input clock mode, clock duty cycle (CLK, CLKB), Binary output data format, 70°C, unless otherwise specified. Signal Noise Distortion ratio GSPS, GSPS, GSPS, 1000 dBFS) MSPS, Effective Number Bits GSPS, GSPS, GSPS, 1000 dBFS) MSPS, SINAD ENOB Bits Bits Bits Bits
TS8388BGL
2145A-BDC-03/02
TS8388BGL
Table Electrical Specifications (Continued)
Test Level Value Unit
Parameter Signal Noise Ratio GSPS, GSPS, GSPS, 1000 dBFS) MSPS, Total Harmonic Distortion GSPS, GSPS, GSPS, 1000 dBFS) MSPS, Spurious Free Dynamic Range GSPS, GSPS, GSPS, 1000 dBFS) GSPS, 1000 dBFS) MSPS, Two-tone Inter-modulation Distortion FIN1 GSPS, FIN2 GSPS
Symbol SFDR
Note
Switching Performance Characteristics Figure Figure page Maximum clock frequency Minimum clock frequency Minimum Clock pulse width (high) Minimum Clock pulse width (low) Aperture delay Aperture uncertainty Data output delay Output rise/fall time DATA (20% 80%) Output rise/fall time DATA READY (20% 80%) Data ready output delay Data ready reset delay Jitter TR/TF TR/TF TRDR 0.280 0.350 1150 1110 0.500 0.500 +250 1360 1320 1660 1620 1000 GSPS MSPS (rms)
(2)(5) (2)(10) (11)(12) (11) (14) (15)
(11)
(2)(10) (11)(12)
2145A-BDC-03/02
Table Electrical Specifications (Continued)
Test Level Value Unit clock cycles Note
(9)(13) (14)
Parameter Data data ready Clock pulse width (See "Timing Diagrams" page Data data ready output delay (50% duty cycle) GSPS (See "Timing Diagrams" page Data pipeline delay Notes:
Symbol TOD-TDR
(2)(15)
Differential output buffers internally loaded resistors. Buffer bias current "Definition Terms" page Histogram testing based sampling sinewave MSPS. Output error amplitude around worst code. Maximum jitter value obtained single-ended clock input JTS8388B (chip board): (500 expected TS8388BGL) Digital output back termination options depicted Application Notes. With typical value GSPS, timing safety margin data storing using ECLinPS 10E452 output registers from Motorola® equally shared before after rising edge Data Ready signals (DR, DRB). clock inputs indifferently entered differential single-ended, using levels typical power level into termination resistor inphase clock input. into clock input correspond power level clock generator.) GSPS, 50/50 clock duty cycle, (TC1). -100 (typ) does depend sampling rate. Specified loading conditions digital outputs: controlled impedance traces properly 50/75 terminated, unterminated controlled impedance traces. Controlled impedance traces loaded standard ECLinPS register from Motorola. (i.e.: 10E452) (Typical input parasitic capacitance including package protections.) Termination load parasitic capacitance derating values: controlled impedance traces properly 50/75 terminated: ps/pF additionnal ECLinPS load. Unterminated (source terminated) controlled impedance lines: ps/pF additionnal ECLinPS termination load. Apply proper 50/75 impedance traces propagation time derating values: ps/mm (155 ps/inch) TSEV8388BGL Evaluation Board. Values track each other over temperature, variation TOD-TDR 100°C temperature variation). Therefore TOD-TDR variation over temperature negligible. Moreover, internal (on-chip) package skews between each Data TODs effect considered negligible. Consequently, minimum values never more than apart. same true maximum values (see Advanced Application Notes about "TOD-TDR Variation Over Temperature" page 23). value guarantees performance. value guarantees functionality. value guarantees functionality. value guarantees performance.
TS8388BGL
2145A-BDC-03/02
TS8388BGL
Timing Diagrams
Figure TS8388BGL Timing Diagram GSPS Clock Rate), Data Ready Reset, Clock Held Level
(VIN, VINB)
1000
(CLK, CLKB)
1360 TPD: Clock periods 1360
DIGITAL OUTPUTS
1000
DATA
DATA
1320
DATA
DATA
DATA
DATA
DATA
1320
TC1+TDR-TOD TC1-40
Data Ready (DR, DRB)
TC2+TOD-TDR TC2+40
TRDR
DRRB
(min)
Figure TS8388BGL Timing Diagram GSPS Clock Rate), Data Ready Reset, Clock Held HIGH Level
(VIN, VINB)
XN-1
1000
(CLK, CLKB)
1360 TPD: Clock periods 1360
DIGITAL OUTPUTS
1000
DATA
DATA
1320
DATA
DATA
DATA
DATA
DATA
1320
TC1+TDR-TOD TC1-40
Data Ready (DR, DRB)
TC2+TOD-TDR TC2+40
TRDR
DRRB
(min)
2145A-BDC-03/02
Explanation Test Levels
Table Explanation Test Levels
Notes: Characteristics 100% production tested +25°C(1) (for Temperature range(2)). 100% production tested +25°C(1), sample tested specified temperatures (for Temperature range(2)). Sample tested only specified temperatures. Parameter guaranteed design characterization testing (thermal steady-state conditions specified temperature). Parameter typical value only. 100% production tested over specified temperature range (for "B/Q" Temperature range(2)). Unless otherwise specified, tests pulsed tests: therefore where case ambient temperature. Refer "Ordering Information" page Only values guaranteed (typical values issuing from characterization results).
Functions Description
Table Functions Description
Name VPLUSD VIN, VINB CLK, CLKB <D0:D7> <D0B:D7B> GAIN GORB DIOD/DRRB Function Positive power supply Analog negative power supply Digital positive power supply Ground Differential analog inputs Differential clock inputs
VINB VPLUSD (ECL) VPLUSD +2.4V (LVDS)
Differential output data port Differential data ready outputs range outputs gain adjust Gray Binary digital output select junction temperature measurement/ asynchronous data ready reset
CLKB GAIN GORG DIOD/ DRRB
TS8388BGL
DVEE
TS8388BGL
2145A-BDC-03/02
TS8388BGL
Digital Output Coding
(Non Return Zero) mode, ideal coding: does include gain, offset, linearity voltage errors.
Table Digital Output Coding
Digital Output Differential Analog Input +251 +251 +249 +126 +124 -124 -126 -249 -251 -251 Voltage Level Positive full scale Positive full scale Positive full scale Positive scale Positive scale Bipolar zero Bipolar zero Negative scale Negative scale Negative full scale Negative full scale Negative full scale Binary GORB Floating 11111111 11111111 11111110 11000000 10111111 10000000 01111111 01000000 00111111 00000001 00000000 00000000 Gray GORB 10000000 10000000 10000001 10100000 11100000 11000000 01000000 01100000 00100000 00000001 00000000 00000000 Range
2145A-BDC-03/02
Package Description
Description
Table TS8388BGL Description
Symbol DVEE VINB CLKB B0B, B1B, B2B, B3B, B4B, B5B, B6B, GORB number B10, E11, G11, K10, F10, A10, D10, H11, J11, C11, G10, H10, L10, Function Ground pins. connected external ground plane. positive supply. analog negative supply. digital negative supply. phase analog input signal Sample Hold differential preamplifier. Inverted phase clock input signal (CLK). phase clock input signal. analog input sampled held rising edge signal. Inverted phase clock input signal (CLK). phase digital outputs. LSB. MSB. Inverted phase digital outputs. inverted LSB. inverted MSB. phase Range Bit. Range high leading edge code code 256. Inverted phase Range (OR). phase output Data Ready Signal. Inverted phase output Data Ready Signal (DR). Gray Binary select output format control pin. Binary output format GORB floating VCC. Gray output format GORB connected ground (0V). gain adjust pin. gain default grounded, gain transfer fuction nominally close one. function temperature measurement asynchronous data ready reset active low, single-ended input. +2.4V LVDS output levels otherwise GND(1). connected.
GAIN DIOD/DRRB
VPLUSD Note:
B11, C10, J10, A11,
common mode level output buffers 1.2V below positive digital supply. compatibility positive digital supply must (ground). LVDS compatibility (output common mode +1.2V) positive digital supply must 2.4V. subsequent LVDS circuitry withstand lower level input common mode, recommended lower positive digital supply level same proportion order spare power dissipation.
TS8388BGL
2145A-BDC-03/02
TS8388BGL
TS8388BGL Pinout
Figure TS8388BGL Pinout CBGA Package
VPLUSD
DVEE
VPLUSD
VPLUSD
DVEE
VPLUSD
Gorb
GAIN
VINB
Ball Index other side
CLKB
Diode
BOTTOM VIEW
2145A-BDC-03/02
Typical Characterization Results
Static Linearity
MSPS/FIN Figure Integral Linearity
Note:
Clock Frequency MSPS; Signal Frequency MHz; Positive peak: 0.78 lsb; Negative peak: -0.73
Figure Differential Linearity
Note:
Clock Frequency MSPS; Signal Frequency MHz; Positive peak: lsb; Negative peak: -0.39
TS8388BGL
2145A-BDC-03/02
TS8388BGL
Effective Number Bits Versus Power Supplies Variation
Figure Effective Number Bits (VEEA); MSPS;
ENOB (bits) -6.5 -5.5 VEEA -4.5
Figure Effective Number Bits (VCC); MSPS;
ENOB (bits)
Figure Effective Number Bits (VEED); MSPS;
ENOB (bits) -5.5 -4.5 VEED -3.5
2145A-BDC-03/02
Typical Results
Figure GSPS;
Figure GSPS;
Figure GSPS; Full Scale Input)
TS8388BGL
2145A-BDC-03/02
TS8388BGL
Spurious Free Dynamic Range Versus Input Amplitude
Figure Sampling Frequency: GSPS; Input Frequency MHz; Full Scale; ENOB 6.4; SINAD dBc; SFDR dBc; Gray Binary Output Coding
Figure Sampling Frequency: GSPS; Input Frequency MHz; Full Scale; ENOB 6.6; SINAD 40.8 dBc; SFDR dBc; Gray Binary Output Coding
2145A-BDC-03/02
Dynamic Performance Versus Analog Input Frequency
Figure ENOB (dB)
GSPS, 1600 MHz, Full Scale input (FS), Clock duty cycle 50/50, Binary/Gray output coding, fully differential single-ended analog clock inputs.
ENOB (dB)
1000
1200
1400
1600
1800
Input frequency (MHz)
Figure (dB)
(dB) 1000 1200 1400 1600 1800 Input frequency (MHz)
Figure SFDR (dBc)
SFDR (dBc) 1000 1200 1400 1600 1800 Input frequency (MHz)
TS8388BGL
2145A-BDC-03/02
TS8388BGL
Effective Number Bits (ENOB) Versus Sampling Frequency
Figure ENOB (dB)
FS/2 ENOB (dB)
Analog Input Frequency: Nyquist conditions (FIN FS/2) Clock duty cycle 50/50, Binary output coding
1000 1200 1400 1600 Sampling frequency (MSPS)
SFDR Versus Sampling Frequency
Figure SFDR (dBc)
SFDR (dBc)
Analog Input Frequency: Nyquist conditions (FIN FS/2) Clock duty cycle 50/50, Binary output coding
FS/2 1000 1200 1400 1600 Sampling frequency (MSPS)
2145A-BDC-03/02
TS8388BGL Performances Versus Junction Temperature
Figure Effective Number Bits Versus Junction Temperature GSPS; MHz; Duty Cycle
ENOB (bits)
Temperature (°C)
Figure Signal Noise Ratio Versus Junction Temperature GSPS; MHz; Differential Clock; Single-ended Analog Input (VIN dBFs)
(dB)
Temperature (°C)
Figure Total Harmonic Distorsion Versus Junction Temperature GSPS; MHz; Differential Clock; Single-ended Analog Input (VIN dBFs)
(dB)
Temperature (°C)
TS8388BGL
2145A-BDC-03/02
TS8388BGL
Figure Power Consumption Versus Junction Temperature GSPS; MHz; Duty Cycle
Power consumption
Temperature (°C)
Typical Full Power Input Bandwidth
Figure Full Power Input)
Frequency (MHz) 1000 1200 1400 1600 1800 2000
Magnitude (dB)
2145A-BDC-03/02
Step Response
Test pulse input characteristics: input full scale rise time
Note: This step response obtained with TSEV8388B chip on-board (device form).
Figure Test Pulse Digitized with
mV/div ps/div
Time (ns)
Figure Same Test Pulse Digitized with TS8388BGL
code
codes/div (Vpp ps/div
calculated rise time: between
Time (ns)
Note:
Ripples test setup (they present both measurements).
TS8388BGL
2145A-BDC-03/02
TS8388BGL
TS8388BGL Main Timing Information
Timing Value TS8388BGL Timing values defined Table page advanced data, issued from electric simulations first characterizations results fitted with measurements. Timing values given CBGA72 package inputs/outputs, taking into account package internal controlled impedance traces propagation delays, specified termination loads. Propagation delays 50/75 impedance traces taken into account TDR. Apply proper derating values corresponding termination topology. min/max timing values valid over full temperature range following conditions: Specified Termination Load (Differential output Data Data Ready): resistor parallel with standard ECLinPS register from Motorola (i.e.: 10E452) Typical ECLinPS inputs shows typical input capacitance (including package protections). addressing output Dmux, take care some Digital outputs have same termination load apply corresponding derating value given below. Output Termination Load derating values TDR: ps/pF additional ECLinPS load. Propagation time delay derating values have also applied TDR: ps/mm (155 ps/inch) TSEV8388B Evaluation Board. Apply proper time delay derating value different dielectric layer used.
Propagation Time Considerations
Timing values given from include additional propagation times between device pins input/output termination loads. TSEV8388B Evaluation Board, propagation time delay ps/mm (155 ps/inch) corresponding GHz) dielectric constant RO4003 used Board. different dielectric layer used (for instance Teflon), please appropriate propagation time values. does depend propagation times because differential data time difference between Data Ready output delay digital Data output delay). also most straightforward data measure, again because differential: measured directly onto termination loads, with matched Oscilloscopes probes.
TOD-TDR Variation Over Temperature
Values track each other over temperature variation TOD-TDR 100°C temperature variation). Therefore TOD-TDR variation over temperature negligible. Moreover, internal (on-chip) package skews between each Data TODs effect considered negligible. Consequently, minimum values never more than apart. same true maximum values.
2145A-BDC-03/02
other terms: 1150 will 1620 (maximum time delay TDR). 1660 will 1110 (minimum time delay TDR). However, external TOD-TDR values dictated total digital datas skews between every TODs (each digital data) TDR: Board, bonding wires output lines lengths differences, output termination impedance mismatches.
external board) skew effect been taken into account specification minimum maximum values TOD-TDR.
Principle Operation
Analog input sampled rising edge external clock input (CLK, CLKB) after (aperture delay) typically digitized data available after clock periods latency (pipeline delay (TPD)), clock rising edge, after 1360 typical propagation delay TOD. Data Ready differential output signal frequency (DR, DRB) half external clock frequency, that switches same rate digital outputs. Data Ready output signal (DR, DRB) switches external clock falling edge after propagation delay typically 1320 Master Asynchronous Reset input command DRRB (ECL compatible single-ended input) available initializing differential Data Ready output signal (DR, DRB). This feature mandatory certain applications using interleaved ADCs using single with demultiplexed outputs. Actually, without Data Ready signal initialization, impossible store output digital datas defined order.
Principle Data Ready Signal Control DRRB Input Command
Data Ready Output Signal Reset Data Ready signal reset falling edge DRRB input command, logical level (-1.8V). DRRB also tied Data Ready output signal Master Reset. long DRRB remains logical level, tied -5V), Data Ready output remains logical zero independant external free running encoding clock. Data Ready output signal (DR, DRB) reset logical zero after TRDR typical. TRDR measured between -1.3V point falling edge DRRB input command zero crossing point differential Data Ready output signal (DR, DRB). Data Ready Reset command pulse minimum time width.
TS8388BGL
2145A-BDC-03/02
TS8388BGL
Data Ready Output Signal Restart Data Ready output signal restarts DRRB command rising edge, logical high levels (-0.8V). DRRB also Grounded, allowed float, normal free running Data Ready output signal. Data Ready signal restart sequence depends logical level external encoding clock, DRRB rising edge instant: DRRB rising edge occurs when external encoding clock input (CLK, CLKB) LOW: Data Ready output first rising edge occurs after half clock period clock falling edge, after delay time 1320 already defined hereabove. DRRB rising edge occurs when external encoding clock input (CLK, CLKB) HIGH: Data Ready output first rising edge occurs after clock period clock falling edge, delay 1320
Consequently, analog input sampled clock rising edge, first digitized data corresponding first acquisition after Data Ready signal restart (rising edge) always strobed third rising edge data ready signal. time delay (TD1) specified between last point change differential output data (zero crossing point) rising falling edge differential Data Ready signal (DR, DRB) (zero crossing point). normal initialization Data Ready output signal, external encoding clock signal frequency level must controlled. reminded that minimum encoding clock sampling rate MSPS consequently clock cannot stopped. single used both DRRB input command junction temperature monitoring. denomination will DRRB/DIOD. former version denomination DIOD. Temperature monitoring Data Ready control DRRB possible simultaneously.
Analog Inputs (VIN) (VINB)
analog input Full Scale range 0.5V peak peak (Vpp), into termination resistor. differential mode input configuration, that means 0.25V each input, ±125 around input common mode GROUND. typical input capacitance TS8388BGL CQFP package. input capacitance mainly package. protections connected (but present) inputs.
Differential Inputs Voltage Span
Figure Differential Inputs Voltage Span
[mV] Full Scale analog input VINB
-250
-125 (VIN, VINB) ±250 diff
2145A-BDC-03/02
Differential Versus Single-ended Analog Input Operation
TS8388BGL operate full speed either differential single-ended configuration. This explained fact uses high input impedance differential preamplifier stage, (preceeding Sample hold stage), which been designed order entered either differential mode single-ended mode. This true long out-of-phase analog input VINB terminated very closely neighboring shield ground pins (52, which constitute local ground reference inphase analog input (VIN). Thus differential analog input preamplifier will fully reject local ground noise (and capacitively inductively coupled noise) common mode effects. typical single-ended configuration, enter (VIN) input pin, with inverted phase input (VINB) grounded through termination resistor. single-ended input configuration, in-phase input amplitude 0.5V peak peak, centered into 50). inverted phase input ground potential through termination resistor. However, dynamic performances somewhat improved entering either analog clock inputs differential mode.
Typical Single-ended Analog Input Configuration Figure Typical Single-ended Analog Input Configuration
[mV] Full Scale analog input VINB ±250 diff reverse termination VINB double (pins VINB
VINB
package)
-250
Clock Inputs (CLK) (CLKB)
TS8388BGL clocked full speed without noticeable performance degradation either differential single-ended configuration. This explained fact uses differential preamplifier stage clock buffer, which been designed order entered either differential single-ended mode. Recommended sinewave generator characteristics typically -120 dBc/Hz phase noise floor spectral density, from carrier, assuming single tone input clock signal.
Single-ended Clock Input (Ground Common Mode)
Although clock inputs were intended driven differentially with nominal -0.8V/-1.8V levels, TS8388BGL clock buffer manage single-ended sinewave clock signal centered around This most convenient clock input configuration does require power splitter. performance degradation (i.e.: timing jitter) observed this particular singleended configuration GSPS Nyquist conditions (FIN MHz).
TS8388BGL
2145A-BDC-03/02
TS8388BGL
This true long inverted phase clock input terminated very closely neighboring shield ground pins, which constitutes local Ground reference inphase clock input. Thus TS8388BGL differential clock input buffer will fully reject local ground noise (and capacitively inductively coupled noise) common mode effects. Moreover, very phase noise sinewave generator must used enhanced jitter performance. typical inphase clock input amplitude peak peak, centered (ground) common mode. This corresponds typical clock input power level into termination resistor. exceed avoid saturation preamplifier input transistors. inverted phase clock input grounded through termination resistor. Figure Single-ended Clock Input (Ground Common Mode): VCLK common mode VCLKB typical clock input power level (into termination resistor)
+0.5V VCLK CLKB double (pins CLKB
VCLK VCLK -0.5V
package)
reverse termination
Note:
exceed into termination resistor single clock input power level.
Differential Clock Input
clock inputs driven differentially with nominal -0.8V/-1.8V levels. this mode, phase noise sinewave generator used drive clock inputs, followed power splitter (hybrid junction) order obtain degrees phase sinewave signals. Biasing tees used offseting common mode voltage levels. Note: biasing tees propagation times matching, tunable delay line required order ensure signals degrees phase especially fast clock rates GSPS range.
Figure Differential Clock Inputs (ECL Levels)
[mV] -0.8V VCLK VCLKB CLKB double (pins CLKB
Common mode -1.3V
package)
-1.8V
reverse termination
2145A-BDC-03/02
Single-ended Clock Input
single-ended configuration enter (resp. CLKB) pin, with inverted phase Clock input CLKB (respectively CLK) connected -1.3V through termination resistor. inphase input amplitude peak peak, centered -1.3V common mode. Figure Single-ended Clock Input (ECL): VCLK common mode -1.3V; VCLKB -1.3V
-0.8V VCLK
VCLKB -1.3V
-1.8V
Noise Immunity Information
Circuit noise immunity performance begins design level. Efforts have been made design order make device insensitive possible chip environment perturbations resulting from circuit itself induced external circuitry (Cascode stages isolation, internal damping resistors, clamps, internal (on-chip) decoupling capacitors). Furthermore, fully differential operation from analog input digital outputs provides enhanced noise immunity common mode noise rejection. Common mode noise voltage induced differential analog clock inputs will canceled these balanced differential amplifiers. Moreover, proper active signals shielding been provided chip reduce amount coupled noise active inputs. analog inputs clock inputs TS8388BGL device have been surrounded ground pins, which must directly connected external ground plane.
Digital Outputs
TS8388BGL differential output buffers internally loaded. resistors connected digital ground pins through -0.8V level shift diode (see Figure Figure Figure page 30). TS8388BGL output buffers designed driving (default) properly terminated impedance lines coaxial cables. bias current flowing alternately into resistors when switching ensures 0.825V voltage drop across resistor (unterminated outputs). VPLUSD positive supply voltage allows adjustment output common mode level from -1.2V (VPLUSD output compatibility) +1.2V (VPLUSD 2.4V LVDS output compatibility). Therefore, single-ended output voltages vary approximately between -0.8V -1.625V, (outputs unterminated), around -1.2V common mode voltage.
TS8388BGL
2145A-BDC-03/02
TS8388BGL
Three possible line driving back-termination scenarios proposed (assuming VPLUSD 0V): impedance transmission lines, differentially terminated (Figure 32): Each output voltage varies between -1.42V (respectively +1.4V +1V), leading ±0.41V 0.825V differential, around -1.21V (respectively +1.21V) common mode VPLUSD (respectively 2.4V). impedance transmission lines, differentially termination (Figure 33): Each output voltage varies between -1.02V -1.35V (respectively +1.38V +1.05V), leading ±0.33V differential, around -1.18V (respectively +1.21V) common mode VPLUSD (respectively 2.4V). impedance open transmission lines (Figure 34): Each output voltage varies between -1.6V -0.8V (respectively +0.8V +1.6V), which true levels, leading ±0.8V 1.6V differential, around -1.2V (respectively +1.2V) common mode VPLUSD (respectively 2.4V). Therefore, possible drive directly high input impedance storing registers, without terminating transmission lines. time domain, that means that incident wave will reflect transmission line output travel back generator (i.e.: data output buffer). buffer output impedance back reflection will occur.
Note: This longer true transmission line used, latter matching buffer output impedance.
Each differential output termination length must kept identical. recommended decouple midpoint differential termination with capacitor avoid common mode perturbation case slight mismatch differential output line lengths. large mismatches (keep differential line lengths will lead switching currents flowing into decoupling capacitor leading switching ground noise. differential output voltage levels termination) standard voltage levels, however possible drive standard logic circuitry like ECLinPS logic line from Motorola®. sampling rates exceeding GSPS, difficult trigger HP16500 other Acquisition System with digital outputs. becomes necessary regenerate digital data Data Ready means external amplifiers, order able test TS8388BGL optimum performance conditions.
2145A-BDC-03/02
Differential Output Loading Configurations (Levels Compatibility) Figure Differential Output: Terminated
VPLUSD -0.8V -1V/-1.41V
Differential output: +0.41V 0.825V Common mode level: -1.2V (-1.2V below VPLUSD level)
impedance
OutB DVEE
-1.41V/-1V
Figure Differential Output: Terminated
VPLUSD -0.8V -1.02V/-1.35V
Differential output: +0.33V 0.660V Common mode level: -1.2V (-1.2V below VPLUSD level)
impedance
OutB DVEE
-1.35V/-1.02V
Figure Differential Output: Open Loaded
VPLUSD -0.8V -0.8V/-1.6V
Differential output: +0.8V 1.6V Common mode level: -1.2V (-1.2V below VPLUSD level)
impedance
OutB DVEE
-1.6V/-0.8V
TS8388BGL
2145A-BDC-03/02
TS8388BGL
Differential Output Loading Configurations (Levels LVDS Compatibility) Figure Differential Output: Terminated
VPLUSD 2.4V 1.6V 1.4V/0.99V
Differential output: +0.41V 0.825V Common mode level: -1.2V (-1.2V below VPLUSD level)
impedance
OutB DVEE
0.99V/1.4V
Figure Differential Output: Terminated
VPLUSD 2.4V 1.6V 1.38V/1.05V
Differential output: +0.33V 0.660V Common mode level: -1.2V (-1.2V below VPLUSD level)
impedance
OutB DVEE
1.05V/1.38V
Figure Differential Output: Open Loaded
VPLUSD 2.4V 1.6V 1.6V/0.8V
Differential output: +0.8V 1.6V Common mode level: -1.2V (-1.2V below VPLUSD level)
impedance
OutB DVEE
0.8V/1.6V
2145A-BDC-03/02
Range
Range (OR, ORB) provided that goes logical high state when input exceeds positive full scale falls below negative full scale. When analog input exceeds positive full scale, digital output datas remain high logical state, with (OR, ORB) logical one. When analog input falls below negative full scale, digital outputs remain logical state, with (OR, ORB) logical again.
Gray Binary Output Data Format Select
TS8388BGL internal regeneration latches indecision (for inputs very close latches threshold) produce errors logic encoding circuitry leading large amplitude output errors. This fact that latches regenerating internal analog residues into logical states with finite voltage gain value (Av) within given positive amount time (t): exp((t)/), with positive feedback regeneration time constant. TS8388BGL been designed reducing probability occurrence such errors approximately 10-13 (targeted TS8388BGL GSPS). standard technique reducing amplitude such errors down consists outputting digital datas Gray code format. Though TS8388BGL been designed featuring Error Rate 10-13 with binary output format, possible user select between Binary Gray output data format, order reduce amplitude such errors when occurring, storing Gray output codes. Digital Datas format selection: BINARY output format GORB floating VCC. GRAY output format GORB connected ground (0V).
Diode
single used both DRRB input command junction monitoring. denomination DRRB/DIOD. Temperature monitoring Data Ready control DRRB possible simultaneously. (See "Principle Data Ready Signal Control DRRB Input Command" page Data Ready Reset input command). operating junction temperature must kept below 145°C, therefore adequate cooling system diode mounted transistor measured value versus junction temperature given below. Figure Diode
1000 (mV) Junction temperature (°C)
TS8388BGL
2145A-BDC-03/02
TS8388BGL
Gain Control
gain adjustable means (input impedance parallel with pF). gain adjust transfer function given below. Figure Gain Control
1.20 1.15 1.10 Gain 1.05 1.00 0.95 0.90 0.85 0.80 -500
-400
-300
-200
-100
Vgain (command voltage) (mV)
Note:
more information, please refer document "DEMUX ADCs Application Notes".
2145A-BDC-03/02
Equivalent Input/Output Schematics
Figure Equivalent Analog Input Circuit Protections
VCLAMP +2.4V
-0.8V -0.8V
-5.8V -5.8V
+1.65V
E21V E21V
VINB
capacitance 5.8V
capacitance
-1.55V
5.8V
0.8V
0.8V
E21G
E21G
Note:
protection equivalent capacitance
Figure Equivalent Analog Clock Input Circuit Protections
+0.8V
-5.8V -0.8V
-5.8V
-5.8V
-5.8V -5.8V E31V
capacitance
E31V
CLKB
capacitance
5.8V
5.8V
0.8V 0.8V
E21G
E21G
Note:
protection equivalent capacitance
TS8388BGL
2145A-BDC-03/02
TS8388BGL
Figure Equivalent Data Output Buffer Circuit Protections
VPLUSD 2.4V
-5.8V
-5.8V
E01V
E01V
OUTB
5.8V capacitance 0.8V
5.8V capacitance 0.8V
0.8V
0.8V
E21GA
DVEE
Note:
protection equivalent capacitance
Figure Gain Adjust Equivalent Analog Input Circuit Protections
-0.8V
+0.8V
NP1032C2
-5.8V
E22V
capacitance
0.8V
0.8V
5.8V
E22GA
Note:
protection equivalent capacitance
2145A-BDC-03/02
Figure GORB Equivalent Input Schematic Protections GORB: gray binary select input; floating tied binary
-0.8V -0.8V -5.8V
E21VA
GORB
capacitance
5.8V
5.8V 5.8V
E31G
Note:
protection equivalent capacitance
Figure DRRB Equivalent Input Schematic Protections Actual protection range: 6.6V above VEE, fact stress above clipped diode used monitoring
NP1032C2
DRRB
-1.3V capacitance
-2.6V 5.8V
0.8V
E21G
Note:
protection equivalent capacitance
TS8388BGL
2145A-BDC-03/02
TS8388BGL
TSEV8388BF: Device Evaluation Board
complete specification, separate TSEV8388BGL document.
General Description
TSEV8388BGL Evaluation Board (EB) board which been designed order facilitate evaluation characterization TS8388BGL device full power bandwidth GSPS military temperature range. high speed TS8388BGL requires careful attention circuit design layout achieve optimal performance. This four metal layer board with internal ground plane adequate functions order allow quick simple evaluation TS8388BGL performances over temperature range. TSEV8388BGL Evaluation Board very straightforward only implements TS8388BGL ADC, connectors input/output accesses 2.54 pitch connector compatible with HP16500C high frequency probes. board also implements de-embedding fixture order facilitate evaluation high frequency insertion loss input microstrip lines, junction temperature measurement setting. board constituted sandwich dielectric layers, featuring insertion loss enhanced thermal characteristics operation high frequency domain extended temperature range. board dimensions board comes fully assembled tested, with TS8388BGL heatsink installed.
2145A-BDC-03/02
Thermal Moisture Characteristics
Thermal Resistance from Junction Ambient: RTHJA following table lists converter thermal performance parameters device itself, with external heatsink added. Table Thermal Resitance
flow (m/s) Estimated thermal resistance (°C/W) 35.8 30.8 27.4 24.9 21.5 19.3 17.7
Figure Thermal Resistance from Junction Ambient: RTHJA
RTHJA (°C/W)
flow (m/s)
Thermal Resistance from Junction Case: RTHJC
Typical value Rthjc given 6.7°C/W (8°C/W max). This value does include thermal contact resistance between package external component (heatsink PCBoard). example, 2.0°C/W taken thermal grease.
TS8388BGL
2145A-BDC-03/02
TS8388BGL
CBGA68 Board Assembly with External Heasink recommended external heatsink PCBoard special design. Cooling system efficiency monitored using Temperature Sensing Diode, integrated device. Figure CBGA68 Board Assembly
50.5
24.2
20.2 32.5
Board
Moisture Characteristics
This device sensitive moisture (MSL3 according JEDEC standard): Shelf life sealed bag: months <40°C <90% relative humidity (RH). After this opened, devices that will subjected infrared reflow, vapor-phase reflow, equivalent processing (peak package body temperature 220°C) must mounted within hours factory conditions 30°C/60% stored
Devices require baking, before mounting, Humidity Indicator Card >20% when read 23°C ±5°C. baking required, devices baked for: hours 40°C +5°C/-0°C low-temperature device containers, hours 125°C ±5°C high temperature device containers.
2145A-BDC-03/02
Definitions
Definition Terms
(BER) Error Rate Probability exceed specified error threshold sample. error code code that differs more than from correct code. Analog input frequency which fundamental component digitally reconstructed output fallen with respect frequency value (determined analysis) input Full Scale. Ratio expressed signal amplitude, below Full Scale, other spectral components, including harmonics except Ratio expressed signal amplitude, below Full Scale, other spectral components excluding five first harmonics. Ratio expressed first five harmonic components, value measured fundamental spectral component. Ratio expressed signal amplitude, below Full Scale, value next highest spectral component (peak spurious spectral component). SFDR parameter selecting converter used frequency domain application (Radar systems, digital receiver, network analyzer, etc.). reported (i.e.: degrades signal levels lowered), dBFS (i.e.: always related back converter full scale).
(FPBW) Full Power Input Bandwidth
(SINAD) Signal Noise Distortion Ratio (SNR) Signal Noise Ratio (THD) Total Harmonic Distorsion (SFDR) Spurious Free Dynamic Range
(ENOB) Effective Number Bits
ENOB
SINAD 1.76 (A/V/2) 6.02
Where actual input amplitude full scale range under test. (DNL) Differential Linearity Differential Linearity output code difference between measured step size code ideal step size. expressed LSBs. maximum value (i). error specification less than guarantees that there missing output codes that transfer function monotonic. Integral Linearity output code difference between measured input voltage which transition occurs ideal value this transition. expressed LSBs, maximum value |INL (i)|. (DG) Differential Gain peak gain variation percent) five different levels signal Full Scale peak peak amplitude. (TBC). Peak Phase variation degrees) five different levels signal Full Scale peak peak amplitude. (TBC). Delay between rising edge differential clock inputs (CLK, CLKB) (zero crossing point), time which (VIN, VINB) sampled.
(INL) Integral Linearity
(DP) Differential Phase
(TA) Aperture Delay
TS8388BGL
2145A-BDC-03/02
TS8388BGL
(JITTER) Aperture Uncertainty (TS) Settling Time Sample sample variation aperture delay. voltage error jitter depends slew rate signal sampling point. Time delay achieve 0.2% accuracy converter output when Full Scale step function applied differential analog input. Time recover 0.2% accuracy output, after 150% full scale step applied input reduced midscale. Delay from falling edge differential clock inputs (CLK, CLKB) (zero crossing point) next point change differential output data (zero crossing) with specified load. Time delay from Data transition Data ready.
(ORT) Overvoltage Recovery Time (TOD) Digital Data Output Delay (TD1) Time Delay from Data Data Ready (TD2) Time Delay from Data Ready Data (TC) Encoding Clock Period (TPD) Pipeline Delay
General expression with encoding clock period. Minimum clock pulse width (high) Minimum clock pulse width (low) Number clock cycles between sampling edge input data associated output data being made available, (not taking account TOD). TS8388BF clock periods. Delay between falling edge Data Ready output asynchronous Reset signal (DDRB) reset digital zero transition Data Ready output signal (DR). Time delay output DATA signals rize from delta between level high level. Time delay output DATA signals fall from delta between level high level. Ratio input offset variation change power supply voltage.
(TRDR) Data Ready Reset Delay (TR) Rise Time
(TF) Fall Time
(PSRR) Power Supply Rejection Ratio (NRZ) Return Zero
When input signal larger than upper bound input range, output code identical maximum code Range logic one. When input signal smaller than lower bound input range, output code identical minimum code, range logic one. assumed that input signal amplitude remains within absolute maximum ratings). tones intermodulation distortion (IMD) rejection ratio either input tone worst third order intermodulation products. input tones levels Full Scale. measured characterize performance response broad bandwidth signals. When using notch-filtered broadband white-noise generator input under test, Noise Power Ratio defined ratio average out-of-notch average in-notch power spectral density magnitudes spectrum output sample test.
(IMD) InterModulation Distortion (NPR) Noise Power Ratio
2145A-BDC-03/02
Ordering Information
Package Device
8388B
Manufacturer prefix
ceramic
Device family Temperature Range: 90°C 40°C 110°C Package: CBGA72 with
Evaluation Board
8388B
ZA2: with MC100EL16 digital recivers receiver Evaluation board prefix ceramic CBGA72 with
evaluation board delivered with includes heat sink.
TS8388BGL
2145A-BDC-03/02
TS8388BGL
TS8388BGL Capacities Resistances Implant
Figure TS8388BGL Capacities Resistances Implant
DVEE
GAIN
VINB
CLKB
Only on-package marking Electrically isolated
Note:
discrete components 0603 size (1.6 mm).
GORB
2145A-BDC-03/02
Outline Descriptions
Figure Package Dimension Pins CBGA
CBGA package. AL203 substrate. Package design. Corner balls (x4) connected (mechanical ball). Balls 1.27 pitch 11x11 grid. View balls side
side with soldered devices 0.95
(using solder Sn/Pb 63/37)
0.20
1.27
Ball Index other side
Balls side Balls Sn/Pb 63/37 AI203 substrate AI203 Ceramic Cap. Glued substrate
0.15
7.84 7.84
15.00 0.15
0.15 0.30
15.00 0.15 0.80 0.10
1.25 0.12 1.27 Detail ball 0.63 0.10 units
0.40 (Positon array balls edges 0.15 (Positon balls within array)
TS8388BGL
2145A-BDC-03/02
TS8388BGL
Figure Cross Section
0.20
-TTop side with soldered devices (using solder Sn/Pb 63/37) 0.95 Balls side
Balls Sn/Pb 63/37
AI203 substrate
AI203 Ceramic Cap. Glued substrate
(0.200) (0.200) (0.250) (0.200)
1.25 0.12 units
0.15
(0.400)
2145A-BDC-03/02
Datasheet Status Description
Table Datasheet Status
Datasheet Status Objective specification This datasheet contains target goal specifications discussion with customer application validation. This datasheet contains target goal specifications product development. This datasheet contains preliminary data. Additional data published later; could include simulation results. This datasheet contains also characterization results. This datasheet contains final product specification. Validity Before design phase
Target specification
Valid during design phase
Preliminary specification -site
Valid before characterization phase
Preliminary specification -site Product specification Limiting Values
Valid before industrialization phase Valid production purposes
Limiting values given accordance with Absolute Maximum Rating System (IEC 134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application Information Where application information given, advisory does form part specification.
Life Support Applications
These products designed life support appliances, devices systems where malfunction these products reasonably expected result personal injury. Atmel customers using selling these products such applications their risk agree fully indemnify Atmel damages resulting from such improper sale.
TS8388BGL
2145A-BDC-03/02
Atmel Headquarters
Corporate Headquarters
2325 Orchard Parkway Jose, 95131 1(408) 441-0311 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway Jose, 95131 1(408) 441-0311 1(408) 436-4314
RF/Automotive
Theresienstrasse Postfach 3535 74025 Heilbronn, Germany (49) 71-31-67-0 (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, 80906 1(719) 576-3300 1(719) 540-1759
Europe
Atmel Sarl Route Arsenaux Case Postale CH-1705 Fribourg Switzerland (41) 26-426-5555 (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway Jose, 95131 1(408) 441-0311 1(408) 436-4314 Chantrerie 70602 44306 Nantes Cedex France (33) 2-40-18-18-18 (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue Rochepleine 38521 Saint-Egreve Cedex, France (33) 4-76-58-30-00 (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza Mody Road Tsimhatsui East Kowloon Hong Kong (852) 2721-9778 (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France (33) 4-42-53-60-00 (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, 80906 1(719) 576-3300 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride 0QR, Scotland (44) 1355-803-000 (44) 1355-242-743
Japan
Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan (81) 3-3523-3551 (81) 3-3523-7581
e-mail
literature@atmel.com
Site
http://www.atmel.com
Atmel Corporation 2002. Atmel Corporation makes warranty products, other than those expressly contained Company's standard warranty which detailed Atmel's Terms Conditions located Company's site. Company assumes responsibility errors which appear this document, reserves right change devices specifications detailed herein time without notice, does make commitment update information contained herein. licenses patents other intellectual property Atmel granted Company connection with sale Atmel products, expressly implication. Atmel's products authorized critical components life support devices systems. ATMEL registered trademark Atmel. Motorola registered trademark Motorola Company. Other terms product names trademarks others. Printed recycled paper.
2145A-BDC-03/02

8-bit GSPS TS8388BGL Applications Digital Sampling Oscillosc

Top Searches for this datasheet

Other recent searches