CMOS With Programmable Half Full Flag Parallel FIFO Tolerant M672

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CMOS With Programmable Half Full Flag Parallel FIFO Tolerant M672

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M672061E
CMOS With Programmable Half Full Flag Parallel FIFO Tolerant
M672061E implements first-in first-out algorithm, featuring asynchronous read/write operations. FULL EMPTY flags prevent data overflow underflow. Expansion logic allows unlimited expansion word size depth with timing penalties. Twin address pointers automatically generate internal read write addresses, external address information required TEMIC FIFOs. Address pointers automatically incremented with write read pin. bits wide data used data communications applications where parity error checking necessary. Retransmit reset Read pointer zero without affecting write pointer. This very useful retransmitting data when error detected system. Using array eight transistors memory cell, M672061E combine extremely standby supply current (typ with fast access time over full temperature range. versions offer battery backup data retention capability with typical power consumption less than military/space applications that demand superior levels performance reliability M672061E processed according methods latest revision (class ,ESA 9000 QML.
Features
First-in first-out dual port memory 16384 organisation Fast Flag access times: Wide temperature range Programmable Half Full Flag Fully expandable word width depth Asynchronous read/write operations Empty, full half flags single device mode Retransmit capability Bi-directional applications Battery back-up operation data retention compatible Single power supply High Performance SCMOS Technology
Rev. June 1999
M672061E
Interface
Block Diagram
16384
16384
Configuration
mils
(top view)
FL/RT XO/PHF
Rev. June 1999
M672061E
Names
NAMES
I0-8 Q0-8 Inputs Outputs Write Enable Read Enable FL/RT Reset Empty Flag Ground Power Supply First Load/Retransmit Expansion
DESCRIPTION
NAMES
XO/PHF
DESCRIPTION
Full Flag Expansion Out/Programmable HalfFull Flag
Signal Data
Data inputs data Read Enable Write Enable inputs must high state during period shown figure (i.e. tRSS before rising edge should change until tRSR after rising edge Otherwise, pulse write read) during reset operation effect load Programmable Half Full Flag register grow data Inputs I0-I8 data outputs Q0-Q8) (shown figure these cases Full Flag Programmable Half Full Flag reseted high Empty Flag low.
Reset (RS)
Reset occurs whenever Reset (RS) input taken state. Reset returns both internal read write pointers first location. reset required after power-up before write operation enabled. Both
Rev. June 1999
M672061E
Figure Reset write Programmable Half Full Flag register)
(tRR)
Notes
change status during reset, flags will valid tRSC. around rising edge
Figure
Reset (write (read) Programmable Half Full Flag register)
(tRR) tWPW (tRPW) (tRC)
tRSR
I0-I8 (Q0-Q8)
DATA VALID
Write Enable
write cycle initiated falling edge this input Full Flag (FF) set. Data set-up hold times must maintained rise time leading edge Write Enable (W). Data stored sequentially array, regardless current read operation. Once half memory filled, during falling edge next write operation, Programmable Half-Full Flag (PHF) will remain this state until difference between write read pointers less than equal half total available memory device. Programmable Half-Full Flag (PHF) then reset rising edge read operation. prevent data overflow, Full Flag (FF) will low, inhibiting further write operations. completion valid read operation, Full Flag (FF) will high after TRFF, allowing valid write begin. When FIFO stack full, internal write pointer blocked from that external changes will have effect full FIFO stack.
Read Enable
read cycle initiated falling edge Read Enable provided that Empty Flag (EF) set. data accessed first in/first basis, with standing current write operations. After Read Enable goes high, Data Outputs will return high impedance state until next Read operation. When data FIFO stack been read, Empty Flag (EF) will low, allowing "final" read cycle, inhibiting further read operations whilst data outputs remain high impedance state. Once valid write operation been completed, Empty Flag (EF) will high after tWEF valid read then initiated. When FIFO stack empty, internal read pointer blocked from that external changes will have effect empty FIFO stack.
First Load/Retransmit (FL/RT)
This dual-purpose input. Depth Expansion Mode, this connected ground indicate that
Rev. June 1999
M672061E
first loaded (see Operating Modes). Single Device Mode, this acts retransmit input. Single Device Mode initiated connecting Expansion (XI) ground. M672061E made retransmit data when Retransmit Enable Control (RT) input pulsed low. retransmit operation will internal read point first location will affect write pointer. Read Enable Write Enable must high state during retransmit. retransmit feature intended when number writes equals less than depth FIFO occured since last cycle. retransmit feature compatible with Depth Expansion Mode will affect Programmable Half-Full Flag (PHF), accordance with relative locations read write pointers. operations when read pointer equal write pointer, indicating that device empty.
Expansion Out/Half-Full Flag (XO/HF)
This dual-purpose output. single device mode, when Expansion (XI) connected ground, this output acts indication half-full memory. M672061E offers variable offset Half Full condition. offset loaded into register during reset cycle When low, Programmable Half Full Flag (PHF) loaded from DATA inputs I0-I8 pulsing from DATA outputs Q0-Q8 pulsing low. offset options listed table loaded during reset cycle, default offset will half total memory device. Programmable Half-Full Flag (PHF) will will remain until difference between write read pointers less than equal Programmable offset Half Full Flag register been loaded during reset cycle) half total memory Half Full register been loaded during reset cycle). Depth Expansion Mode, Expansion (XI) connected Expansion (XO) previous device. This output acts signal next device Daisy Chain providing pulse next device when previous device reaches last memory location.
Expansion (XI)
This input dual-purpose pin. Expansion (XI) connected indicate operation single device mode. Expansion (XI) connected Expansion (XO) previous device Depth Expansion Daisy Chain modes.
Full Flag (FF)
Full Flag (FF) will low, inhibiting further write operations when write pointer location less than read pointer, indicating that device full. read pointer moved after Reset (RS), Full Flag (FF) will after 16384 writes.
Data Output
DATA output 9-bit wide data. This data high impedance condition whenever Read high state.
Empty Flag (EF)
Empty Flag (EF) will low, inhibiting further read
Rev. June 1999
M672061E
Functional Operating Modes Single Device Mode
single M672061E used when application requirements 16384 words less. M672061E Figure Block Diagram Single 16384
(HALF-FULL FLAG) WRITE DATAIN READ
Single Device Configuration when Expansion (XI) control input grounded (see Figure this mode Programmable Half-Full Flag (PHF), which active output, shared with Expansion (XO).
672061
DATAOUT
FULL FLAG (FF) RESET (RS)
(EF) EMPTY FLAG (RT) RETRANSMIT
EXPANSION (XI)
Width Expansion Mode
Word width increased simply connecting corresponding input control signals multiple devices. Figure
Status flags (EF, PHF) detected from device. Figure demonstrates 18-bit word width using M672061E. word width attained adding additional M672061E.
Block Diagram 16384 FIFO Memory Used Width Expansion Mode.
DATAIN
READ WRITE FULL FLAG RESET (RS) DATAOUT Note Flag detection accomplished monitoring signals either (any) device used width expansion configuration. connect output control signals together. (FF)
672061
672061
(EF) EMPTY FLAG (RT) RETRANSMIT
Rev. June 1999
M672061E
Table Programmable Half Full Flag Offset
16384-64 16384-32 8192 (Half Full) Default Offset
OFFSET
Table Reset retransmit Single Device Configuration/Width Expansion Mode
INPUTS MODE
Reset Retransmit Read/Write
INTERNAL STATUS
OUTPUTS
Read Pointer
Location Zero Location Zero Increment(4)
Write Pointer
Location Zero Unchanged Increment(4)
Note Pointer will increment flag high.
Table Reset First Load Truth Table Depth Expansion/Compound Expansion Mode
INPUTS MODE
Reset First Device Reset Other Devices Read/Write
INTERNAL STATUS
OUTPUTS
Read Pointer
Location Zero Location Zero
Write Pointer
Location Zero Location Zero
Note connected previous device. fig.
Depth Expansion (Daisy Chain) Mode
M672061E easily adapted applications which require more than 16384 words. Figure demonstrates Depth Expansion using three M672061E. depth achieved adding additional 672061. M672061E operates Depth Expansion configuration following conditions first device must designated connecting First Load (FL) control input ground.
other devices must have high state. Expansion (XO) each device must connected Expansion (XI) next device. figure External logic needed generate composite Full Flag (FF) Empty Flag (EF). This requires that EF's (i.e. must generate correct composite EF). figure
Rev. June 1999
M672061E
Retransmit (RT) function Programmable Half-Full Flag (PHF) available Depth Expansion Mode. write flow-through mode (figure 19), FIFO stack allows single word data written immediately after single word data been read from full FIFO stack. line causes reset, line, being low, causes again anticipation data word. word loaded into FIFO stack leading edge line must toggled when order write data into FIFO stack increment write pointer.
Compound Expansion Module
quite simple apply expansion techniques described above together create large FIFO arrays (see figure
Bidirectional Mode
Applications which require data buffering between systems (each system being capable Read Write operations) created coupling M672061E shown figure Care must taken ensure that appropriate flag monitored each system (i.e. monitored device which monitored device which use). Both Depth Expansion Width Expansion used this mode.
Data Flow Through Modes
types flow-through modes permitted read flow-through write flow-through mode. read flow-through mode (figure FIFO stack allows single word read after word been written empty FIFO stack. data enabled (tWEF after leading edge which known first write edge remains until line raised from high, after which will into three-state mode after tRHZ line will show pulse indicating temporary reset then will set. interval which low, more words written FIFO stack (the subsequent writes after first write edge will reset Empty Flag) however, same word (written first write edge) presented output read pointer will incremented low. toggling remaining words written FIFO will appear output accordance with read cycle timings.
Rev. June 1999
M672061E
Figure Block Diagram 49152 FIFO Memory (Depth expansion).
672061
FULL
672061
EMPTY
672061
Figure
Compound FIFO Expansion.
672061 DEPTH EXPANSION BLOCK 672061 DEPTH EXPANSION BLOCK Q(N-8) Q(N-8)
672061 DEPTH EXPANSION BLOCK
I(N-8)
I(N-8)
Notes depth expansion block section Depth Expansion Figure Flag detection section Width Expansion Figure
Figure
Bidirectional FIFO Mode.
672061
PHFB
SYSTEM
SYSTEM
PHFA
672061
Rev. June 1999
M672061E
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage (VCC GND) Input Output voltage applied (GND (Vcc Storage temperature
OPERATING RANGE
Military Automotive
OPERATING SUPPLY VOLTAGE
OPERATING TEMPERATURE
Parameters
Parameter
ICCOP ICCSB ICCPD (10) Notes
Operating supply current Standby supply current Power down current
672061-30
672061-15
UNIT
VALUE
measurements made with outputs open. FL/RT VIH. input Vcc.
PARAMETER
(11) (12) (13) (13) (13) (14) (14) (15) (15) Notes
DESCRIPTION
Input leakage current Output leakage current Input voltage Input high voltage Input high voltage Output voltage Output high voltage Input capacitance Output capacitance
M672061E
UNIT
VALUE
Vcc. VIH, VOUT VCC. -0.3 pulse width input VIH= 2.6V (Com), VIH= 2.8V (Mil, Auto, Ind) min, This parameter sampled tested MHz.
Test Conditions
Input pulse levels Input rise/Fall times
Input timing reference levels Output reference levels Output load
figure
Rev. June 1999
M672061E
Figure Output Load.
OUTPUT
includes scope capacitance
SYMBOL (16) SYMBOL (17)
READ CYCLE TRLRL TRLQV TRHRL TRLRH TRLQX TWHQX TRHQX TRHQZ WRITE CYCLE TWLWL TWLWH TWHWL TDVWH TWHDX RESET CYCLE TRSLWL TRSLRSH TWHRSH TRSHWL tRSC tRSS tRSR tWPW tRPW tRLZ tWLZ tRHZ
PARAMETER
M672061E MIN. MAX.
READ CYCLE
M672061E MIN.
UNIT
MAX.
Read cycle time Access time Read recovery time Read pulse width (19) Read data (20) Write data (20, Data valid from read high Read high data high (20) Write cycle time Write pulse width (19) Write recovery time Data set-up time Data hold time Reset cycle time Reset pulse width (19) Reset set-up time Reset recovery time
WRITE CYCLE
RESET CYCLE
RETRANSMIT CYCLE TRTLWL TRTLRTH TWHRTH TRTHWL FLAGS TRSLEFL TRSLFFH TRLEFL TRHFFH TEFHRH TWHEFH TWLFFL TWLHFL TRHHFH TFFHWH tEFL tHFH, tFFH tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF Reset Reset HF/FF high Read Read high high Read width after high Write high high Write Write Read high high Write width after high tRTC tRTS tRTR Retransmit cycle time Retransmit pulse width (19) Retransmit set-up time (20) Retransmit recovery time
RETRANSMIT CYCLE FLAGS
Rev. June 1999
M672061E
SYMBOL (16) SYMBOL (17)
EXPANSION TWLXOL TWHXOH TXILXIH TXIHXIL TXILRL Notes tXOL tXOH tXIR tXIS Read/Write Read/Write high pulse width recovery time set-up time
PARAMETER
M672061E MIN. MAX.
M672061E MIN. MAX.
UNIT
symbol. symbol. Timings referenced test conditions. Pulse widths less than minimum value allowed. Values guaranteed design, currently tested. Only applies read data flow-through mode. parameters tested only.
Figure
Asynchronous Write Read Operation.
Rev. June 1999
M672061E
Figure Full Flag from Last Write First Read.
Figure Empty Flag from Last Read First Write.
Figure Retransmit.
Note
change status during Retransmit, flags will valid tRTC.
Rev. June 1999
M672061E
Figure Empty Flag Timing
Figure Full Flag Timing
Figure Programmable Half-Full Flag Timing.
PROGRAMMABLE HALF FULL OFFSET LESS PROGRAMMABLE HALF FULL OFFSET LESS
MORE THAN HALF FULL
Rev. June 1999
M672061E
Figure Expansion Out.
Figure Expansion
Figure Read Data Flow Through Mode.
Rev. June 1999
M672061E
Figure Write Data Flow Through Mode.
Rev. June 1999
M672061E
Ordering Information
TEMPERATURE RANGE PACKAGE DEVICE 67206EV SPEED FLOW /883
Preview* pins mils side brazed Flat pack pins mils form
blank /883
standards MIL-STD CLASS QML-Q QML-V
672061 16384 FIFO Very power tolerant Military Space -55° +125°C -55° +125°C
information contained herein subject change without notice. responsibility assumed TEMIC using this publication and/or circuits described herein possible infringements patents other rights third parties which result from use.
Rev. June 1999

CMOS With Programmable Half Full Flag Parallel FIFO Tolerant M672

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