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MPC8250EC / D Rev. 0.9 8 / 2003 MPC8250 Hardware Specifications

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Technical Data
MPC8250EC / D Rev. 0.9 8 / 2003 MPC8250 Hardware Specifications
Freescale Semiconductor, Inc..
This document contains detailed information on power considerations, DC / AC electrical characteristics, and AC timing specifications for the MPC8250 PowerQUICC II communications processor. The following topics are addressed: Topic Section 1.1, "Features" Section 1.2, "Electrical and Thermal Characteristics" Section 1.2.1, "DC Electrical Characteristics" Section 1.2.2, "Thermal Characteristics" Section 1.2.3, "Power Considerations" Section 1.2.4, "AC Electrical Characteristics" Section 1.3, "Clock Configuration Modes" Section 1.3.1, "Local Bus Mode" Section 1.3.2, "PCI Mode" Section 1.4, "Pinout" Section 1.5, "Package Description" Section 1.6, "Ordering Information" Page 2 5 5 10 10 11 19 19 22 28 53 56
The MPC8250 is available in two packages-the standard ZU package (480 TBGA) and an alternate VR package (516 PBGA)-as described in Section 1.4, "Pinout, " and Section 1.5, "Package Description." For more information on VR packages, contact your Motorola sales office. Note that throughout this document references to the MPC8250 are inclusive of its VR version unless otherwise specified.
NOTE: Document Revision History Changes to this document are summarized in Table 23 on page 56.
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Features
Figure 1 shows the block diagram for the MPC8250.
16 Kbytes I-Cache I-MMU G2 Core System Interface Unit (SIU) 16 Kbytes D-Cache D-MMU Bus Interface Unit 60x-to-PCI Bridge 60x-to-Local Bridge Memory Controller Timers Interrupt Controller 32 Kbytes Dual-Port RAM Serial DMAs 4 Virtual IDMAs Clock Counter System Functions 60x Bus
PCI Bus
32 bits, up to 66 MHz or
Local Bus
32 bits, up to 66 MHz
Communication Processor Module (CPM)
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Parallel I / O Baud Rate Generators 32-bit RISC Microcontroller and Program ROM
Time Slot Assigner Serial Interface
4 TDM Ports
3 MII Ports
Non-Multiplexed I / O
Figure 1. MPC8250 Block Diagram
Features
Footprint-compatible with the MPC8260 Dual-issue integer core - A core version of the EC603e microprocessor - System core microprocessor supporting frequencies of 150-200 MHz - Separate 16-Kbyte data and instruction caches: - Four-way set associative - Physically addressed - LRU replacement algorithm - PowerPC architecture-compliant memory management unit (MMU) - Common on-chip processor (COP) test interface - High-performance (4.4-5.1 SPEC95 benchmark at 200 MHz 280 Dhrystones MIPS at 200 MHz) - Supports bus snooping for data cache coherency - Floating-point unit (FPU)
The major features of the MPC8250 are as follows:
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Features
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Separate power supply for internal logic (1.8 V) and for I / O (3.3V) Separate PLLs for G2 core and for the CPM - G2 core and CPM can run at different frequencies for power / performance optimization - Internal core / bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios - Internal CPM / bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios 64-bit data and 32-bit address 60x bus - Bus supports multiple master designs - Supports single- and four-beat burst transfers - 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller - Supports data parity or ECC and address parity 32-bit data and 18-bit address local bus - Single-master bus, supports external slaves - Eight-beat burst transfers - 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller 60x-to-PCI bridge - Programmable host bridge and agent - 32-bit data bus, 66 MHz, 3.3 V - Synchronous and asynchronous 60x and PCI clock modes - All internal address space available to external PCI host - DMA for memory block transfers - PCI-to-60x address remapping
System interface unit (SIU) - Clock synthesizer - Reset controller - Real-time clock (RTC) register - Periodic interrupt timer - Hardware bus monitor and software watchdog timer - IEEE 1149.1 JTAG test access port
Twelve-bank memory controller - Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other userdefinable peripherals - Byte write enables and selectable parity generation - 32-bit address decodes with programmable bank size - Three user programmable machines, general-purpose chip-select machine, and page-mode pipeline SDRAM machine - Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local) - Dedicated interface logic for SDRAM
CPU core can be disabled and the device can be used in slave mode to an external core
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Features
Communications processor module (CPM) - Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications protocols - Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller - Serial DMA channels for receive and transmit on all serial channels - Parallel I / O registers with open-drain and interrupt capability - Virtual DMA functionality executing memory-to-memory and memory-to-I / O transfers - Three fast communications controllers supporting the following protocols: - 10 / 100-Mbit Ethernet / IEEE 802.3 CDMA / CS interface through media independent interface (MII) - Transparent
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- HDLC-Up to T3 rates (clear channel) - One multichannel controller (MCC2) - Handles 128 serial, full-duplex, 64-Kbps data channels. The MCC can be split into four subgroups of 32 channels each. - Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces up to four TDM interfaces per MCC - Four serial communications controllers (SCCs) identical to those on the MPC860, supporting the digital portions of the following protocols: - Ethernet / IEEE 802.3 CDMA / CS - HDLC / SDLC and HDLC bus - Universal asynchronous receiver transmitter (UART) - Synchronous UART - Binary synchronous (BISYNC) communications - Transparent - Two serial management controllers (SMCs), identical to those of the MPC860 - Provide management for BRI devices as general circuit interface (GCI) controllers in timedivision-multiplexed (TDM) channels - Transparent - UART (low-speed operation) - One serial peripheral interface identical to the MPC860 SPI - One inter-integrated circuit (I2C) controller (identical to the MPC860 I2C controller) - Microwire compatible - Multiple-master, single-master, and slave modes - Up to four TDM interfaces - Supports one group of four TDM channels - 2, 048 bytes of SI RAM - Bit or byte resolution - Independent transmit and receive routing, frame synchronization
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Electrical and Thermal Characteristics
- Supports T1, CEPT, T1 / E1, T3 / E3, pulse code modulation highway, ISDN basic rate, ISDN primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and user-defined TDM serial interfaces - Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs, SCCs, SMCs, and serial channels - Four independent 16-bit timers that can be interconnected as two 32-bit timers PCI bridge - PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz - On-chip arbitration - Support for PCI to 60x memory and 60x memory to PCI streaming - PCI Host Bridge or Peripheral capabilities - Includes 4 DMA channels for the following transfers: - PCI-to-60x to 60x-to-PCI - 60x-to-PCI to PCI-to-60x - PCI-to-60x to PCI-to-60x - 60x-to-PCI to 60x-to-PCI - Includes all of the configuration registers (which are automatically loaded from the EPROM and used to configure the MPC8265A) required by the PCI standard as well as message and doorbell registers - Supports the I2O standard - Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0 August 3, 1998) - Support for 66 MHz, 3.3 V specification - 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port - Makes use of the local bus signals, so there is no need for additional pins
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Electrical and Thermal Characteristics
DC Electrical Characteristics
This section provides AC and DC electrical specifications and thermal characteristics for the MPC8250.
This section describes the DC electrical characteristics for the MPC8250. Table 1 shows the maximum electrical ratings.
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Electrical and Thermal Characteristics Table 1. Absolute Maximum Ratings1
Rating Core supply voltage2 PLL supply voltage2 Symbol VDD VCCSYN VDDH VIN Tj TSTG Value -0.3 - 2.5 -0.3 - 2.5 -0.3 - 4.0 GND(-0.3) - 3.6 120 (-55) - (+150) Unit V V V V °C °C
I / O supply voltage3 Input voltage4 Junction temperature Storage temperature range
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Absolute maximum ratings are stress ratings only functional operation (see Table 2) at the maximums is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage. 2 Caution: VDD / VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset. 3 Caution: VDDH can exceed VDD / VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH should not exceed VDD / VCCSYN by more than 2.5 V during normal operation. 4 Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.
Table 2 lists recommended operational voltage conditions.
Table 2. Recommended Operating Conditions1
Rating Core supply voltage PLL supply voltage I / O supply voltage Input voltage Junction temperature (maximum) Ambient temperature
Symbol VDD VCCSYN VDDH VIN Tj TA 1.7 - 1.92 1.7 - 1.92
Value 1.7-2.13 1.7-2.13 3.135 - 3.465 GND (-0.3) - 3.465 1055 0-705 1.9 -2.24 1.9-2.24
Caution: These are the recommended and tested operating conditions. Proper device operating outside of these conditions is not guaranteed. CPU frequency less than or equal to 200 MHz. CPU frequency greater than 200 MHz but less than 233 MHz. CPU frequency greater than or equal to 233 MHz. Note that for extended temperature parts the range is (-40)T - 105Tj.
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Electrical and Thermal Characteristics
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Figure 2. Overshoot / Undershoot Voltage
Table 3 shows DC electrical characteristics.
Table 3. DC Electrical Characteristics1
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Electrical and Thermal Characteristics Table 3. DC Electrical Characteristics1 (Continued)
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Electrical and Thermal Characteristics Table 3. DC Electrical Characteristics1 (Continued)
Symbol VOL
Max 0.4
Unit V
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The default configuration of the CPM pins (PA0-31, PB4-31, PC0-31, PD4-31) is input. To prevent excessive DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs. 2 The leakage current is measured for nominal VDD, VCCSYN, and VDD.
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Electrical and Thermal Characteristics
Thermal Characteristics
Table 4. Thermal Characteristics
Value
Table 4 describes thermal characteristics.
Characteristic
Symbol
480 TBGA (ZU package) 13 10
516 PBGA (VR package) 24 18 16 13 8 6
Air Flow
Junction to ambient- single-layer board1 Junction to ambient- four-layer board Junction to board2 JA
Natural convection 1 m / s °C / W Natural convection 1 m / s °C / W °C / W - -
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Junction to case3
Assumes no thermal vias Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 3 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
Power Considerations
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA.
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Electrical and Thermal Characteristics
Layout Practices
Table 5. Estimated Power Dissipation for Various Configurations1
PINT(W)2 Bus (MHz) CPM Core CPU Multiplier Multiplier CPM (MHz) CPU (MHz) Vddl 1.8 Volts Nominal 66.66 66.66 66.66 66.66 83.33 83.33 83.33
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Vddl 2.0 Volts Nominal 1.8 1.9 2.3 2.4 2.2 2.2 2.4 Maximum 2.3 2.3 2.9 3.1 2.8 2.8 3.1
AC Electrical Characteristics
The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and inputs for the 66 MHz MPC8250 device. Note that AC timings are based on a 50-pf load. Typical output buffer impedances are shown in Table 6.
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Electrical and Thermal Characteristics Table 6. Output Buffer Impedances1
Output Buffers 60x bus Local bus Memory controller Parallel I / O PCI
Typical Impedance () 40 40 40 46 25
Table 7 lists CPM output characteristics.
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Table 7. AC Characteristics for CPM Outputs1
Spec Number Characteristic Max sp36a sp36b sp40 sp38a sp38b sp42 sp42a
Max Delay (ns)
Min Delay (ns)
Table 8 lists CPM input characteristics.
Table 8. AC Characteristics for CPM Inputs1
Spec Number Characteristic Max sp16a sp16b sp20 sp18a sp18b sp22
Setup (ns)
Hold (ns)
Min sp17a sp17b sp21 sp19a sp19b sp23 FCC inputs-internal clock (NMSI) FCC inputs-external clock (NMSI) TDM inputs / SI SCC / SMC / SPI / I2C inputs-internal clock (NMSI) SCC / SMC / SPI / I2C inputs-external clock (NMSI) PIO / TIMER / IDMA inputs
Note that although the specifications generally reference the rising edge of the clock, the following AC timing diagrams also apply when the falling edge is the active edge.
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Electrical and Thermal Characteristics
Figure 3 shows the FCC external clock.
Serial ClKin sp17b sp16b FCC input signals sp36b / sp37b FCC output signals
sp36b / sp37b
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FCC output signals
Figure 3. FCC External Clock Diagram
Figure 4 shows the FCC internal clock.
sp36a / sp37a
FCC output signals
Figure 4. FCC Internal Clock Diagram
Figure 5 shows the SCC / SMC / SPI / I2C external clock.
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Electrical and Thermal Characteristics
Serial CLKin sp18b SCC / SMC / SPI / I2C input signals
(See note.)
sp19b
sp38b / sp39b SCC / SMC / SPI / I2C output signals
(See note.)
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Note: There are four possible timing conditions for SCC and SPI: 1. Input sampled on the rising edge and output driven on the rising edge (shown). 2. Input sampled on the rising edge and output driven on the falling edge. 3. Input sampled on the falling edge and output driven on the falling edge. 4. Input sampled on the falling edge and output driven on the rising edge.
Figure 5. SCC / SMC / SPI / I2C External Clock Diagram
Figure 6 shows the SCC / SMC / SPI / I2C internal clock.
(See note.)
sp19a
sp38a / sp39a SCC / SMC / SPI / I2C output signals
(See note.)
Note: There are four possible timing conditions for SCC and SPI: 1. Input sampled on the rising edge and output driven on the rising edge (shown). 2. Input sampled on the rising edge and output driven on the falling edge. 3. Input sampled on the falling edge and output driven on the falling edge. 4. Input sampled on the falling edge and output driven on the rising edge.
Figure 6. SCC / SMC / SPI / I2C Internal Clock Diagram
Figure 7 shows TDM input and output signals.
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Electrical and Thermal Characteristics
Serial CLKin sp20 TDM input signals sp40 / sp41 TDM output signals Note: There are four possible TDM timing conditions: 1. Input sampled on the rising edge and output driven on the rising edge (shown). 2. Input sampled on the rising edge and output driven on the falling edge. 3. Input sampled on the falling edge and output driven on the falling edge. 4. Input sampled on the falling edge and output driven on the rising edge. sp21
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Figure 7. TDM Signal Diagram
Figure 8 shows PIO, timer, and DMA signals.
Sys clk
sp23 sp22 PIO / IDMA / TIMERTGATE assertion input signals
(See note)
sp23 sp22
TIMER input signal TGATE deassertion
(See note)
sp42 / sp43 IDMA output signals sp42 / sp43 sp42a / sp43a TIMER(sp42 / 43) / PIO(sp42a / sp43a) output signals Note: TGATE is asserted on the rising edge of the clock it is deasserted on the falling edge.
Figure 8. PIO, Timer, and DMA Signal Diagram
Table 9 lists SIU input characteristics.
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Electrical and Thermal Characteristics Table 9. AC Characteristics for SIU Inputs1
Spec Number Characteristic Max sp11 sp12 sp13 sp14 sp15
Setup (ns)
Hold (ns)
Min sp10 sp10 sp10 sp10 sp10 AACK / ARTRY / TA / TS / TEA / DBG / BG / BR Data bus in normal mode Data bus in ECC and PARITY modes DP pins All other pins
66 MHz 83 MHz 66 MHz 83 MHz 6 5 8 7 5 5 4 6 6 4 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5
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Table 10 lists SIU output characteristics.
Table 10. AC Characteristics for SIU Outputs1
Spec Number Characteristic Max sp31 sp32 sp33a sp33b sp34 sp35
Max Delay (ns)
Min Delay (ns)
66 MHz 83 MHz 66 MHz 83 MHz 7 8 6.5 8 6 6 6 6.5 6.5 7 5 5.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5
NOTE Activating data pipelining (setting BRxDR in the memory controller) improves the AC timing. When data pipelining is activated, sp12 can be used for data bus setup even when ECC or PARITY are used. Also, sp33a can be used as the AC specification for DP signals. Figure 9 shows the interaction of several bus signals.
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Electrical and Thermal Characteristics
CLKin sp11 AACK / ARTRY / TA / TS / TEA / DBG / BG / BR input signals sp12 DATA bus normal mode input signal sp15 All other input signals sp31 sp10 sp10 sp10
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All other output signals
Figure 9. Bus Signals
Figure 10 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
CLKin sp10 sp13 DATA bus, ECC, and PARITY mode input signals
sp10 sp14 DP mode input signal
sp33b / sp30 DP mode output signal
Figure 10. Parity Mode Diagram
Figure 11 shows signal behavior in MEMC mode.
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Electrical and Thermal Characteristics
CLKin
Memory controller signals
sp34 / sp30
Figure 11. MEMC Mode Diagram
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NOTE Generally, all MPC8250 bus and system output signals are driven from the rising edge of the input clock (CLKin). Memory controller signals, however, trigger on four points within a CLKin cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge, and T3 at the falling edge, of CLKin. However, the spacing of T2 and T4 depends on the PLL clock ratio selected, as shown in Table 11.
Table 11. Tick Spacing for Memory Controller Signals
Tick Spacing (T1 Occurs at the Rising Edge of CLKin) PLL Clock Ratio T2 1:2, 1:3, 1:4, 1:5, 1:6 1:2.5 1:3.5 1 / 4 CLKin 3 / 10 CLKin 4 / 14 CLKin T3 1 / 2 CLKin 1 / 2 CLKin 1 / 2 CLKin T4 3 / 4 CLKin 8 / 10 CLKin 11 / 14 CLKin
Figure 12 is a graphical representation of Table 11.
CLKin T1 T2 T3 T4 for 1:2, 1:3, 1:4, 1:5, 1:6
CLKin T1 T2 T3 T4
for 1:2.5
CLKin T1 T2 T3 T4
for 1:3.5
Figure 12. Internal Tick Spacing for Memory Controller Signals
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Clock Configuration Modes
Table 12. MPC8250 Clocking Modes
Pins Clocking Mode Local bus PCI host PCI Clock Frequency Range (MHZ) - 50-66 25-50 50-66 PCI agent 25-50 Table 17 and Table 18 Table 15 and Table 16 Reference Table 13 and Table 14
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Determines PCI clock frequency range. Refer to Section 1.3.2, "PCI Mode."
Local Bus Mode
Table 13 shows the eight basic clock configurations for the MPC8250. Another 49 configurations are available by using the configuration pin (RSTCONF) and driving four pins on the data bus.
Table 13. Clock Default Configurations
MODCK1-3 000 001 010 011 100 101 110 111 Input Clock Frequency 33 MHz 33 MHz 33 MHz 33 MHz 66 MHz 66 MHz 66 MHz 66 MHz CPM Multiplication Factor 3 3 4 4 2 2 2.5 2.5 CPM Frequency 100 MHz 100 MHz 133 MHz 133 MHz 133 MHz 133 MHz 166 MHz 166 MHz Core Multiplication Factor 4 5 4 5 2.5 3 2.5 3 Core Frequency 133 MHz 166 MHz 133 MHz 166 MHz 166 MHz 200 MHz 166 MHz 200 MHz
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Clock Configuration Modes Table 14. Clock Configuration Modes1
33 MHz 33 MHz 33 MHz 33 MHz 33 MHz
100 MHz 100 MHz 100 MHz 100 MHz 100 MHz
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz
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33 MHz 33 MHz 33 MHz 33 MHz 33 MHz
133 MHz 133 MHz 133 MHz 133 MHz 133 MHz
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz
33 MHz 33 MHz 33 MHz 33 MHz 33 MHz
166 MHz 166 MHz 166 MHz 166 MHz 166 MHz
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz
33 MHz 33 MHz 33 MHz 33 MHz 33 MHz
200 MHz 200 MHz 200 MHz 200 MHz 200 MHz
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz
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Clock Configuration Modes Table 14. Clock Configuration Modes1 (Continued)
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Reserved
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
133 MHz 133 MHz 133 MHz 133 MHz 133 MHz 133 MHz
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
166 MHz 166 MHz 166 MHz 166 MHz 166 MHz 166 MHz
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz
133 MHz 166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
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Clock Configuration Modes Table 14. Clock Configuration Modes1 (Continued)
Core Multiplication Input Clock CPM Multiplication CPM Core Factor2 Factor2 Frequency2, 3 Frequency2 Frequency2 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 3.5 3.5 3.5 3.5 3.5 3.5 233 MHz 233 MHz 233 MHz 233 MHz 233 MHz 233 MHz 2 2.5 3 3.5 4 4.5 133 MHz 166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
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PCI Mode
PCI Host Mode
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Input Clock CPM Core CPM Core PCI Division PCI Multiplication MODCK1-31 Frequency Multiplication Frequency Frequency Factor2 Frequency2 (Bus) Factor Factor 000 001 010 011 100 101 110 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 66 MHz 2 2 2.5 2.5 2.5 3 3 3 133 MHz 133 MHz 166 MHz 166 MHz 166 MHz 200 MHz 200 MHz 200 MHz 2.5 3 3 3.5 4 3 3.5 4 166 MHz 200 MHz 200 MHz 233 MHz 266 MHz 200 MHz 233 MHz 266 MHz 2 / 4 2 / 4 3 / 6 3 / 6 3 / 6 3 / 6 3 / 6 3 / 6 66 / 33 MHz 66 / 33 MHz 55 / 28 MHz 55 / 28 MHz 55 / 28 MHz 66 / 33 MHz 66 / 33 MHz 66 / 33 MHz
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Table 16. Clock Configuration Modes in PCI Host Mode
Input Clock Frequency1 (Bus) 33 MHz 33 MHz 33 MHz 33 MHz
CPM Core PCI CPM Core PCI Division Multiplication Multiplication Frequency2 Frequency Frequency Factor2 Factor Factor 3 3 3 3 100 MHz 100 MHz 100 MHz 100 MHz 5 6 7 8 166 MHz 200 MHz 233 MHz 266 MHz 3 / 6 3 / 6 3 / 6 3 / 6 33 / 16 MHz 33 / 16 MHz 33 / 16 MHz 33 / 16 MHz
33 MHz 33 MHz 33 MHz 33 MHz
133 MHz 133 MHz 133 MHz 133 MHz
166 MHz 200 MHz 233 MHz 266 MHz
33 MHz 33 MHz 33 MHz 33 MHz
166 MHz 166 MHz 166 MHz 166 MHz
166 MHz 200 MHz 233 MHz 266 MHz
33 MHz 33 MHz 33 MHz 33 MHz
33 MHz 33 MHz 33 MHz
200 MHz 200 MHz 200 MHz
166 MHz 200 MHz 233 MHz
33 MHz 33 MHz 33 MHz
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Clock Configuration Modes Table 16. Clock Configuration Modes in PCI Host Mode (Continued)
Input Clock Frequency1 (Bus) 33 MHz
CPM Core CPM Core PCI Division PCI Multiplication Multiplication Frequency Frequency Factor2 Frequency2 Factor Factor 6 200 MHz 8 266 MHz 6 33 MHz
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
133 MHz 133 MHz 133 MHz 133 MHz 133 MHz
166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
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66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
166 MHz 166 MHz 166 MHz 166 MHz 166 MHz
166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
200 MHz 200 MHz 200 MHz 200 MHz 200 MHz
166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
200 MHz 200 MHz 200 MHz 200 MHz 200 MHz
166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
233 MHz 233 MHz 233 MHz 233 MHz 233 MHz
166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
100 MHz 100 MHz
200 MHz 200 MHz
200 MHz 250 MHz
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Clock Configuration Modes Table 16. Clock Configuration Modes in PCI Host Mode (Continued)
Input Clock Frequency1 (Bus) 100 MHz 100 MHz 100 MHz
CPM Core CPM Core PCI Division PCI Multiplication Multiplication Frequency Frequency Factor2 Frequency2 Factor Factor 2 2 2 200 MHz 200 MHz 200 MHz 3 3.5 4 300 MHz 350 MHz 400 MHz 3 / 6 3 / 6 3 / 6 66 / 33 MHz 66 / 33 MHz 66 / 33 MHz
100 MHz 100 MHz 100 MHz 100 MHz 100 MHz
250 MHz 250 MHz 250 MHz 250 MHz 250 MHz
200 MHz 250 MHz 300 MHz 350 MHz 400 MHz
62 / 31 MHz 62 / 31MHz 62 / 31 MHz 62 / 31 MHz 62 / 31 MHz
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PCI Agent Mode
Input Clock Core CPM CPM Core Bus Division 60x Bus Multiplication MODCK1-31 Frequency Multiplication Frequency Frequency3 Factor Frequency4 (PCI)2 Factor Factor2 000 001 010 011 100 101 110 111
133 MHz 133 MHz 200 MHz 200 MHz 200 MHz 200 MHz 266 MHz 266 MHz
166 MHz 200 MHz 200 MHz 266 MHz 240 MHz 280 MHz 300 MHz 300 MHz
66 MHz 66 MHz 66 MHz 66 MHz 80 MHz 80 MHz 88 MHz 100 MHz
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Clock Configuration Modes Table 18. Clock Configuration Modes in PCI Agent Mode
150 MHz 150 MHz 150 MHz 150 MHz
180 MHz 210 MHz 240 MHz 270 MHz
60 MHz 60 MHz 60 MHz 60 MHz
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133 MHz 133 MHz 133 MHz 133 MHz 133 MHz
110MHz 132 MHz 154 MHz 176MHz 198 MHz
44 MHz 44 MHz 44 MHz 44 MHz 44 MHz
200 MHz 200 MHz 200 MHz 200 MHz 200 MHz
166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
33 MHz 33 MHz 33 MHz 33 MHz 33 MHz
166 MHz 166 MHz 166 MHz 166 MHz 166 MHz
166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
200 MHz 200 MHz 200 MHz 200 MHz 200 MHz
166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
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Clock Configuration Modes Table 18. Clock Configuration Modes in PCI Agent Mode (Continued)
200 MHz 200 MHz 200 MHz 200 MHz 200 MHz 200 MHz
160 MHz 200 MHz 240 MHz 280 MHz 320 MHz 360 MHz
80 MHz 80 MHz 80 MHz 80 MHz 80 MHz 80 MHz
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266 MHz 266 MHz 266 MHz 266 MHz 266 MHz
166 MHz 200 MHz 233 MHz 266 MHz 300 MHz
66 MHz 66 MHz 66 MHz 66 MHz 66 MHz
266 MHz 266 MHz 266 MHz 266 MHz 266 MHz
222 MHz 266 MHz 300 MHz 350 MHz 400 MHz
88 MHz 88 MHz 88 MHz 88 MHz 88 MHz
266 MHz 266 MHz 266 MHz 266 MHz 266 MHz
212MHz 265 MHz 318 MHz 371 MHz 424 MHz
106 MHz 106 MHz 106 MHz 106 MHz 106 MHz
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Pinout
ZU Package
This section provides the pin assignments and pinout list for the MPC8250.
The following figures and table represent the standard 480 TBGA package. For information on the alternate package, refer to Section 1.4.2, "VR Package" on page 40.
ZU Pin Assignments
Figure 13 shows the pinout of the ZU package as viewed from the top surface.
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Not to Scale
Figure 13. Pinout of the 480 TBGA Package as Viewed from the Top Surface
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Pinout
Figure 14 shows the side profile of the TBGA package to indicate the direction of the top surface view.
Copper Heat Spreader (Oxidized for Insulation) Polymide Tape Die Soldermask Glob-Top Filled Area Glob-Top Dam 1.27 mm Pitch Copper Traces Die Attach Etched Cavity Pressure Sensitive Adhesive
Figure 14. Side View of the TBGA Package
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Table 19 shows the pinout list of the ZU package of the MPC8250. Table 20 defines conventions and acronyms used in Table 19.
Table 19. MPC8250 ZU Package Pinout List
Pin Name BR BG ABB / IRQ2 TS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 Ball W5 F4 E2 E3 G1 H5 H2 H1 J5 J4 J3 J2 J1 K4 K3 K2 K1 L5 L4 L3 L2 L1 M5
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Pinout Table 19. MPC8250 ZU Package Pinout List (Continued)
Pin Name A19 A20 A21 A22 A23 A24 A25 A26 Ball N5 N4 N3 N2 N1 P4 P3 P2 P1 R1 R3 R5 R4 F1 G4 G3 G2 F2 D3 C1 E4 D2 F5 F3 E1 V1 V2 B20 A18 A16 A13 E12 D9 A6 B5
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A27 A28 A29 A30 A31 TT0 TT1 TT2 TT3 TT4 TBST TSIZ0 TSIZ1 TSIZ2 TSIZ3 AACK ARTRY DBG DBB / IRQ3 D0 D1 D2 D3 D4 D5 D6 D7
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Pinout Table 19. MPC8250 ZU Package Pinout List (Continued)
Pin Name D8 D9 D10 D11 D12 D13 D14 D15 Ball A20 E17 B15 B13 A11 E9 B7 B4 D19 D17 D15 C13 B11 A8 A5 C5 C19 C17 C15 D13 C11 B8 A4 E6 E18 B17 A15 A12 D11 C8 E7 A3 D18 A17 A14
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D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42
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Pinout Table 19. MPC8250 ZU Package Pinout List (Continued)
Pin Name D43 D44 D45 D46 D47 D48 D49 D50 Ball B12 A10 D8 B6 C4 C18 E16 B14 C12 B10 A7 C6 D5 B18 B16 E14 D12 C10 E8 D6 C2 B22 A22 E21 D21 C21 B21 A21 E20 V3 C22 V5 W1 U2 U3
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Pinout Table 19. MPC8250 ZU Package Pinout List (Continued)
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Pinout Table 19. MPC8250 ZU Package Pinout List (Continued)
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Pinout Table 19. MPC8250 ZU Package Pinout List (Continued)
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Pinout Table 19. MPC8250 ZU Package Pinout List (Continued)
Pin Name TDO TRIS PORESET HRESET SRESET QREQ RSTCONF MODCK1 / AP1 / TC0 / BNKSEL0 Ball AF5 AB4 AG6 AH5 AF6 AA3 AJ4 W2 W3 W4 AB2 AH4 AC291 AC251 AE281 AG291 AG281 AG261 AE241 AH251 AF231 AH231 AE221 AH221 AJ211 AH201 AG191 AF181 AF171 AE161 AJ161 AG151 AJ131 AE131 AF121
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Pinout Table 19. MPC8250 ZU Package Pinout List (Continued)
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Pinout Table 19. MPC8250 ZU Package Pinout List (Continued)
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Pinout Table 19. MPC8250 ZU Package Pinout List (Continued)
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Pinout Table 19. MPC8250 ZU Package Pinout List (Continued)
Pin Name THERMAL14 I / O power Ball AG4 AG21, AG14, AG8, AJ1, AJ2, AH1, AH2, AG3, AF4, AE5, AC27, Y27, T27, P27, K26, G27, AE25, AF26, AG27, AH28, AH29, AJ28, AJ29, C7, C14, C16, C20, C23, E10, A28, A29, B28, B29, C27, D26, E25, H3, M4, T3, AA4, A1, A2, B1, B2, C3, D4, E5 U28, U29, K28, K29, A9, A19, B19, M1, M2, Y1, Y2, AC1, AC2, AH19, AJ19, AH10, AJ10, AJ5 AA5, AF21, AF14, AF8, AE7, AF11, AE17, AE23, AC26, AB25, Y26, V25, T26, R25, P26, M25, K27, H25, G26, D7, D10, D14, D16, D20, D23, C9, E11, E13, E15, E19, E22, B3, G5, H4, K5, M3, P5, T4, Y5, AA2, AC3
Core Power
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Ground
The default configuration of the CPM pins (PA0-31, PB4-31, PC0-31, PD4-31) is input. To prevent excessive DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs. 2 Must be pulled down or left floating. 3 If PCI is not desired, this pin should be pulled up or left floating. 4 For information on how to use this pin, refer to MPC8260 PowerQUICC II Thermal Resistor Guide (AN2271 / D) available at www.motorola.com / semiconductors.
Symbols used in Table 19 are described in Table 20.
Table 20. Symbol Legend
Symbol OVERBAR MII Meaning Signals with overbars, such as TA, are active low. Indicates that a signal is part of the media independent interface.
VR Package
The following figures and table represent the alternate 516 PBGA package. For information on the standard package for the MPC8250, refer to Section 1.4.1, "ZU Package" on page 28.
VR Pin Assignments
Figure 15 shows the pinout of the VR package as viewed from the top surface.
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Pinout
Not to Scale
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Figure 15. Pinout of the 516 PBGA Package (View from Top)
Figure 16 shows the side profile of the PBGA package to indicate the direction of the top surface view.
Transfer molding compound
Plated substrate via
Die attach
Wire bonds
Ball bond Screen-printed solder mask Cu substrate traces
1 mm pitch
BT resin glass epoxy
Figure 16. Side View of the PBGA Package
Table 21 shows the pinout list of the MPC8250VR. Table 20 defines conventions and acronyms used in Table 21.
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Pinout Table 21. MPC8250 VR Package Pinout List
Pin Name BR BG ABB / IRQ2 TS A0 A1 A2 A3 Ball C16 D2 C1 D1 D5 E8 C4 B4 A4 D7 D8 C6 B5 B6 C7 C8 A6 D9 F11 B7 B8 C9 A7 B9 E11 A8 D11 B10 C11 A9 B11 C12 D12 A10 B12
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A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30
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Pinout Table 21. MPC8250 VR Package Pinout List (Continued)
Pin Name A31 TT0 TT1 TT2 TT3 TT4 TBST TSIZ0 Ball B13 E7 B3 F8 A3 C3 F5 E3 E2 E1 E4 D3 C2 A14 C15 W4 Y1 V1 P4 N3 K5 J4 G1 AB1 U4 U2 N6 N1 L1 J5 G3 AA2 W1 T3 T1
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TSIZ1 TSIZ2 TSIZ3 AACK ARTRY DBG DBB / IRQ3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19
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Pinout Table 21. MPC8250 VR Package Pinout List (Continued)
Pin Name D20 D21 D22 D23 D24 D25 D26 D27 Ball M2 K2 J1 G4 U5 T5 P5 P3 M3 K3 H2 G5 AA1 V2 U1 P2 M4 K4 H3 F2 Y2 U3 T2 N2 M5 K1 H4 F1 W2 T4 R3 N4 M1 J2 H5
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D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54
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Pinout Table 21. MPC8250 VR Package Pinout List (Continued)
Pin Name D55 D56 D57 D58 D59 D60 D61 D62 Ball F3 V3 R5 R2 N5 L2 J3 H1 F4 AB3 W5 AC2 AA3 AD1 AC1 AB2 Y3 D15 Y4 D16 E15 D14 E14 A17 B14 F13 B17 AC6 AD6 AE6 AB7 AF7 AC7 AD7 AF8
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Pinout Table 21. MPC8250 VR Package Pinout List (Continued)
Pin Name CS8 CS9 CS10 / BCTL1 CS11 / AP0 BADDR27 BADDR28 ALE BCTL0 Ball AE8 AD8 AC8 AB8 C13 A12 D13 AF4 AA5 AE4 AD4 AF3 AB4 AE3 AF2 AD3 AE2 AD2 AE1 AC3 W6 AA4 AC9 AD9 AE9 AF9 AB6 AF5 AE5 AD5 AC5 AB5 AF6 AE13 AD15
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Pinout Table 21. MPC8250 VR Package Pinout List (Continued)
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Pinout Table 21. MPC8250 VR Package Pinout List (Continued)
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Pinout Table 21. MPC8250 VR Package Pinout List (Continued)
Pin Name PA0 / RESTART1 / DREQ3 PA1 / REJECT1 / DONE3 PA2 / CLK20 / DACK3 PA3 / CLK19 / DACK4 / L1RXD1A2 PA4 / REJECT2 / DONE4 PA5 / RESTART2 / DREQ4 PA6 PA7 / SMSYN2 Ball AC201 AC211 AF251 AE241 AA211 AD251 AC241 AA221 AA231 Y261 W221 W231 V261 V251 T221 T251 R241 P221 N261 N231 K261 L231 K231 H261 F251 D261 D251 C251 C221 B211 A201 A191 AD211 AD221 AC221
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Pinout Table 21. MPC8250 VR Package Pinout List (Continued)
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Pinout Table 21. MPC8250 VR Package Pinout List (Continued)
Pin Name PC10 / CD3 / RENA3 PC11 / CTS3 / CLSN3 / L1TXD3A2 PC12 / CD2 / RENA2 PC13 / CTS2 / CLSN2 PC14 / CD1 / RENA1 PC15 / CTS1 / CLSN1 / SMTXD2 PC16 / CLK16 / TIN4 PC17 / CLK15 / TIN3 / BRGO8 Ball V231 U231 T261 R261 P261 P241 M261 L261 M241 L221 K251 J251 G261 F261 G241 E251 G231 B231 E221 E211 D211 B201 AF231 AE231 AB211 AD231 AD261 Y221 AB241 Y231 AA261 W241 V221 U261 T231
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Pinout Table 21. MPC8250 VR Package Pinout List (Continued)
Pin Name PD17 / BRGO2 / SPIMOSI PD18 / SPICLK PD19 / SPISEL / BRGO1 PD20 / RTS4 / TENA4 / L1RSYNCA2 PD21 / TXD4 / L1RXD0A2 / L1RXDA2 PD22 / RXD4L1TXD0A2 / L1TXDA2 PD23 / RTS3 / TENA3 PD24 / TXD3 Ball R251 P231 N221 M251 L251 J261 K221 G251 H241 F241 H221 B221 D221 C211 E191 D19 K6 B18 K21 C14 AD24 B15 E17 C23 E6, F6, H6, L5, L6, P6, T6, U6, V5, Y5, AA6, AA8, AA10, AA11, AA14, AA16, AA17, AB19, AB20, W21, U21, T21, P21, N21, M22, J22, H21, F21, F19, F17, E16, F14, E13, E12, F10, E10, E9
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Package Description Table 21. MPC8250 VR Package Pinout List (Continued)
Pin Name Core Power Ball L3, V4, W3, AC11, AD11, AB15, U25, T24, J24, H25, F23, B19, D17, C17, D10, C10 A2, B1, B2, A5, C5, C18, D4, D6, G2, L4, P1, R1, R4, AC4, AE7, AC23, Y25, N24, J23, A23, D23, D20, E18, A13, A16, K10, K11, K12, K13, K14, K15, K16, K17, L10, L11, L12, L13, L14, L15, L16, L17, M10, M11, M12, M13, M14, M15, M16, M17, N10, N11, N12, N13, N14, N15, N16, N17, P10, P11, P12, P13, P14, P15, P16, P17, R10, R11, R12, R13, R14, R15, R16, R17, T10, T11, T12, T13, T14, T15, T16, T17, U10, U11, U12, U13, U14, U15, U16, U17
Ground
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The default configuration of the CPM pins (PA0-31, PB4-31, PC0-31, PD4-31) is input. To prevent excessive DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs. 2 Must be pulled down or left floating. 3 If PCI is not desired, must be pulled up or left floating. 4 For information on how to use this pin, refer to MPC8260 PowerQUICC II Thermal Resistor Guide (AN2271 / D).
Package Description
Package Parameters
Table 22. Package Parameters
The following sections provide the package parameters and mechanical dimensions.
Package parameters are provided in Table 22.
Package ZU VR
Devices MPC8250 MPC8250VR
Outline (mm) 37.5 x 37.5 27 x 27
Type TBGA PBGA
Interconnects 480 516
Pitch (mm) 1.27 1
Nominal Unmounted Height (mm) 1.55 2.25
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Package Description
Mechanical Dimensions
ZU Package Dimensions
Figure 17 provides the mechanical dimensions and bottom surface nomenclature of the 480 TBGA package.
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Notes: 1. Dimensions and Tolerancing per ASME Y14.5M-1994. 2. Dimensions in millimeters. 3. Dimension b is measured at the maximum solder ball diameter, parallel to primary data A. 4. Primary data A and the seating plane are defined by the spherical crowns of the solder balls. Millimeters Dim Min A A1 A2 A3 b D D1 e E E1 1.45 0.60 0.85 0.25 0.65 Max 1.65 0.70 0.95 - 0.85
37.50 BSC 35.56 REF 1.27 BSC 37.50 BSC 35.56 REF
Figure 17. Mechanical Dimensions and Bottom Surface Nomenclature-480 TBGA
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Package Description
VR Package Dimensions
Figure 18 provides the mechanical dimensions and bottom surface nomenclature of the 516 PBGA package.
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Figure 18. Mechanical Dimensions and Bottom Surface Nomenclature-516 PBGA
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Ordering Information
Figure 19 provides an example of the Motorola part numbering nomenclature for the MPC8250. In addition to the processor frequency, the part numbering scheme also consists of a part modifier that indicates any enhancement(s) in the part from the original production design. Each part number also contains a revision code that refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. For more information, contact your local Motorola sales office.
MPC 8250 A C ZU XXX X
Product Code Device Number Die Revision Level
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Figure 19. Motorola Part Number Key Table 23. Document Revision History
Addition of VR (516 PBGA) package information. Refer to sections 1.2.2, 1.4.2, and 1.5.
10 / 2002 Table 21, "VR Pinout": corrected ball assignment for the following pins-A12-A17, TA, PD5, PC2. 10 / 2002 Table 21, "VR Pinout": Addition of L3 to the Core (VDDx) pin list (page 53) 11 / 2002 Table 21, "VR Pinout": Addition of C18 to the Ground (GND) pin list (page 53)
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Ordering Information Table 23. Document Revision History (Continued)
Revision 0.9 Date 8 / 2003 · · · · · · · · · · · Substantive Changes Table 2: Modification to supply voltage ranges reflected in notes 2, 3, and 4 Addition of VCCSYN to "Note: Core, PLL, and I / O Supply Voltages" following Table 2 Addition of Figure 2 Addition of note 1 to Table 3 Table 4: Changes to JA. Addition of JB and JC Table 7, Figure 8: Addition of sp42a / sp43a Figure 3 through Figure 8: Addition of notes or modifications Table 9: Change to sp10 Table 14, Table 16, and Table 18: Removal of PLL bypass mode from clock tables Table 19 and Table 21: Addition of note 1 Addition of SPICLK to PC19 in Table 19 and Table 21. It is documented correctly in the MPC8260 PowerQUICC II Family Reference Manual but had previously been omitted from Table 19 and Table 21.
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Ordering Information
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Ordering Information
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HOW TO REACH US: USA / EUROPE / LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA / PACIFIC:
Information in this document is provided solely to enable system and software
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Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://www.motorola.com / semiconductors
MPC8250EC / D
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