4Bank 16bits Synchronous DRAM Revision First Version Release Chan

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4Bank 16bits Synchronous DRAM Revision First Version Release Chan

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64Mb Synchronous DRAM based 4Bank Document Title
4Bank 16bits Synchronous DRAM
Revision First Version Release Changed tOH: [tCK (CL3) Product] Changed Input High/Low Voltage (Page Changed characteristics (Page IDD2NS: 18mA 15mA IDD5:210 180mA 150mA [Speed 133MHz] Changed Clock High pulse width Time (Page Changed Time (Page11) Changed tRRD Time (Page12) Corrected Revision No.: Deleted Remark Revision History Corrected OPERATING CONDITION 50pF 30pF Changed OPERATING CONDITION VDDQ+2.0 VDDQ+0.3 VSSQ-2.0 -0.3 Modified note Super Power ORDERING INFORMATION Corrected ASSIGNMENT Corrected comments overshoot undershoot Nov. 2004 History Draft Date Remark
Dec. 2004
Dec. 2004
Jan. 2005 Jan. 2005 Feb. 2005
This document general product description subject change without notice. Hynix does assume responsibility circuits described. patent licenses implied. Rev. Feb. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P) Series
DESCRIPTION
Hynix HY57V641620E(L/S)T(P) series 67,108,864bit CMOS Synchronous DRAM, ideally suited memory applications which require wide data high bandwidth. HY57V641620E(L/S)T(P) organized 4banks 1,048,576x16. HY57V641620E(L/S)T(P) offering fully synchronous operation referenced positive edge clock. inputs outputs synchronized with rising edge clock input. data paths internally pipelined achieve very high bandwidth. input output voltage levels compatible with LVTTL. Programmable options include length pipeline (Read latency number consecutive read write cycles initiated single control command (Burst length 1,2,4,8 full page), burst count sequence(sequential interleave). burst read write cycles progress terminated burst terminate command interrupted replaced burst read write command cycle. (This pipelined design restricted '2N' rule)
FEATURES
Voltage: VDD, VDDQ 3.3V supply voltage device pins compatible with LVTTL interface TSOPII (Lead Lead Free Package) inputs outputs referenced positive edge system clock Data mask function UDQM, LDQM Internal four banks operation Burst Read Single Write operation Programmable Latency; Clocks Auto refresh self refresh 4096 Refresh cycles 64ms Programmable Burst Length Burst Type full page Sequential Burst Interleave Burst
ORDERING INFORMATION
Part HY57V641620E(L/S)T(P)-5 HY57V641620E(L/S)T(P)-6 HY57V641620E(L/S)T(P)-7 HY57V641620E(L/S)T(P)-H Clock Frequency 200MHz 166MHz 143MHz 133MHz 4Banks 1Mbits LVTTL TSOPII Organization Interface Package
Note: HY57V641620ET Series: Normal power, Leaded. HY57V641620ELT Series: power, Leaded. HY57V641620EST Series: Super power, Leaded. HY57V641620ETP Series: Normal power, Lead Free. HY57V641620ELTP Series: power, Lead Free. HY57V641620ESTP Series: Super Power, Lead Free
Rev. Feb. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P) Series
ASSIGNMENTS
VDDQ VSSQ VDDQ VSSQ LDQM /CAS /RAS A10/AP
DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 VDDQ UDQM
TSOPII 400mil 875mil 0.8mm pitch
Rev. Feb. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P) Series
DESCRIPTION
SYMBOL TYPE Clock DESCRIPTION system clock input. other inputs registered SDRAM rising edge Controls internal clock signal when deactivated, SDRAM will states among power down, suspend self refresh Enables disables inputs except CLK, CKE, UDQM LDQM Selects bank activated during activity Selects bank read/written during activity Address: RA11, Column Address: Auto-precharge flag: RAS, define operation Refer function truth table details Controls output buffers read mode masks input data write mode Multiplexed data input output Power supply internal circuits input buffers Power supply output buffers connection
BA0,
Clock Enable Chip Select Bank Address
Address Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input Output Power Supply Ground Data Output Power Ground Connection
RAS, CAS,
UDQM, LDQM DQ15 VDDQ VSSQ
Rev. Feb. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P) Series
FUNCTIONAL BLOCK DIAGRAM
1Mbit 4banks Synchronous DRAM
Self refresh logic timer
Internal Counter
State Machine Active
1Mx16 BANK
Decoder
1Mx16 BANK 1Mx16 BANK 1Mx16 BANK
Buffer Logic Sense Gate
X-Decoder X-Decoder X-Decoder X-Decoder
Refresh
Memory Cell Array
Column Active
U/LDQM
Column Decoder
DQ15
Y-Decoder
Bank Select
Column Counter
Address Buffers
Address Register
Burst Counter
Mode Register
Latency
Data Control
Pipe Line Control
Rev. Feb. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P) Series
BASIC FUNCTIONAL DESCRIPTION
Mode Register
Code Latency Burst Length
Code
Write Mode Burst Read Burst Write Burst Read Single Write
Burst Type
Burst Type Sequential Interleave
Latency
Latency Reserved Reserved Reserved Reserved Reserved
Burst Length
Burst Length Reserved Reserved Reserved Full Page A3=1 Reserved Reserved Reserved Reserved
Rev. Feb. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P) Series
ABSOLUTE MAXIMUM RATING
Parameter Ambient Temperature Storage Temperature Voltage relative Voltage relative Short Circuit Output Current Power Dissipation Soldering Temperature Time Symbol TSTG VIN, VOUT VDD, VDDQ TSOLDER Rating -1.0 -1.0
Unit
OPERATING CONDITION (TA= 70oC)
Parameter Power Supply Voltage Input High Voltage Input Voltage Symbol VDD, VDDQ -0.3 VDDQ Unit Note
Note: voltages referenced VIH(max) acceptable 5.6V pulse width with <=3ns duration. VIL(min) acceptable -2.0V pulse width with <=3ns duration.
OPERATING TEST CONDITION (TA= VDD=3.3±0.3V, VSS=0V)
Parameter Input High/Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise/Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance Access Time Measurement Note:
Vtt=1.4V
Symbol Vtrip Voutref
Value
Vtt=1.4V
Unit
Note
RT=500
RT=50
Output
Output
30pF
30pF
Output Load Circuit
Output Load Circuit
Rev. Feb. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P) Series
CAPACITANCE (TA= f=1MHz, VDD=3.3V)
Parameter Input capacitance A11, BA0, BA1, CKE, RAS, CAS, LDQM, UDQM DQ15 Symbol CI/O Unit
Data input output capacitance
CHARACTERRISTICS (TA= 70oC)
Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Voltage Symbol Unit Note -4mA +4mA
Note: 3.3V, other balls tested under DOUT disabled, VOUT=0
Rev. Feb. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P) Series
CHARACTERISTICS (TA= 70oC)
Parameter Symbol Test Condition Burst length=1, bank active tRC(min), IOL=0mA VIL(max), 15ns VIL(max), VIH(min), VIH(min), 15ns Input signals changed time during 2clks. other pins VDD-0.2V 0.2V VIH(min), Input signals stable. VIL(max), 15ns VIL(max), VIH(min), VIH(min), 15ns Input signals changed time during 2clks. other pins VDD-0.2V 0.2V VIH(min), Input signals stable. tCK(min), IOL=0mA banks active tRC(min), banks active Normal Self Refresh Current IDD6 0.2V power Super power Speed Unit Note
Operating Current
IDD1
Precharge Standby Cur- IDD2P rent IDD2PS Power Down Mode
Precharge Standby Cur- IDD2N rent Power Down Mode IDD2NS Active Standby Current Power Down Mode IDD3P IDD3PS
Active Standby Current Power Down Mode
IDD3N
IDD3NS Burst Mode Operating Current Auto Refresh Current IDD4 IDD5
Note: IDD1 IDD4 depend output loading cycle rates. Specified values measured with output open Min. tRRC (Refresh cycle time) shown CHARACTERISTICS HY57V641620ET(P) Series: Normal Power HY57V641620ELT(P) Series: Power HY57V641620EST(P) Series: Super Power
Rev. Feb. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P) Series
CHARACTERISTICS operating conditions unless otherwise noted)
Parameter Symbol tCK3 tCK2 tCHW tCLW tAC3 tAC2 tCKS tCKH 1.75 1.75 1000 1000 1000 1000 Unit Note
System Clock Cycle Time Clock High Pulse Width Clock Pulse Width Access Time From Clock Data-out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time Setup Time Hold Time Command Setup Time Command Hold Time
Data Output Low-Z Time tOLZ Data Output High-Z Time tOHZ3 tOHZ2
Note: Assume (input rise fall time) 1ns. 1ns, then [(tR+tF)/2-1]ns should added parameter. Access time measured with input signals 1V/ns edge rate, from 0.8V 0.2V. 1ns, then (tR/2-0.5)ns should added parameter.
Rev. Feb. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P) Series
CHARACTERISTICS operating conditions unless otherwise noted)
Parameter Cycle Time Cycle Time Delay Active Time Precharge Time Bank Active Delay Delay Operation Symbol 38.7 100K 100K tDPL 100K 120K Unit Note
Auto Refresh tRRC tRCD tRAS tRRD tCCD
Write Command Data-In DetWTL Data-in Precharge Command tDPL Data-In Active Command Data-Out Hi-Z Data-In Mask Command Precharge Data Output High-Z Power Down Exit Time Self Refresh Exit Time Refresh Time tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tDPE tSRE tREF
Note: command given tRRC after self refresh exit.
Rev. Feb. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P) Series
COMMAND TRUTH TABLE
Command Mode Register Operation Bank Active Read Read with charge Write Write with charge AutopreH AutopreH CKEn-1 CKEn ball High (Other balls code) Mode ADDR A10/AP code Note
Precharge Banks Precharge Bank Burst Stop Auto Refresh Burst-Read-SingleWRITE Entry Self Refresh1 Exit selected
Entry Precharge power down Exit
Clock Suspend
Entry Exit
Rev. Feb. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY57V641620E(L/S)T(P) Series
PACKAGE INFORMATION
400mil 54pin Thin Small Outline Package
UNIT mm(inch)
11.938(0.4700) 11.735(0.4620) 22.327(0.8790) 22.149(0.8720) 10.262(0.4040) 10.058(0.3960)
0.150(0.0059) 0.050(0.0020)
1.194(0.0470) 0.991(0.0390)
0.80(0.0315)BSC
0.400(0.016) 0.300(0.012)
5deg 0deg
0.597(0.0235) 0.406(0.0160)
0.210(0.0083) 0.120(0.0047)
Rev. Feb. 2005

4Bank 16bits Synchronous DRAM Revision First Version Release Chan

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