Literature Number: SSYZ015A Second Edition September 1999 MicroSt
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MicroStar BGAt Packaging Reference Guide
Literature Number: SSYZ015A Second Edition September 1999
MicroStar trademark Texas Instruments Incorporated.
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
Introduction
parallel pursuit cost reduction miniaturization recent years given rise increasing emphasis very small integrated circuit (IC) package solutions. This particularly evident consumer-based Figure Packaging Trends
Package trend (customer requirement) pitch (ball grid array) 1.27 ball pitch
equipment using digital signal processor (DSP) solutions such wireless telephones, laptop computers, hard-disk drives. Despite formal definition, packages with area similar size they encapsulate loosely referred chip scale packages (CSPs). Figure illustrates this trend.
Fine pitch requirement
pitch
Infra. issue (KGD) Soldering difficulties
(chip scale pkg.) solution Fine pitch (0.5, 0.8, ball pitch)
Bare chip (flip chip) QFP-0.5 QFP-0.4 Package size
PWB/ASSY cost
Bare chip (bump) count
Chip scale packages many ways ideal solution cost reduction miniaturization requirements. They offer enormous area reductions comparison quad flat packages (QFPs) have increasing potential without adding system-level cost. best case, CSPs compete today cost-per-terminal basis with QFPs. example, various CSPs from Texas Instruments (TIt) available cost parity with thin QFPs. Texas Instruments produces polyimide film-based family CSPs called MicroStar BGAt. Like most other CSPs, MicroStar BGAs solder alloy balls interconnect between package substrate board which package soldered. MicroStar family comes range solder ball pitch (0.5 mm). Currently, TI's most popular packages 144-ball packages. Figure shows structure TI's MicroStar package.
Figure Structure TI's MicroStar
Conforms JEDEC Outlines: MO-192 MO-205-A Encapsulant pitch Chip mils) Wire bond paste
pattern line/ space) Flex substrate (polyimide) (Single electrical layer)
(0.375 DIA.)
DIA./0.8 ball pitch Sn/Pb: near eutectic
MicroStar trademarks Texas Instruments Incorporated.
MicroStar Packaging Reference Guide
Texas Instruments addressed several issues package assembly order produce that only physically mechanically stable cost-effective wide variety applications. Figure demonstrates MicroStar BGAs resolve reliability cost issues. overall view flow used produce MicroStar packages shown Figure process solder ball attachment shown Figure Figure MicroStar Package Assembly Issues
Substrate selection Ceramic Glass-epoxy Polyimide
Figure MicroStar Package Assembly Flow
Same assembly
attach
Wire bond
Encap
Non-Ag paste
Short loop
X'fer mode
unique process
Ball attach
Transducer Solder wire Capillary Orifice
reflow
Flux wash
Interconnection
Bump (flip chip) Wire bond
Molten solder
0.30 DIA.
Ultrasonic clean
Solder ball form
Solder Stud bump Paste print Pick place Vacuum Laser symbol singulation Test
Printing mask Solder paste
Encapsulation
Potting Transfer mold
Tray These processes used
Figure Solder Ball Attachment
Solder ball attach Squeegee Printing mask Solder paste Pick place Vacuum
Substrate Ball pads (via) Solder paste print
Solder ball Solder ball attach DIA.)
Solder ball shear tests Fail Ave. Reading
144GGU, 0.8-mm pitch, DIA. ball spec.
Texas Instruments qualified many product lines using MicroStar packages, shipped more than million production units. This guide designed give technical background MicroStar packages well they used build advanced board layouts.
would like more information using reliable cost-effective MicroStar packaging your design, please contact your local field sales office.
MicroStar Packaging Reference Guide
Contents
Design Considerations Solder Land Areas Conductor Width/Spacing High-Density Routing Techniques Density Conventional Design Advanced Design Methods Reliability Daisy-Chained Units Reliability Data Reliability Calculations Package Characteristics Thermal Modeling Electrical Modeling Surface-Mounting MicroStar Packages Design Manufacturability (DFM) Solder Paste Solder Ball Collapse Reflow Inspection Packing Shipping Trays Tape-and-Reel Packing Method Tape Format Device Insertion Packaging Method Sockets Design Challenge Contacting Ball Establishing Contact Force Conclusions Future Work
References Appendix Frequently Asked Questions Package Questions Assembly Questions Appendix Package Data Sheets 80GJK (Pitch Size 167GJJ (Pitch Size 151GHZ (Pitch Size 100GGM (Pitch Size 64GGV (Pitch Size 80GGM (Pitch Size 100GGF (Pitch Size 100GGT (Pitch Size 144GGU (Pitch Size B-10 179GHH (Pitch Size B-11 176GGW (Pitch Size B-12 208GGW (Pitch Size B-13 240GGW (Pitch Size B-14 196GHC (Pitch Size B-15 257GHK (Pitch Size B-16 257GJG (Pitch Size B-17
MicroStar Packaging Reference Guide
List Figures
Figure Page Packaging Trends Structure TI's MicroStar MicroStar Package Assembly Issues MicroStar Package Assembly Flow Solder Ball Attachment Package Board Land Area Configuration Effects Via-to-Land Ratios Optimum Land Configurations Design Considerations (Conventional) Microvia Structure "Dog Bone Via" Structure Buried Vias Daisy-Chained Pinout List General List Layout Daisy-Chained Unit Daisy-Chain Test Configuration Board-Level Reliability Test Boards Board-Level Reliability Test Data Thermal Modeling Process Electrical Modeling Process Solder Ball Collapse Ideal Reflow Profile Shipping Tray Detail Packing Method Trays Single Sprocket Tape Dimensions Reel Dimensions Tape-and-Reel Packing Approaches Contacting Solder Ball Pinch Contact Solder Balls Contact Area Solder Ball Witness Marks Solder Ball Effect Burn-in Probe Marks TI's Strategic Package Line-Up
List Tables
Table
Page Package-Level Reliability Tests Package-Level Reliability Test Results Board-Level Reliability Summary Summary Significant Improvements Effects Size Board Thickness Fatigue Life Number Units Shipping Tray Tape Dimensions Reel Dimensions
MicroStar Packaging Reference Guide
Design Considerations
MicroStar Packaging Reference Guide
Design Considerations
Solder Land Areas
Design Considerations
Design both MicroStar itself printed circuit board (PCB) important achieving good manufacturability optimum reliability. particular, diameters package vias board lands critical. While actual sizes these dimensions important, their ratio more critical. Figure illustrates package via-to-PCB configuration Figure illustrates this ratio critical. Figure Package Board Land Area Configuration
MicroStar package
Solder lands generally simple round pads. Solder lands either solder-mask-defined non-solder-mask-defined. Figure Optimum Land Configurations
Solder-mask-defined Land
Ball Pitch 1.00
DIA. DIA. development) 0.38 0.48 0.45 0.55
Non-solder-mask-defined Land
Ball Pitch
DIA. DIA. development) 0.35 0.50 0.55
Land
Package ball
(Not scale) diameter package Land diameter Ratio should equal optimum reliability.
Figure Effects Via-to-Land Ratios
Solder-mask-defined (SMD) land. With this method, copper made larger than desired land area, opening size defined opening solder mask material. advantages normally associated with this technique include more closely controlled size better copper adhesion laminate. Better size control result photoimaging stencils masks. chief disadvantage this method that larger copper spot make routing more difficult. Non-solder-mask-defined (NSMD) land. Here, land area etched inside solder mask area. While size control dependent copper etching accurate solder mask method, overall pattern registration dependent copper artwork, which quite accurate. tradeoff between accurate placement accurate size. Figure example optimum land diameters configurations common MicroStar pitch.
Package
Package
Package
Conductor Width/Spacing
Many today's circuit board layouts based most 100-µm conductor line width 200-µm spacing. route between 0.8-mm-pitch balls, given clearance roughly between ball lands, only signal routed between ball pads. 380-µm ball spacing worst case calculated assuming diameter solder ball land Figure presents some design considerations based commonly used design rules. Conventionally, pads connected wide copper traces other devices plated through holes (PTH). rule, mounting pads must isolated from PTH. Placing interstitially land pads often achieves this.
MicroStar Packaging Reference Guide
view Figure package larger than via, solder ball prone crack prematurely interface. middle view, larger than package via, which leads cracks package surface. bottom view, where ratio almost 1:1, stresses equalized neither site more susceptible cracking than other.
Design Considerations
Figure Design Considerations (Conventional)
(Not scale) pitch pitch
Design Considerations
0.125 line
0.50 DIA. solder mask opening
0.125 line
0.55 DIA. solder mask opening
0.350 DIA. NSMD pads
0.254 DIA. hole
0.400 DIA. NSMD pads
0.254 DIA. hole
0.100 line
0.125 line
0.375 DIA. solder mask opening
0.450 DIA. solder mask opening
0.480 DIA. pads
0.550 DIA. pads
High-Density Routing Techniques
challenge when designing with packages that available space contracts, space available signal fanout also decreases. using high-density routing techniques, designer minimize many these design manufacturing challenges. This section focuses designators (144-pin) (176-pin) packages. Both packages have 0.8-mm pitch, each distinctly different array style. ball array wide channels four corners, providing inner balls with space routing connectivity. Mechanical drawings these MicroStar packages found Appendix package solid four-row array configuration which cause difficulties when routing inner rows two-layer boards.
Figure
Microvia Structure
Density
density, mentioned earlier, limiting factor when designing high-density boards. density defined number vias particular board area. Using smaller vias increases routability board requiring less board space increasing density. invention microvia, shown Figure solved many problems associated with density.
MicroStar Packaging Reference Guide
Microvias often created using laser penetrate first layers dielectric. laser penetrate 4-mil-thick dielectric layer, creating 4-µm microvia shown Figure layout designer route first internal board layer. layers (each mils thick) laser-drilled, creating 200-µm microvia diameter. this case, routing first internal layers possible. number board layers increases board chip density functional count increase. example, TMS320VC549GGU digital signal processor (DSP) 144-GGU package uses balls power ground. Routing roughly
Design Considerations
Design Considerations
signals accomplished three layers. power ground planes increase board five layers. sixth layer used bottom side place discrete components. Furthermore, increasing board layer stack-up eight layers, high-density applications possible with only mils between chips.
Advanced Design Methods
Another option combination blind buried vias. Blind vias connect either bottom side board inner layers. Buried vias usually connect only inner layers. Figure illustrates this method using 4-mil laser-drilled microvias center pads burying bone layer Since buried does extend through underside board, designer another laser-drilled blind microvias, needed, connect bypass capacitors other discrete components bottom side. More information these advanced techniques available contacting your local field sales office. Figure Buried Vias
Conventional Design
relatively large density package periphery, mentioned earlier, caused limited options when routing signal from ball. reduce eliminate density problem periphery package, designers build vertically from through internal layers board, shown Figure working vertically mechanical drilling 250-µm vias between pads board internal layers, designers create "pick-and-choose" method. They pick layer choose route. "dog bone" method used connect through-hole pad. This method requires very small mechanical drill create necessary number vias package. Although this method least expensive, disadvantage that vias through board, creating matrix vias bottom side board. Figure "Dog Bone Via" Structure
side view Cross-sectional view
Solder wicks into blind filling void
Layer Layer Layer Layer Layer Layer
Micro blind vias
Layer Layer Layer Layer Layer Layer
10-mil through-hole buried
4-mil laser-drilled microvia required connect discretes bottom side board
MicroStar Packaging Reference Guide
Reliability
MicroStar Packaging Reference Guide
Reliability
Reliability
Daisy-Chained Units
Daisy-chained units used gain experience handling mounting CSPs, board-reliability testing, check electrical layouts, confirm accuracy mounting equipment. facilitate this, Texas Instruments offers daisy-chained units production MicroStar packages. Each daisy-chained pinout differs slightly depending package layout. example shown Figure Daisy-chained packages wired provide continuous path through package easy testing. issues list each package, which correlates each ball position with corresponding wire number. daisy-chained list special case general list shown Figure Package lists daisy-chained lists production packages included Appendix layout 144-GGU daisy-chained package shown Figure When daisy-chained package assembled PCB, complete circuit formed, which allows continuity testing. circuit includes solder balls, metal pattern die, bond wires, traces. entire package only quadrant interconnected tested. diagram test configuration shown Figure
Reliability Data
Reliability first questions designers about packaging technology. They want know well package will survive handling assembly operation, long will last board. elements package reliability system reliability, while related, focus different material properties characteristics tested different methods. Figure General List
100GGT View
Reliability
Index mark
PIN#
BALL#
PIN#
BALL#
PIN#
BALL#
PIN#
BALL#
Figure
Daisy-Chained Pinout List
100GGT View
Index mark
Figure
Layout Daisy-Chained Unit
H11,
MicroStar Packaging Reference Guide
Reliability
Figure
Wire bonds Solder balls
Daisy-Chain Test Configuration
MicroStar Tester
reliability, thermal cycling tests generally used predict behavior reliability. Many these used conjunction with solder fatigue life models using modified Coffin-Manson strain range-fatigue life plots. Table Package-Level Reliability Tests
Test Environments HAST Conditions 85RH/85°C Read Points hrs. 1000 hrs. hrs. hrs. Reliability cycles cycles 1000 cycles cycles cycles cycles 1000 cycles hrs. hrs. 1000 hrs. hrs. hrs. hrs. 1000 hrs. hrs. hrs.
Copper traces
Test pads
Package reliability focuses materials construction, thermal flows, material adherence/delamination issues, resistance high temperatures, moisture resistance ball/stitch bond reliability. Thorough engineering package performed prevent delamination caused interaction substrate material mold compound. subjects each MicroStar rigorous qualification testing before package released production. These tests summarized Table samples used these tests preconditioned according Joint Electronic Device Committee (JEDEC) A113 various levels. Typical data presented Table MicroStar packages have proven robust reliable. Board-level reliability (BLR) issues generally focus complex interaction various materials under influence heat generated operation electronic devices. only there complex thermal situation caused multiple heat sources, there cyclical strains expansion mismatches, warping transient conditions, non-linear material properties, solder fatigue behavior influenced geometry, metallurgy, stress relaxation phenomenon, cycle conditions. addition material issues, board package design influence reliability. Thermal management from system level critical optimum Table Package-Level Reliability Test Results
Autoclave
121°C, psig
Temp. Cycle
-55/125°C -65/150°C
Thermal Shock
-65/150°C -55/125°C
HTOL
125°C, voltage
HTOL HTOL Bake
140°C, voltage 155°C, voltage 150°C 170°C
HAST
130°C
samples used these tests preconditioned according Joint Electronic Device Committee (JEDEC) A113 various levels. Optional tests. more them added meet customer requirements.
Package Types Leads Body (mm) Device (mm) Level Test Environment Autoclave T/C, -55/125°C T/S, -65/150°C (240 hrs.) (1000 cycles) (500 cycles) (750 cycles) (1000 cycles) (1000 hrs.) (1250 hrs.) (600 hrs.) (1000 hrs.) (1000 hrs.) 0/70 0/116 0/78 0/78 0/78 0/77 0/116 0/77 0/77 0/78 0/115 0/43 0/78 0/116 0/77 0/77 0/77 0/77
Failures/Sample Size 0/77 0/77 0/77 0/77 0/77 0/76
HAST, 85°C/85%RH 150°C Storage
HTOL
MicroStar Packaging Reference Guide
Reliability
addition device/package testing, board-level reliability testing been extensively performed MicroStar packages. Various types daisy-chained packages were assembled special boards shown Figure Electrical measurements
were made initial state then intervals after temperature cycles were run. overall test conditions shown Figure summary wide range board-level reliability shown Table This data includes testing manufacturers. Table summarizes conclusions from testing. important conclusions that size needs match size, that solder paste needed attachment give optimal reliability.
Figure
Board-Level Reliability Test Boards
Board Material FR-4 Structure: external metal layers Traces: design rule mils) width, mils) space Paste: Eutectic (SENJU 63-330F-21-10.5) Paste thickness: 0.15 Board thickness: mils Reflow profile: 225°C max, time above 200°C sec, time above 150°C Screen opening: match land diameter Precondition: Level
Reliability Calculations
Another important aspect predicting package will perform given application reliability modeling. Thermal, electrical, thermomechanical modeling, verified experimental results, provide insight into system behavior, shorten package Figure Board-Level Reliability Test Data
Reliability
TI-Houston test board
Test condition: Open short @25°C, resistance change Sample size: Greater equal Temperature cycle range: -40°C 125°C Sampling rate: Every cycles, first failure; every cycles thereafter 1000 cycles; every cycles between 1000 1500 cycles; every cycles between 1500 2500 cycles; Test stopping point (2500 cycles, failures)
Ramp time: min-5 Dwell time: min-13
TI-HIJI test board
Table Board-Level Reliability Summary
Failures/Sample Size Conditions (With Solder Paste) Site Test Site HIJI HIJI Philippines HIJI HIJI HIJI TIPI Philippines Customer HIJI Customer HIJI Customer Body (mm) Pitch (mm) (mm) Temp. Cycle (°C) -40/125 0/85 Requirements 1000 (Cycles) 0/85 0/85 1100 4/85 Extended Range 1200 1300 (Cycles) 5/77 5/72 1500 15/39
Package balls balls balls balls balls balls balls
-40/125
0/36
0/36
0/36
0/36
0/36
0/36
1/35
-25/125
0/32
0/32
0/32
0/32
0/32
0/16
6/16
-40/125
0/62
0/62
0/62
0/62
0/62
0/62
4/62
-40/100
0/180
0/180
0/180
0/180
-25/125
0/35
0/35
0/35
0/35
0/35
0/35
1/35
-40/125
0/12
0/12
0/12
0/10
MicroStar Packaging Reference Guide
Reliability
Table Summary Significant Improvements
Condition size edge Ball count Ball size size Solder paste Larger Over balls Smaller Smaller Over/undersized None insufficient Improved Smaller Within ball matrix Larger Larger Matches package (for NSMD ~90% via) Thickness 0.15 nom. (type matches reflow)
combination Finite Element Analysis (FEA), accurate thermal property information, advanced statistical methods allows prediction number cycles failure various probability levels. Using assumption that cyclic fatigue lifetime follows Weibull distribution, various probability levels calculated. these calculations, Weibull shape parameter used which based experimental data calibration. also consistent with available experimental data found literature leadless packages. This then results following equation: Nf(x%) Nf(50%)[ln(1-0.01x)/ln(0.5)]1/ Using this equation, using plastic strain combination with curves, data below example accuracy possible with this method: Sample Finite Element Simulation Life Prediction: T/C: -40/125°C {Model} 0.353% outmost joint Nf(50%)= 4434 cycles Nf(1%) 1539 cycles {BLR Testing} -40/125°C min/10 min) Nf(1%) 1657 cycles Modeling most useful exploring changes materials, designs process parameters without need build experimental units. example, modeling used study effects changes board thickness size. Table shows simulated effects size board thickness fatigue life 144-GGU package.
Reliability
development time, predict system lifetimes, provide important analytical tool. applications such BGAs, where interconnections made through solder balls, useful life package most cases, dependent useful life solder itself. This area that been studied extensively, very accurate models predicting both solder behavior interpreting accelerated life testing exist. current methodology employed Texas Instruments includes both extensive model refinement constant experimental verification. given package, detailed Finite Element Model (FEM) constructed. This model will used carry plain strain elastoplastic analysis predict areas high stress. These models also account thermal variation material properties, such Modulus Elasticity, Coefficient Thermal Expansion, Poisson's Ratio function temperature. These allow calculate thermomechanical plastic strains solder joints given thermal loading.
Table Effects Size Board Thickness Fatigue Life
Example1: Effects size fatigue life
Package: Die: 0.279 Board: FR-4 board mils thick
Dia. (mils)
Standoff (mm) 0.3847 0.3689 0.3523 0.3350
Solder Center Dia. (mm) 0.4908 0.4951 0.5005 0.5060 (1%) (cycles failure) 1152 1249
Plastic Strain 0.4400 0.4127 0.3908 0.3741
(1%) (cycles failure) 1134 1263 1377
Difference 0.88x 1.11x 1.21x
Example Effects board thickness fatigue life
Package: Die: 0.279 Board: FR-4 Size: mils
Board Thickness (mils)
Plastic Strain 0.4095 0.393
Difference 1.08x
MicroStar Packaging Reference Guide
Reliability
Package Characteristics
Texas Instruments extensive package characterization capabilities, including electrical measurements with TDR/LRC (Time Domain Reflectometer/inductance resistance capacitance) network analysis capabilities, thermal measurements with JEDEC standard test conditions 1000 watts, extensive electrical, thermal, mechanical modeling capability. Modeling implemented starting 1984. Stress analysis done with Ansys Analysis tool, which provides full linear, nonlinear, capabilities solder reliability, package warpage, stress analysis studies. internally developed tool (PACEDt) used electrical modeling that gives 2.5D full capability models, transmission lines, lossy dielectrics, SPICE deck outputs. thermal modeling tool also internally developed (ThermCALt) provides full automatic mesh generation most packages. Figure Thermal Modeling Process
Heat-Transfer Paths
Complex geometries, transient analysis, anisotropic materials modeled with With these capabilities, full range modeling from device level through system level provided. Package modeling used predict package performance design stage, provide package development tool, qualification similarity, used failure analysis tool.
Thermal Modeling
Figure outlines thermal modeling process. Data each package included Appendix
Reliability
Electrical Modeling
Figure outlines electrical modeling process. Data each package included Appendix Figure Electrical Modeling Process
Chip Package Conduction Convection Radiation Calculates inductances, capacitances, resistances, transmission line characteristics package geometries Uses loads circuit simulation Process Select solution algroithms problem domain Identify package structures modeled Generate spice deck package parameters Simulate impact driver output waveforms Calculate ground/power bounce
(TQFP shown illustration purposes) Model's three heat-transfer mechanisms: Conduction Convection Radiation Method: Define solid Mesh solid Solve large number simultaneous equations relating each defined mesh point each other Sources error: Convection coefficients Material properties Solid definition inaccuracies
Voltage Input Output pin1 Crosstalk 2.00E-09 4.00E-09
Time (sec)
PACED ThermCAL trademarks Texas Instruments Incorporated.
MicroStar Packaging Reference Guide
Surface-Mounting MicroStar Packages
MicroStar Packaging Reference Guide
Surface-Mounting MicroStar Packages
Surface-Mounting MicroStar Packages
Surface-mount technology (SMT) evolved over past decade from into science with development design guidelines rules. While these guidelines specific enough incorporate many shared conclusions, they general enough allow flexibility board layouts, solder pastes, stencils, fixturing, reflow profiles. From experience, most assembly operations have found MicroStar packages robust, manufacturing-friendly packages that easily within existing processes profiles. addition, they require special handling. However, ball pitch becomes smaller, layout methodology placement accuracy become more critical. Below review more important aspects surface-mounted CSPs. suggestions provided efficient, cost-effective production.
edges boards used conveyer transfer, cleared zone least 3.17 should allowed. Normally, longest edges board used this purpose, actual width dependent equipment capability. While component lands fiducials this area, breakaway tabs Interpackage spacing aspect DFM, question close safely components each other critical one. following component layout considerations recommendations based experience:
There should minimum 0.508 between land areas adjacent components reduce risk shorting. recommended minimum spacing between discrete component bodies equal height tallest component. This allows soldering angle case manual work needed. Polarization symbols need provided discrete SMDs (diodes, capacitors, etc.) next positive pin. Pin-1 indicators features needed determine keying components. Space between lands (under components) backside discrete components should minimum 0.33 open vias this space. direction backside discretes wave solder should perpendicular direction through wave. components bottom side that exceed grams square inch contact area with board. space permits, symbolize reference designators within land pattern respective components. preferable have components oriented well-ordered columns rows. Group similar components together whenever possible. Room testing needs allowed.
Design Manufacturability (DFM)
Surface-Mounting MicroStar Packages
well-designed board that follows basic surface-mount technology considerations greatly improves cost, cycle time, quality product. Board design should comprehend SMT-automated equipment used assembly, including minimum maximum dimensional limits placement accuracy. Many board shapes accommodated, front board should have straight square edge help machine sensors detect While odd-shaped small boards assembled, they require panelization special tooling process in-line. more irregular board-non-rectangular with cutouts-the more expensive assembly cost. Fiducials (the optical alignment targets that align module automated equipment) should allow vision-assisted equipment accommodate shrink stretch board during processing. They also define coordinate system automated equipment, such printing pick-and-place. following guidelines helpful:
Automated equipment requires minimum preferably three fiducials. wide range fiducial shapes sizes used. Among most useful circle diameter with annulus 3.175/3.71 outer ring optional, other feature within 0.76 fiducial. most useful placement fiducials configuration, which orthogonal optimize stretch/shrink algorithms. When possible, lower left fiducial should design origin (coordinate 0,0). components should within 101.6 fiducial guarantee placement accuracy. large boards panels, fourth fiducial should added.
Solder Paste
recommends paste when mounting MicroStar BGAs. paste offers following advantages:
acts flux wetting solder ball land. adhesive properties paste will hold component place during reflow.
MicroStar Packaging Reference Guide
Surface-Mounting MicroStar Packages
helps compensate minor variations planarity solder balls. Paste contributes final volume solder joint, thus allows this volume varied give optimum joint.
Figure
Solder Ball Collapse
0.40 0.05 Land
Paste selection normally driven overall system assembly requirements. general, clean" compositions preferred difficulty cleaning under mounted component. Most assembly operations have found that changes existing pastes required addition MicroStar BGA, large variety board designs tolerances, possible this will true specific application. Nearly critical paste selection stencil design. proactive approach stencil design large dividends assembly yields lower costs. general, MicroStar packages special cases packages, general design guidelines package assembly applies them well. There some excellent papers assembly, only brief overview issues especially important MicroStar packages will presented here. typical stencil hole diameter should same size land area, 125- 150-µm-thick stencils have been found give best results. Good release consistent amount solder paste shapes critical, especially ball pitches decrease. metal squeegee blades, very least, high durometer polyblades, important achieving this. Paste viscosity consistency during screening some variables that require close control.
0.35 typical
(Not scale)
Controlling collapse, thus defining package standoff, critical obtaining optimum joint reliability. Generally, larger standoff gives better solder joint fatigue strength, this should achieved reducing board land diameter. Reducing land diameter will increase standoff, will also reduce minimum cross-section area joint. This, turn, will increase maximum shear force side solder joint. Thus, reduction land diameter will normally result worse fatigue life, should avoided unless consequences well understood.
Reflow
Solder reflow conditions next critical step mounting process. During reflow, solvent solder paste evaporates, flux cleans metal surfaces, solder particles melt, wetting surfaces takes place wicking molten solder, solder balls collapse, finally solidification solder into strong metallurgical bond completes process. desired result uniform solder structure strongly bonded both package with small voids smooth, even fillet both ends. Conversely, when steps carefully together, voids, gaps, uneven joint thickness, discontinuities, insufficient fillet occur. While exact cycle used depends reflow system paste composition, there several points successful cycles have common. first these warm-up period sufficient safely evaporate solvent. This done with pre-heat bake, more commonly, hold cycle evaporation temperatures. there less solvent paste (such high-viscosity, high-metal-content paste), then hold shorter. However, when hold long enough solvent fast allow evaporate, many negative things happen. These range from solder-particle splatter
Solder Ball Collapse
order produce optimum solder joint, important understand amount collapse solder balls, overall shape joint. These function
diameter package solder ball via. volume type paste screened onto PCB. diameter land. board assembly reflow conditions. weight package.
original ball height package typical 0.8-mm-pitch package 0.40 After package mounted, this typically drops 0.35 illustrated Figure
MicroStar Packaging Reference Guide
Surface-Mounting MicroStar Packages
Surface-Mounting MicroStar Packages
trapped gases, which cause voids embrittlement. significant number reliability problems with solder joints solved with warm-up step, needs careful attention. second point that successful reflow cycles have common uniform heating across package board. Uneven solder thickness non-uniform solder joints indicator that profile needs adjustment. There also problem when different sized components reflowed same time. Care needs taken when profiling oven sure that indicated temperatures representative what most difficult reflow parts seeing. These problems more pronounced with some reflow methods, such infrared (IR) reflow, than with others, such forced hot-air convection. Finally, successful reflow cycles strike balance among temperature, timing, length cycle. Mistiming lead excessive fluxing activation, oxidation, excessive voiding, even damage package. Heating paste fast before melts also paste, which leads poor wetting. Process development needed optimize reflow profiles each solder paste/flux combination. profile shown Figure ideal forced-air-convection furnace, which most highly recommended type. best results have been found nitrogen atmosphere. guidelines upon which this profile based, also shown Figure general. Modification ideal reflow profile will driven interplay solder-paste particle size flux percentage with process variables such heating rates, peak temperatures, board construction factors atmosphere. These modifications dependent upon specific applications. should noted that while they more rugged than most CSP-type packages, many MicroStar packages still slightly moisture-sensitive time printing this Reference Guide. time environment should controlled according label packing material. This will prevent moisture absorption problems with package such "popcorning," delamination.
Surface-Mounting MicroStar Packages
Figure
Ideal Reflow Profile
60-90 60-120 60-150 220°C 10-20 6°C/sec maximum
140°C: 140°C 180°C: Time above 183°C: Peak temperature: Time within peak temperature: Ramp-down rate:
Ideal Reflow Profile Temperature (°C) Time (sec) Note: This ideal profile, actual conditions obtained specific reflow oven will vary. This profile based convection plus forced convection heating.
Other concerns with packages those caused bowing twisting during reflow. PCBs thinner, these problems will become more significant. Potential problems from these effects will show open pins, hourglass solder joints, solder discontinuities. Proper support through furnace, balancing attachments panel, and, worst cases, using weight stiffen help prevent this. general, small size CSPs create fewer problems than standard BGAs. also true that BGAs generally have fewer problems than leaded components.
Inspection
MicroStar packages have been designed consistent with very high-yield assembly processes. Because their relatively light weight, MicroStar packages tend self-align during reflow. Since pitch ball pattern large compared that fine-pitch leaded packages, solder bridging rarely encountered. recommended that high-quality solder joint assembly process developed using various inspection analytical techniques, such cross-sectioning. Once quality process been developed, detailed inspection should necessary. Visual methods, while obviously limited, offer valuable clues general stability process. Electrical checks confirm interconnection. Both transmission X-rays laminographic X-rays have proven useful nondestructive tools, desired.
MicroStar Packaging Reference Guide
Packing Shipping
Packing Shipping
MicroStar Packaging Reference Guide
Packing Shipping
MicroStar BGAs shipped either packing methods: Trays Tape reel
with same package outline individually designed tray. trays designed used with pick-and-place machines. Figure gives typical tray details, Table shows number units tray. Figure shows packing method used ship trays. Before trays sealed aluminum-lined plastic bag, they baked accordance with requirements dry-packing appropriate level.
Trays
Thermally resistant plastic trays currently used ship majority packages. Each family parts
Figure
Shipping Tray Detail
Packing Shipping
Table Number Units Shipping Tray
Body Size (mm) Units/ Tray Units/ 1000 1125
Package Code GZY, GGW,GHC GHG, GHJ, GZG, GGF, GHZ, GGV, GFZ, GHB,
Matrix
MicroStar Packaging Reference Guide
Packing Shipping
Figure
Packing Method Trays
Wrap tape bubble pack around snug inner carton. Place necessary labels inner carton.
Arrange stack trays packed with tray bottom.
Tray
Tray stack
label
Tray
Bar-code label bubble pack around inner carton snug skidboard liner. Strap tray stack pads together with four straps-three crosswise lengthwise. Then place desiccants humidity indicator top.
Humidity indicator Packing Shipping Place four foam corner spacers folded skidboard liner before placing outer carton. enhanced skidboard liner, which eliminates need foam corner spacers, used. Seal outer carton apply necessary labels. Aluminum-lined label Moisture-sensitivity label Bar-code label
Desiccant packs
Place inside aluminum-lined vacuum-seal Place necessary labels sealed bag.
MicroStar Packaging Reference Guide
Packing Shipping
Tape-and-Reel Packing Method
embossed tape-and-reel method generally preferred automatic pick-and-place machines. This will standard MicroStar packages will shipped. Trays will remain option those customers prefer them. tape made from antistatic/conductive material. cover tape, which peels back during use, heat-sealed carrier tape keep devices their cavities during shipping handling. tape-and-reel packaging used Texas Instruments full compliance with Standard 481-A, "Taping Surface-Mount Components Automatic Placement." static-inhibiting materials used carrier-tape manufacturing provides device
protection from static damage, while rigid, dust-free polystyrene reels provide mechanical protection clean-room compatibility with dereeling equipment currently available most high-speed automated placement systems.
Tape Format
Typical tape format shown Figure variables used Figure Table defined follows: tape width; pocket pitch; pocket width; pocket length; pocket depth; maximum tape depth; distance between drive hole centerline pocket.
Figure
Single Sprocket Tape Dimensions
0.10 2.00 0.05 0.40
1.75
Packing Shipping
Carrier tape embossment Diameter
Direction feed Notes:
Cover tape
Tape widths Camber Standard 481-A Minimum bending radius Standard 481-A linear dimensions millimeters.
Table Tape Dimensions
Tape Width Pocket Pitch Pocket Width (A0) 10.2 11.35 12.4 15.25 Pocket Length (B0) 10.2 11.35 12.4 15.25 Pocket Depth (K0) Max. Tape Depth Centerline Drive Hole 11.5 11.5 11.5 11.5 Package Size
dimensions millimeters.
MicroStar Packaging Reference Guide
Packing Shipping
Figure
Reel Dimensions
diameter reel hub.
13.0
20.2
code label
width Note linear dimensions millimeters.
Table Reel Dimensions
Tape Width Reel Diameter Reel Total Thickness MAX) Parts Reel 1000 1000
Device Insertion
Devices inserted toward outer periphery tape placing side with device name face side with balls attached face down. pin-1 indicator placed right-hand corner pocket, next sprocket holes.
dimensions millimeters.
reels shown Figure this figure, width tape, diameter hub, total reel thickness. After parts loaded into reel, each individual reel packed "pizza" shipping, shown Figure Figure Tape-and-Reel Packing
Packaging Method
reels, once taping been completed, leader fixed onto reel with tape. product name, number, quantity, date code recorded reel cardboard used tape delivery. Each reel separately packed cardboard delivery. Trays packed with five loaded trays empty tray support keep packages secure. stack secured with stable plastic straps sealed moisture-proof bag. Customer-specific code labels added under request general purchasing specification. Moisture-sensitive packages baked before packing packed within hours coming oven. Both tape-and-reel tray moisture-proof bags sealed marked with appropriate labeling warning that packages inside bags dry-packed giving level moisture sensitivity.
Desiccant Humidity indicator Reeled units Aluminum
Pizza
code label
MicroStar Packaging Reference Guide
Packing Shipping
Packing Shipping
Packing Shipping
MicroStar Packaging Reference Guide
Sockets
MicroStar Packaging Reference Guide
Sockets
Sockets
Design Challenge
fine pitch MicroStar packages makes socketing special challenge. Mechanical, thermal, electrical issues must accommodated socket designer. packaging cutting edge package design appears that being adopted faster than other previous package technology. Standards only beginning established. fully supports these efforts, MicroStar outlines being engineered within JEDEC standards where they exist. instance, 0.8-mm-pitch packages within JEDEC MO205. While these standards detail pitch placement, they allow wide latitude overall body size variation. size specific package within MicroStar family based package construction, independent size. Thus, range sizes I/Os within family will have same package dimensions. Each different family specific pitch array. maximum socket versatility, adapter "personalizer" customized each application, allowing single-socket body used with many packages. This feature especially useful early days technology being developed adopted total volume required small.
Figure
Approaches Contacting Solder Ball
Metal
Metal pinch
Rough bump flex
Conductive
Etched pocket silicon
Metal
Contacting Ball
number different approaches contacting solder ball shown schematically Figure pinch style contact been used extensively contacting solder balls conventional BGAs. benefit pinch style that socket does have push down package provide necessary contact force penetrate oxide film solder balls. issues utilizing this approach pitches below 1.27 involve: Miniaturizing contact Developing injection-molding tooling pitch Developing cost-effective manufacturing procedures handling assembling fragile contact pitches 0.75 above, Texas Instruments designed pinch contact that satisfies these requirements. Further information availability these sockets obtained from your local Field Sales representative. contact designed grip solder ball with pinching action. This only provides electrical contact solder ball also helps retain package socket. contact shown Figure contact stamped formed from 0.12-mm-thick strip 172, high-yield-strength beryllium copper alloy. This alloy used spring applications that exposed high stresses temperatures because excellent stress relaxation performance formability.
Sockets
Figure
Pinch Contact Solder Balls
Each contact incorporates beams that provide oxide-piercing interface with sides balls above central area-the equator. Since contact above equator, resultant force downward ensures package retention socket. contact made
MicroStar Packaging Reference Guide
Sockets
bottom solder ball original package planarity specifications unchanged. photomicrograph contact touching solder balls shown Figure Figure Contact Area Solder Ball
Figure
Effect Burn-in Probe Marks
Establishing Contact Force
Contact force typically generated result deflection contact arm. actual force generated function modulus material specific geometric details design. solder ball diameters CSPs tend small-in range 0.25 which limits deflection contact very small distance. Typically, this distance half ball diameter. This presents challenge designer must generate required grams force contact tip, keep bending stresses within contact arms enough value achieve 20K-cycle life. contact force requirements incorporating pre-load, that even small displacements, desired force achieved socket operate within acceptable stress levels. 15-gram target force smaller than that associated with TSOP-type contact force levels, which require 30-gram minimum. However, based contact geometry, this lower force translates contact pressures that high enough achieve oxide penetration good electrical continuity.
witness marks left solder ball from contact shown Figure This ball contacted room temperature clear that there damage bottom ball witness marks from contact above equator. effect burn-in probe marks examined simulating cycle placing loaded socket into oven 125°C hours. result shown Figure penetration contact into solder ball higher temperature greater well within acceptable range. There visible pickup solder contact tips. This experiment being continued evaluate impact longer times witness marks solder pickup. location contact pinch clearly seen this photograph. Figure Witness Marks Solder Ball
Conclusions Future Work
importance continuing development 0.5-mm pitch clear. users want more more electronic functionality smaller smaller packages. Sockets testing these fine pitches available today specialty considered expensive broad commercial application. Continued development includes innovative approaches well refining present methods, time preparation this Reference Guide, clear-cut favorite technology emerged. current progress this other areas 0.5-mm-pitch technology, your local Field Sales representative give up-to-date information.
Sockets
MicroStar Packaging Reference Guide
Sockets
Growth rates high 400% CSPs 1998 over those 1997 have been forecasted. opportunity participate market with this growth provided incentive socket companies develop solutions infrastructure needed burn-in test sockets. issues contacting small, soft solder balls CSPs have been solved. price disparity between sockets TSOP sockets expected during
early days introduction technology entirely embryonic state industry volume. believed that once this packaging technology matures volumes increase those conventional burn-in sockets, then prices sockets CSPs will decrease more line with other commercial sockets.
Sockets
MicroStar Packaging Reference Guide
References
MicroStar Packaging Reference Guide
References
References
al., "MicroStar BGAs," Application Note, 2328, July 1998. Gerald Capwell, "High Density Design with MicroStar BGAs," Texas Instruments Application Note, July 1998. James Forster, "Performance Drivers Fine Pitch Sockets," Chip Scale Processing, June 1998. Kevin Lyne, "Chip Scale Packaging From Texas Instruments: MicroStar BGA," Texas Instruments Application Note, June 1997.
Gary Morrison, Stark, Azcarte, Capistrano, Ano, Murata, Watanabe, Ohuchida, Takahashi, Greg Ryan, "MicroStar Packaging: Critical Interconnections," SEMICON '98. Stark M'hamed Idnabdeljalil, "MicroStar FC-CSP: Finite Element Simulation Performance: 144GGF Footprint," Texas Instruments Application Note, August 1998.
References
MicroStar Packaging Reference Guide
Appendix
Frequently Asked Questions
Package Questions
solder balls come during shipping? this never been observed. balls 100% inspected coplanarity, diameter, other physical properties prior packing shipment. Because solder used during ball-attachment process, uniformly high ball-attachment strengths developed. Also, ball-attachment strength monitored frequently assembly process prevent ball loss from vibration other shipping forces. package repair possible? tools available? Yes, some limited package repair possible, there some semiautomatic tools available. However, does guarantee reliability repaired packages. What leads that appear package edge for? they connected inner pattern? Those leads used plating connections during plating Ni/Au copper trace during fabrication substrate. Since they have electrical connection with inner pattern, they used test probing signal analysis. There reliability risk with them. What composition melting point solder balls? balls near-Sn/Pb eutectic solder that includes some additives improve thermal fatigue life. liquidus temperature 178°C 210°C. burn-in testing possible? about ball damage? There commercial sockets available 1.00-mm 0.8-mm pitch package burn-in. Sockets 0.5-mm pitch packages becoming available. Vendors include Texas Instruments, Yamaichi, Wells Enplas. ball damage observed falls within specified tolerances, testing does affect board mount. tape-and-reel shipping available? Tape-and-reel preferred method shipping MicroStar packages. Tray shipping methods available upon customer request. What about actual market experience? Since started production 1996, well over million units have been shipped. products primarily Solutions such wireless phones digital camcorders where MicroStar create significant space savings. Technologies available MicroStar BGAs include DSP, ASIC, Mixed Signal, Linear devices. does packaging cost compare QFPs? CSPs many ways ideal solution cost reduction miniaturization requirements. They offer enormous area reductions comparison QFPs have increasing potential without adding system-level costs. best case, CSPs compete today cost-per-terminal basis with QFPs. example, various CSPs from Texas Instruments available cost parity with thin QFPs.
Appendix Questions
MicroStar Packaging Reference Guide
Frequently Asked Questions
Assembly Questions
What alignment accuracy possible? Alignment accuracy 0.8-mm-pitch package dependent upon board-level tolerance, placement accuracy, solder ball position tolerance. Nominal ball position tolerances specified These packages self-aligning during solder reflow, final alignment accuracy better than placement accuracy. solder joints inspected after reflow? Process yields 5-ppm (parts million) rejects typically seen, final in-line inspection required. Some customers achieving satisfactory results during process set-up with lamographic X-ray techniques. board assembly yields MicroStar BGAs compare QFPs? Many customers initially concerned about assembly yields. However, once they MicroStar BGAs production, most them report improved process yields compared QFPs. This elimination bent misoriented leads, wider terminal pitch than with 0.5-mm-pitch QFPs, ability these packages self-align during reflow. collapsing solder balls also mean that coplanarity improved over leaded components. there specific recommendations processing? Texas Instruments recommends alignment with solder balls package, although possible package outline alignment. Most customers have found they need change their reflow profile. boards repaired? Yes, there rework repair tools profiles available. strongly recommend that removed packages discarded. developing lead-free version MicroStar BGAs? Yes, Texas Instruments working toward eliminating lead solder balls comply with lead-free environmental policies. lead-free solder final evaluation. Only solder will change, package structure mechanical dimensions. solder system under development based Sn-Ag metallurgy. Check with your local Field Sales representative sample availability. What size land diameter these packages should design board? Land size board-level reliability, Texas Instruments strongly recommends following design rules included this bulletin.
Appendix Questions
MicroStar Packaging Reference Guide
Appendix
Package Data Sheets
Figure shows TI's strategic package lineup, followed package data sheets package families offered standard products Texas Instruments. packages added, they will placed Figure TI's Strategic Package Line-Up
MicroStar BGAt Package Product Guide Strategic Package Lineup: HIJI Philippines PITCH (mm) PACKAGE SIZE (mm)
strategic package lineup. Contact your field sales office information most current offerings. Samples available packages shown Figure
Qual:
Qual:
Qual: Complete
Qual: Complete
PITCH
Qual: Complete
Qual: Complete
Qual: Complete Qual: Complete Qual: Complete
Qual: Complete
Qual: Complete
Qual: Complete
Qual: Complete
Qual: Complete
Qual: Complete
Qual: Complete
MicroStar Packaging Reference Guide
Appendix Package Data Sheets
Package Data Sheets
80GJK PACKAGE OUTLINE pitch)
(S-PBGA-N80) PLASTIC BALL GRID ARRAY VIEW DAISY CHAIN LIST
INDEX MARK NOTES: linear dimensions millimeters. This drawing subject change without notice. MicroStar BGAconfiguration Electrical Characteristics B1-C1 D1-E1 F1-G1 H1-J1 J2-J3 J4-J5 J6-J7 J8-J9 H9-G9 F9-E9
G4-G5 G6-G7 F7-E7 D7-C7 C6-C5 C4-D4 E4-F4 F5-F6 E6-D6 D5-E5
Thermal Characteristics
D9-C9 B9-A9 A8-A7 A6-A5 A4-A3 A2-B2 C2-D2 E2-F2 G2-H2 H3-H4
H5-H6 H7-H8 G8-F8 E8-D8 C8-B8 B7-B6 B5-B4 B3-C3 D3-E3 F3-G3
PIN# BALL# PIN# BALL#
ASSIGNMENT LIST
PIN# BALL# PIN# BALL#
Productization
Appendix Package Data Sheets MicroStar trademark Texas Instruments Incorporated.
MicroStar Packaging Reference Guide
Package Data Sheets
167GJJ PACKAGE OUTLINE pitch)
(S-PBGA-N167) PLASTIC BALL GRID ARRAY VIEW DAISY CHAIN LIST
INDEX MARK B1-C1 F3-G3 D1-E1 H3-J3 F1-G1 K3-L3 H1-J1 M3-M4 K1-L1 B4-B5 M1-N1 C4-D4 A2-B2 E4-F4 C2-D2 G4-H4 E2-F2 J4-K4 G2-H2 L4-L5 J2-K2 N4-N5 L2-M2 A5-A6 N2-N3 C5-C6 A3-A4 D5-E5 B3-C3 F5-G5 D3-E3 H5-J5
NOTES: linear dimensions millimeters. This drawing subject change without notice. MicroStar BGAconfiguration Electrical Characteristics
K5-K6 M5-M6 B6-B7 D6-D7 E6-F6 G6-H6 J6-J7 L6-L7 N6-N7 A7-A8 C7-C8 E7-E8 H7-H8 K7-K8 M7-M8 B8-B9 D8-D9 F8-G8 J8-J9 L8-L9 N8-N9 A9-A10 C9-C10 E9-F9 G9-H9 K9-K10 M9-M10 B10-B11 D10-E10 F10-G10 H10-J10 L10-L11 N10-N11 G13-H13 A11-A12 J13-K13 C11-D11 L13-M13 E11-F11 G11-H11 J11-K11 M11-M12 B12-C12 D12-E12 F12-G12 H12-J12 K12-L12 N12-N13 A13-B13 C13-D13 E13-F13
Thermal Characteristics
ASSIGNMENT LIST
PIN# BALL#
PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL#
Productization
MicroStar trademark Texas Instruments Incorporated.
MicroStar Packaging Reference Guide
Appendix Package Data Sheets
Package Data Sheets
151GHZ PACKAGE OUTLINE pitch)
(S-PBGA-N151) PLASTIC BALL GRID ARRAY VIEW DAISY CHAIN LIST
INDEX MARK NOTES: linear dimensions millimeters. This drawing subject change without notice. MicroStar BGAconfiguration Electrical Characteristics R13-T13 P13-T14 R14-V14 R15-T15 T16-V16 V17-V18 U17-U18 P14-T18 R16-R18 P15-P16 N15-N18 M15-N16 L15-M16 L16-L18 K15-K16 J15-J16 H15-J18 G15-H16 G16-G18 F15-F16 E16-F14 E15-E18 D15-D16 C16-C18 A18-B18 A17-B17 A16-E14 A15-C15 C14-D14 A13-D13 C13-D12 C12-D11 A11-C11 C10-D10 C9-D9 A9-D8 C8-D7 A7-C7 C6-D6 A5-C5 C4-D5 C3-D4 A2-A3
Thermal Characteristics
B1-B2 C1-E5 D1-D3 E3-E4 F1-F4 F3-G4 G3-H4 H1-H3 J3-J4 K3-K4 K1-L4 L3-M4 M1-M3 N3-N4 N5-P3 P1-P4
R3-R4 T1-T3 U1-V1 U2-V2 P5-V3 T4-V4 R5-T5 R6-V6 R7-T6 R8-T7 T8-V8 R9-T9 R10-T10 R11-V10 R12-T11 T12-V12
PIN# BALL# PIN# BALL# PIN#
ASSIGNMENT LIST
BALL# PIN# BALL# PIN# BALL#
Productization
Appendix Package Data Sheets MicroStar trademark Texas Instruments Incorporated.
MicroStar Packaging Reference Guide
Package Data Sheets
100GGM PACKAGE OUTLINE pitch)
(S-PBGA-N100) PLASTIC BALL GRID ARRAY VIEW DAISY CHAIN LIST
INDEX MARK B2-B1 C2-C3 C1-D2 D1-D3 E1-E2 E3-E4 F1-F2 F3-F4 G4-G1 G2-G3 H1-H2 J1-K1 J2-K2 J3-H3 K3-J4 K4-H4 K5-J5 H5-G5 K6-J6 H6-G6 G7-K7 J7-H7 K8-J8 K9-K10 J9-J10 H9-H8 H10-G9 G10-G8 F10-F9 F8-F7 E10-E9 E8-E7 D7-D10 D9-D8 C10-C9 B10-A10
NOTES: linear dimensions millimeters. This drawing subject change without notice. MicroStar BGAconfiguration Electrical Characteristics Min. Mean Max. 0.071 0.076 0.081 (nH) 1.999 2.425 2.957 (pF) 0.296 0.440 0.589
Thermal Characteristics
B9-A9 B8-C8 A8-B7 A7-C7 A6-B6 C6-D6 A5-B5 C5-D5 D4-A4 B4-C4 A3-B3 A2-A1
E5,E6,F5,F6
PIN# BALL# PIN# BALL#
ASSIGNMENT LIST
PIN# BALL# PIN# BALL#
Productization
MicroStar trademark Texas Instruments Incorporated.
MicroStar Packaging Reference Guide
Appendix Package Data Sheets
Package Data Sheets
64GGV PACKAGE OUTLINE pitch)
(S-PBGA-N64) PLASTIC BALL GRID ARRAY VIEW DAISY CHAIN LIST
INDEX MARK A1-B1 C2-C1 D4-D3 D1-D2 E2-E1 E3-F1 F2-F3 G1-G2 H1-H2 G3-H3 E4-F4 H4-G4 G5-H5 F5-H6 G6-F6 H7-G7 H8-G8 F7-F8 E5-E6 E8-E7 D7-D8 D6-C8 C7-C6 B8-B7 A8-A7 B6-A6 D5-C5 A5-B5 B4-A4 C4-A3 B3-C3 A2-B2
NOTES: linear dimensions millimeters. This drawing subject change without notice. MicroStar BGAconfiguration Electrical Characteristics Min. Mean Max. 0.071 0.076 0.082 (nH) 2.002 2.544 3.443 (pF) 0.273 0.380 0.580
Thermal Characteristics
ASSIGNMENT LIST
PIN# BALL#
PIN# BALL# PIN# BALL# PIN# BALL#
Productization
Appendix Package Data Sheets MicroStar trademark Texas Instruments Incorporated.
MicroStar Packaging Reference Guide
Package Data Sheets
80GGM PACKAGE OUTLINE pitch)
(S-PBGA-N80) PLASTIC BALL GRID ARRAY VIEW DAISY CHAIN LIST
INDEX MARK
NOTES: linear dimensions millimeters. This drawing subject change without notice. MicroStar BGAconfiguration Electrical Characteristics Min. Mean Max. 0.054 0.062 0.074 (nH) 1.487 1.920 2.659 (pF) 0.215 0.315 0.428
Thermal Characteristics
B2-B1 C2-C3 C1-D2 D1-D3 E1-E2 E3-F1 F2-F3 G1-G2 G3-H1 H2-J1
J2-K2 J3-H3 K3-J4 K4-H4 K5-J5 H5-K6 J6-H6 K7-J7 H7-K8 J8-K9
J9-J10 H9-H8 H10-G9 G10-G8 F10-F9 F8-E10 E9-E8 D10-D9 D8-C10 C9-B10
B9-A9 B8-C8 A8-B7 A7-C7 A6-B6 C6-A5 B5-C5 A4-B4 C4-A3 B3-A2
PIN# BALL# PIN# BALL#
ASSIGNMENT LIST PIN# BALL# PIN# BALL#
Productization
MicroStar trademark Texas Instruments Incorporated.
MicroStar Packaging Reference Guide
Appendix Package Data Sheets
Package Data Sheets
100GGF PACKAGE OUTLINE pitch)
(S-PBGA-N100) PLASTIC BALL GRID ARRAY VIEW DAISY CHAIN LIST
INDEX MARK
NOTES: linear dimensions millimeters. This drawing subject change without notice. MicroStar BGAconfiguration Electrical Characteristics Min. Mean Max. 0.011 0.022 0.035 (nH) 0.676 1.026 1.606 (pF) 0.102 0.172 0.339
Thermal Characteristics
B1-C2 R2-P3 C1-D2 R3-P4 D1-E2 R4-P5 E1-F2 R5-P6 F1-G2 R6-P7 G1-H2 R7-P8 J1-J2 R9-P9 K1-K2 R10-P10 L1-L2 R11-P11 M1-M2 R12-P12 N1-N2 R13-P13 P1-R1 R14-R15 NC-- H15,
P15-N14 N15-M14 M15-L14 L15-K14 K15-J14 J15-H14 G15-G14 F15-F14 E15-E14 D15-D14 C15-C14 B15-A15
A14-B13 A13-B12 A12-B11 A11-B10 A10-B9 A9-B8 A7-B7 A6-B6 A5-B5 A4-B4 A3-B3 A2-A1
ASSIGNMENT LIST BALL# PIN# BALL#
Productization
Appendix Package Data Sheets
PIN# BALL# PIN# BALL# PIN#
MicroStar trademark Texas Instruments Incorporated.
MicroStar Packaging Reference Guide
Package Data Sheets
100GGT PACKAGE OUTLINE pitch)
(S-PBGA-N100) PLASTIC BALL GRID ARRAY VIEW DAISY CHAIN LIST
INDEX MARK
NOTES: linear dimensions millimeters. This drawing subject change without notice. MicroStar BGAconfiguration Electrical Characteristics Min. Mean Max. 0.072 0.077 0.086 (nH) 2.200 2.636 3.633 (pF) 0.254 0.398 0.582
Thermal Characteristics
E3,J5,H11,A8
PIN# BALL# PIN#
ASSIGNMENT LIST BALL# PIN# BALL# PIN# BALL#
Productization
MicroStar trademark Texas Instruments Incorporated.
MicroStar Packaging Reference Guide
Appendix Package Data Sheets
Package Data Sheets
144GGU PACKAGE OUTLINE pitch)
(S-PBGA-N144) PLASTIC BALL GRID ARRAY VIEW DAISY CHAIN LIST
INDEX MARK
NOTES: linear dimensions millimeters. This drawing subject change without notice. MicroStar BGAconfiguration Electrical Characteristics Min. Mean Max. 0.052 0.055 0.062 (nH) 1.438 1.958 3.095 (pF) 0.215 0.305 0.563
Thermal Characteristics
A1-B1 C2-C1 D4-D3 D2-D1 E4-E3 E2-E1 F4-F3 F2-F1 G2-G1 G3-G4 H1-H2 H3-H4 J1-J2 J3-J4 K1-K2 K3-L1 L2-L3 M1-M2 PIN# BALL#
N1-N2 M3-N3 K4-L4 M4-N4 K5-L5 M5-N5 K6-L6 M6-N6 M7-N7 L7-K7 N8-M8 L8-K8 N9-M9 L9-K9 N10-M10 L10-N11 M11-L11 N12-M12
N13-M13 L12-L13 K10-K11 K12-K13 J10-J11 J12-J13 H10-H11 H12-H13 G12-G13 G11-G10 F13-F12 F11-F10 E13-E12 E11-E10 D13-D12 D11-C13 C12-C11 B13-B12
A13-A12 B11-A11 D10-C10 B10-A10 D9-C9 B9-A9 D8-C8 B8-A8 B7-A7 C7-D7 A6-B6 C6-D6 A5-B5 C5-D5 A4-B4 C4-A3 B3-C3 A2-B2
ASSIGNMENT LIST PIN# BALL# PIN# BALL# PIN# BALL#
Productization
Appendix Package Data Sheets MicroStar trademark Texas Instruments Incorporated. B-10
MicroStar Packaging Reference Guide
Package Data Sheets
179GHH PACKAGE OUTLINE pitch)
(S-PBGA-N179) PLASTIC BALL GRID ARRAY VIEW
INDEX MARK
DAISY CHAIN LIST
B2-B1 C3-C2 C1-D4 D3-D2 D1-E4 E3-E2 E1-F4 F3-F2 F1-F5 G5-G2 G1-G3
H3-H1 H2-H4 H5-J1 J2-J3 J4-K1 K2-K3 J5-L1 L2-L3 K4-M1 M2-K5 N1-P1
N2-P2 M3-N3 P3-L4 M4-N4 P4-L5 M5-N5 P5-L6 M6-N6 P6-K6 K7-N7 P7-M7
M8-P8 N8-L8 K8-P9 N9-M9 L9-P10
N13-N14 G12-G14 B13-A13 C7-A7 M12-M13 G13-G11 C12-B12 B7-D7 M14-L11 G10-F14 A12-D11 E7-A6 L12-L13 L14-K11 F13-F12 F11-E14 C11-B11 A11-D10 B6-C6
NOTES: linear dimensions millimeters. This drawing subject change without notice. MicroStar BGAconfiguration Electrical Characteristics
D6-A5 N10-M10 K12-K13 E13-E12 C10-B10 B5-C5 K9-P11 K14-J11 F10-D14 A10-D9 E6-A4 N11-M11 J12-J13 D13-D12 C9-B9 B4-C4 L10-P12 J14-J10 E11-C14 A9-E9 D5-A3 N12-K10 H10-H13 C13-E10 E8-B8 P13-P14 H14-H12 B14-A14 A8-C8 B3-E5 F6-A2
D8,G4,H11,L7,A2
Thermal Characteristics
ASSIGNMENT LIST
PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# (179 ball))
Productization
MicroStar trademark Texas Instruments Incorporated.
MicroStar Packaging Reference Guide
B-11
Appendix Package Data Sheets
Package Data Sheets
176GGW PACKAGE OUTLINE pitch)
(S-PBGA-N176) PLASTIC BALL GRID ARRAY VIEW
INDEX MARK
DAISY CHAIN LIST
NOTES: linear dimensions millimeters. This drawing subject change without notice. MicroStar BGAconfiguration Electrical Characteristics Min. Mean Max. 0.075 0.083 0.099 (nH) 1.595 2.417 3.284 (pF) 0.204 0.298 0.425
Thermal Characteristics
B1-C2 C1-D3 D2-D1 E3-E2 E1-F3 F2-F1 G4-G3 G2-G1 H1-H4 H3-H2 J1-J4 J3-J2 K1-K2 K3-K4 L1-L2 L3-L4 M1-M2 M3-N1 N2-N3 P1-P2 P3-R1 R2-T1
U2-T3 U3-R4 T4-U4 R5-T5 U5-R6 T6-U6 P7-R7 T7-U7 U8-P8 R8-T8 U9-P9 R9-T9 U10-T10 R10-P10 U11-T11 R11-P11 U12-T12 R12-U13 T13-R13 U14-T14 R14-U15 T15-U16
T17-R16 R17-P15 P16-P17 N15-N16 N17-M15 M16-M17 L14-L15 L16-L17 K17-K14 K15-K16 J17-J14 J15-J16 H17-H16 H15-H14 G17-G16 G15-G14 F17-F16 F15-E17 E16-E15 D17-D16 D15-C17 C16-B17
A16-B15 A15-C14 B14-A14 C13-B13 A13-C12 B12-A12 D11-C11 B11-A11 A10-D10 C10-B10 A9-D9 C9-B9 A8-B8 C8-D8 A7-B7 C7-D7 A6-B6 C6-A5 B5-C5 A4-B4 C4-A3 B3-A2
PIN# BALL# PIN#BALL# PIN#
ASSIGNMENT LIST
BALL# PIN# BALL# PIN# BALL#
Productization
Appendix Package Data Sheets MicroStar trademark Texas Instruments Incorporated. B-12
MicroStar Packaging Reference Guide
Package Data Sheets
208GGW PACKAGE OUTLINE pitch)
(S-PBGA-N208) PLASTIC BALL GRID ARRAY VIEW
INDEX MARK
DAISY CHAIN LIST
B2-C2 B1-C1 D3-D2
J1-K4 K3-K2 K1-L4 L3-L2 L1-M4 M3-M2 M1-N4 N3-N2 N1-P4 P1-P3 P2-R1 R2-T1 R3-U1
T2-T3 U2-U3 R4-T4 U4-P5 R5-T5 U5-P6 R6-T6 U6-P7 R7-T7 U7-P8 R8-T8 U8-P9 R9-T9
U9-P10 R10-T10 U10-P11 R11-T11 U11-P12 R12-T12 U12-P13 R13-T13 U13-P14 U14-R14 T14-U15 T15-U16 R15-U17
T16-R16 T17-R17 P15-P16
J17-H14
B16-B15
A9-D8 C8-B8 A8-D7 C7-B7 A7-D6 C6-B6 A6-D5 C5-B5 A5-D4 A4-C4 B4-A3 B3-A2 C3-A1
H15-H16 A16-A15 H17-G14 C14-B14
NOTES: linear dimensions millimeters. This drawing subject change without notice. MicroStar BGAconfiguration Electrical Characteristics Min. Mean Max. 0.070 0.075 0.079 (nH) 1.824 2.266 3.416 (pF) 0.217 0.278 0.433
D1-E4 E3-E2 E1-F4 F3-F2 F1-G4 G3-G2 G1-H4 H3-H2 H1-J4 J3-J2
P17-N14 G15-G16 A14-D13 N15-N16 G17-F14 N17-M14 F15-F16 M15-M16 F17-E14 M17-L14 E15-E16 L15-L16 L17-K14 K15-K16 K17-J14 J15-J16 E17-D14 C13-B13 A13-D12 C12-B12 A12-D11 C11-B11
D17-D15 A11-D10 D16-C17 C10-B10 C16-B17 C15-A17 A10-D9 C9-B9
Thermal Characteristics
ASSIGNMENT LIST
PIN# BALL# PIN# BALL#PIN# BALL#PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN#BALL#
Productization
MicroStar trademark Texas Instruments Incorporated.
MicroStar Packaging Reference Guide
B-13
Appendix Package Data Sheets
Package Data Sheets
240GGW PACKAGE OUTLINE pitch)
(S-PBGA-N240) PLASTIC BALL GRID ARRAY VIEW
INDEX MARK
DAISY CHAIN LIST
B2-C2 B1-C1 D3-D2 D1-E5
J2-J1 K5-K4 K3-K2 K1-L5 L4-L3 L2-L1 M5-M4 M3-M2 M1-N4
T2-T3 U2-U3 R4-T4 U4-N5 P5-R5 T5-U5 N6-P6 R6-T6 U6-N7 P7-R7 T7-U7 N8-P8 R8-T8 U8-N9 P9-R9
T9-U9 N10-P10 R10-T10 U10-N11 P11-R11 T11-U11 N12-P12 R12-T12 U12-P13 R13-T13 U13-P14 U14-R14 T14-U15 T15-U16 R15-U17
T16-R16 T17-R17 P15-P16
J16-J17 H13-H14 H15-H16
B16-B15 B9-A9 A16-A15 E8-D8 C14-B14 C8-B8 A14-E13 A8-E7 D13-C13 D7-C7 B13-A13 B7-A7 E12-D12 E6-D6 C12-B12 C6-B6 A12-E11 A6-D5 D11-C11 C5-B5 B11-A11 A5-D4
P17-N13 H17-G13 N14-N15 G14-G15 N16-N17 G16-G17 M13-M14 F13-F14 M15-M16 F15-F16 M17-L13 F17-E14 L14-L15 L16-L17 K13-K14 K15-K16 K17-J13 J14-J15 E15-E16 E17-D14 D17-D15 D16-C17 C16-B17 C15-A17
NOTES: linear dimensions millimeters. This drawing subject change without notice. MicroStar BGAconfiguration Electrical Characteristics
E4-E3 E2-E1 F5-F4 F3-F2 F1-G5
G4-G3 N3-N2 G2-G1 N1-P4 H5-H4 H3-H2 H1-J5 P1-P3 P2-R1 R2-T1 R3-U1
E10-D10 A4-C4 C10-B10 B4-A3 A10-E9 D9-C9 B3-A2 C3-A1
Thermal Characteristics
J4-J3
ASSIGNMENT LIST
PIN#BALL# PIN#BALL# PIN#BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL#
Productization
Appendix Package Data Sheets
MicroStar trademark Texas Instruments Incorporated. B-14
MicroStar Packaging Reference Guide
Package Data Sheets
196GHC PACKAGE OUTLINE pitch)
(S-PBGA-N196) PLASTIC BALL GRID ARRAY VIEW
INDEX MARK
DAISY CHAIN LIST
NOTES: linear dimensions millimeters. This drawing subject change without notice. MicroStar BGAconfiguration Electrical Characteristics Min. Mean Max. 0.078 0.092 0.123 (nH) 2.174 3.288 6.418 (pF) 0.256 0.470 1.071
Thermal Characteristics
Internal connection
ASSIGNMENT LIST
PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL#
Productization
Internal connection
MicroStar trademark Texas Instruments Incorporated.
MicroStar Packaging Reference Guide
B-15
Appendix Package Data Sheets
Package Data Sheets
257GHK PACKAGE OUTLINE pitch)
(S-PBGA-N257) PLASTIC BALL GRID ARRAY VIEW
INDEX MARK R10-P10 U11-P11 V12-U12 P12-R12 U13-P13 R13-U14 V15-R14 V18-V19 U19-T18 P15-N14 R18-R19 N15-P19 N18-N19 K15-K14 J19-J18 J17-J14 J15-H19 H18-H17 H14-H15 G19-G18 G17-G14 G15-F17 B18-A18 A17-B16 E14-F13 B15-A15 E13-A14 F12-C13 B13-A13 B12-A12 A11-B11 C11-E11 F11-A10 E10-F10 C9-F9 B8-C8 F8-E8 C7-F7 A6-B6 E7-C6 B5-E6 C5-A4 B4-A3 C4-B3
DAISY CHAIN LIST
NOTES: linear dimensions millimeters. This drawing subject change without notice. MicroStar BGAconfiguration Electrical Characteristics
B2-B1 K5-K6 V2-W2 D3-C2 L1-L2 C1-D2 L3-L6 U4-V3 W3-V4
W11-V11 T17-U18 R11-W12 T19-R17
C16-B17 A9-B9 A16-C15 E9-A8
D1-E3 L5-M1 W4-U5 F5-G6 M2-M3 R6-P7 E2-E1 M6-M5 V5-W5 F3-F2 N1-N2 U6-V6 G5-F1 N3-N6 R7-W6 H6-G3 P1-P2 P8-U7 G2-G1 N5-P3 V7-W7 H5-H3 R1-P6 R8-U8
W13-V13 P17-P18
C14-B14 A7-B7
W14-V14 M14-N17 F19-F18 W15-P14 M15-M17 E19-F14 M18-M19 E18-F15 E17-D19 D18-C19 D17-C18 B19-C17 U15-W16 L19-L18 V16-W17 L17-L15 L14-K19
E12-C12 A5-F6
Thermal Characteristics
H2-H1 R2-P5 V8-W8 J1-J2 J3-J5 J6-K1 R3-T1 W9-V9 T2-U1 U9-R9
T3-U2 P9-W10 U16-V17
K2-K3 V1-U3 V10-U10 W18-U17 K18-K17 NC-E5
B10-C10 A2-C3
ASSIGNMENT LIST
PIN#BALL# PIN#BALL# PIN#BALL#
PIN#BALL# PIN#BALL# PIN#BALL# PIN#BALL# PIN#BALL#
Productization
Appendix Package Data Sheets
BALL
MicroStar trademark Texas Instruments Incorporated. B-16
MicroStar Packaging Reference Guide
Package Data Sheets
257GJG PACKAGE OUTLINE pitch)
(S-PBGA-N257) PLASTIC BALL GRID ARRAY VIEW
INDEX MARK
DAISY CHAIN LIST
B2-B1 C1-C2 D1-D2 E4-E5 E1-E2 F5-F4 F1-F2 G6-G5 G2-G1 G4-H6 H1-H2 H4-H5 J4-J1 J2-J5 J6-K6 K1-K2
NOTES: linear dimensions millimeters. This drawing subject change without notice. MicroStar BGAconfiguration Electrical Characteristics
K4-K5 L6-L1 L2-L4 L5-M6 M1-M2 M4-M5 N7-N1 N2-N4 N5-N6 P1-P2 P4-P5 P6-R1 R2-R4 T1-T2 U1-T4 U2-V1
V2-W2 T10-R10 W3-V3 P11-W11 W4-V4 V11-T11 R11-P12 T5-R5 W5-V5 W12-V12 T12-R12 R6-T6 W6-V6 N13-W13 V13-T13 P7-R7 V7-W7 R13-P13 W14-V14 T7-P8 W8-V8 T14-R14 P14-W15 T8-R8 T9-W9 V15-T15 W16-V16 V9-R9 P9-P10 W17-T16 W10-V10 V17-W18
V18-V19 U19-U18 T19-T18 R16-R15 R19-R18 P15-P16 P19-P18 N14-N15 N18-N19 N16-M14 M19-M18 M16-M15 L16-L19 L18-L15 L14-K14 K19-K18
K16-K15 J14-J19 J18-J16 J15-H14 H19-H18 H16-H15 G13-G19 G18-G16 G15-G14 F19-F18 F16-F15 F14-E19 E18-E16 D19-D18 C19-D16 C18-B19
B18-A18 D10-E10 A17-B17 A16-B16 D15-E15 A15-B15 E14-D14 A14-B14 F13-E13 B13-A13 D13-F12 A12-B12 D12-E12 D11-A11 B11-E11 F11-F10 A10-B10 F9-A9 B9-D9 E9-F8 A8-B8 D8-E8 G7-A7 B7-D7 E7-F7 A6-B6 D6-E6 F6-A5 B5-D5 A4-B4 A3-D4 B3-A2
BALL-C3
Thermal Characteristics ASSIGNMENT LIST
PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN# BALL# PIN#BALL# PIN#BALL#
Productization
1PIN MARK
MicroStar trademark Texas Instruments Incorporated.
MicroStar Packaging Reference Guide
B-17
Appendix Package Data Sheets
Package Data Sheets
Notes
B-18
MicroStar Packaging Reference Guide
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