PM8620 NSE-20G Narrowband Switch Element Data Sheet
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NSE-20GStandard Product Data Sheet Preliminary
PM8620
NSE-20G
Narrowband Switch Element
Data Sheet
Preliminary Issue May, 2001
Proprietary Confidential PMC-Sierra, Inc., Customers' Internal Document PMC-2000170, Issue
NSE-20GStandard Product Data Sheet Preliminary
Legal Information
Copyright
2001 PMC-Sierra, Inc. information proprietary confidential PMC-Sierra, Inc., customers' internal use. event, cannot reproduce part this document, form, without express written consent PMC-Sierra, Inc. PMC-2000170 (P3)
Disclaimer
None information contained this document constitutes express implied warranty PMC-Sierra, Inc. sufficiency, fitness suitability particular purpose such information fitness, suitability particular purpose, merchantability, performance, compatibility with other parts systems, products PMC-Sierra, Inc., portion thereof, referred this document. PMC-Sierra, Inc. expressly disclaims representations warranties kind regarding contents information, including, limited express implied warranties accuracy, completeness, merchantability, fitness particular use, non-infringement. event will PMC-Sierra, Inc. liable direct, indirect, special, incidental consequential damages, including, limited lost profits, lost business lost data resulting from reliance upon information, whether PMC-Sierra, Inc. been advised possibility such damage.
Trademarks
S/UNI registered trademark PMC-Sierra, Inc. NSE-20G, SBS, CHESS, TEMUX-84, AAL1gator-32, FREEDM-336, SPECTRA, trademarks PMC-Sierra, Inc.
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Contacting PMC-Sierra
PMC-Sierra 8555 Baxter Place Burnaby, Canada Tel: (604) 415-6000 Fax: (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Site: http://www.pmc-sierra.com
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Table Contents
Features. Applications References Application Examples Block Diagram Description.19 Diagram Description.24 Description Table Analog Power Filtering Recommendations.41 LVDS Overview 9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 9.2.1 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 LVDS Receiver (RXLV) LVDS Transmitter (TXLV) LVDS Transmit Reference (TXREF) Data Recovery Unit (DRU) Parallel Serial Converter (PISO) Clock Synthesis Unit (CSU) FIFO Buffer.45 SBI336S 8B/10B Character Encoding Serial TelecomBus 8B/10B Character Encoding.47 Serial SBI336S TelecomBus Alignment Character Alignment Block.49 Frame Alignment SBI336S Multiframe Alignment
Functional Description
Receive 8B/10B Frame Aligner (R8TD) Transmit 8B/10B Encoder (T8TE).45
Cross switch (DCB) Clock Synthesis Transmit Reference Digital Wrapper (CSTR).53 Fabric Latency.53 JTAG Support.53 Microprocessor Interface In-band Link Controller (ILC).54
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9.9.1
In-Band Signaling Channel Fixed Overhead.55
9.10 Microprocessor Interface Normal Mode Register Description.60 Test Features Description.131 11.1 Master Test Test Configuration Registers .131 11.2 JTAG Test Port .134 11.2.1 Boundary Scan Cells.138 Operation .140 12.1 Software Default Settings .140 12.1.1 Setting T8TE Time-slot Configuration Register.140 12.1.2 Setting T8TE Time-slot Configuration Register.140 12.1.3 Configuring NSE-20G Fewer Links .140 12.1.4 Design Notes .142 12.2 "C1" Synchronization.142 12.3 Synchronized Control Setting Changes .143 12.3.1 SBS/NSE-20G Systems with switching .143 12.3.2 SBS/NSE-20G Systems switching DS0s without .145 12.3.3 SBS/NSE-20G Non-DS0 Level Switching with SBI336 Devices .147 12.4 NSE-20G Interaction with Switching Cycle When Using ILC.148 12.5 Controlling frame alignment receive port. .149 12.6 Cross-Bar Switch (DCB) Operation .150 12.6.1 Configuring using Port Transfer Mode.150 12.6.2 Configuring using Word Transfer Mode.151 12.6.3 Reading Configurations.152 12.6.4 Online Offline Memory Page Copy .152 12.7 TelecomBus Mode Operation.153 12.8 column Mode Operation.153 12.9 Mode Operation .154 12.10 with Mode Operation.154 12.11 Operation.155 12.12 Operations .156 12.12.1 Accessing Transmit Message FIFO .156 12.12.2 Accessing Receive Message FIFO .156 12.12.3 Handling Transmit Header .160 12.12.4 Handling Receive Header .160
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12.12.5 Handling Interrupts .160 12.12.6 Bypass Function.160 12.13 Switch Setting Algorithm .162 12.13.1 Problem Description .162 12.13.2 Algorithm .163 12.13.3 Bi-partite graphs .165 12.13.4 Unicast .166 12.13.5 Experimental Results .168 12.13.6 Multicast .168 12.14 JTAG Support.169 12.14.1 Controller .170 12.14.2 States.170 12.14.3 Instructions .171 Functional Timing.173 13.1 Receive Interface Timing .173 13.2 Transmit Interface Timing.174 Absolute Maximum Ratings.176 D.C. Characteristics.177 Microprocessor Interface Timing Characteristics .179 A.C. Timing Characteristics .182 17.1 Input Timing.182 Reset Timing .183 17.2 Serial Interface.184 17.3 JTAG Port Interface.184 Ordering Thermal Information .186 18.1 Packaging Information .186 18.2 Thermal Information .186 Mechanical Information .188 Notes .189
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List Registers
Register 000H: NSE-20G Master Reset.61 Register 001H: NSE-20G Individual Channel Reset.62 Register 002H: NSE-20G Master JTAG Register 003H: Page select Page Register 004H: Page select Page Register 005H: NSE-20G Master Interrupt Source Register 006H: NSE-20G Master Interrupt Source Register 007H: NSE-20G Master R8TD Interrupt Source.69 Register 008H: NSE-20G Master T8TE Interrupt Source Register 009H: NSE-20G Master Clock Monitor Register 00AH: NSE-20G select.72 Register 00BH: NSE-20G Interrupt Enable Register Register 00CH: NSE-20G Subsystem Interrupt Enable Register Register 00DH: NSE-20G R8TD Rgister Register 00EH: User Register 00FH: User Register 010H: User Register 011H: NSE-20G FREE User Register.79 Register 012H: Correct R8TD_RX_C1 Pulse Monitor Register 013H: Unexpected R8TD_RX_C1 Interrupt.81 Register 014H: Missing R8TD_RX_C1 Interrupt.82 Register 015H: Unexpected R8TD_RX_C1 Interrupt Enable Register 016H: Missing R8TD_RX_C1 Interrupt Enable Register 020H, 024H: CSTR Control*.85 Register 021H, 025H: CSTR Interrupt Enable Lock Status Register 022H, 026H: CSTR Interrupt Indication Register 040H: Configuration port 31-30 Register (NSE-20G only) Register 041H: Configuration port 29-24 Register (NSE-20G only) Register 042H: Configuration port 23-18 Register (NSE-20G only) Register 043H: Configuration port 17-12 Register Register 044H: Configuration port 11-6 Register.92 Register 045H: Configuration port Register Register 046H: Configuration Output Register
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Register 047H: Access Mode Register Register 048H: delay (RC1DLY) Register.97 Register 04AH: Frame size Register Register 04CH: Configuration Register Register 04DH: Interrupt status Register. .102 Register 100H N*20H: R8TD Control Status.103 Register 101H N*20H, R8TD Interrupt Status.105 Register 102H N*20H, R8TD Line Code Violation Count .107 Register 103H N*20H, RXLV Control .108 Register 108H N*20H, T8TE Control Status Register 109H N*20H, T8TE Interrupt Status Register 10AH N*20H: T8TE Time-slot Configuration Register 10BH N*20H: T8TE Time-slot Configuration Register 10CH N*20H, T8TE Test Pattern Register 10DH N*20H, TXLV PISO Control Register 110H N*20H, Transmit FIFO Data. Register 111h N*20H, Transmit Control Register Register 112h N*20H, Transmit Misc.Status FIFO Synch Register. Register 113h N*20H, Receive FIFO Data Register.121 Register 114h N*20H, Receive Control Register.122 Register 115h N*20H, Receive Auxiliary, Status FIFO Synch Register.123 Register 116h N*20H, Interrupt Enable Control Register .127 Register 117h N*20H: Interrupt Reason Register.130 Register 800H: NSE-20G Master Test .132
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List Figures
Figure OC-48 T1/E1 (Individually Drop/Add T1/E1 STS-48) Figure OC-48 T1/E1 (Drop/Add STS-48 STS-1 Granularity).14 Figure Any-Service-Any-Port Access Solution Figure Any-Service-Any-Port DS0-Granularity Card Figure NSE-20G Block Diagram Showing TSBs.17 Figure NSE-20G UBGA-480 Ball Diagram (Bottom-View).20 Figure Analog Power Filter Circuit.42 Figure Generic LVDS Link Block Diagram Figure Character Alignment State Machine Figure Frame Alignment State Machine.51 Figure In-Band Signaling Channel Message Format Figure In-Band Signaling Channel Header Format Figure Input Observation Cell (IN_CELL) .138 Figure Output Cell (OUT_CELL) .139 Figure Bidirectional Cell (IO_CELL) .139 Figure Layout Output Enable Bidirectional Cells.139 Figure Shutting down link .141 Figure "C1" Synchronization Control .143 Figure Switching with CAS.144 Figure Multiframe timing .145 Figure Switch Timing DSOs with .145 Figure TEMUX-84/SBS/NSE/SBS/FREEDM-336 system Switching CAS.146 Figure Switch Timing DSOs without .147 Figure Switch Timing .148 Figure Architecture Input Interface.150 Figure Position First Row.155 Figure Transport Overhead Affected .161 Figure Example Graph .164 Figure Time Space Time Switching NSE-20G four Single-Ported SBSs .164 Figure Example Graph .166 Figure Example Problem.167
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Figure Merged Graph .167 Figure Relabeled Graph .168 Figure Boundary Scan Architecture .169 Figure Controller Finite State Machine.170 Figure Receive Interface Timing .173 Figure Transmit Interface Timing .174 Figure Timing .175 Figure Microprocessor Interface Read Timing .179 Figure Microprocessor Interface Write Timing .181 Figure NSE-20G Input Timing .182 Figure RSTB Timing.183 Figure JTAG Port Interface Timing.185
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List Tables
Table Analog Power Filters Table SBI336S Character Encoding Table Serial TelecomBus Character Encoding Table Switching Control layout.53 Table In-band Message Header Fields Table NSE-20G Register Map.56 Table FIFO Message Level .120 Table FIFO Message Level .125 Table RXFIFO Threshold Values .128 Table RXFIFO Timeout Delay .128 Table Test Mode Register Memory .131 Table Instruction Register (Length bits) .134 Table Identification Register.134 Table Boundary Scan Register .135 Table Absolute Maximum Ratings.176 Table Characteristics .177 Table Microprocessor Interface Read Access .179 Table Microprocessor Interface Write Access.181 Table NSE-20G Input Timing Figure .182 Table RSTB Timing Figure .183 Table Serial Interface .184 Table JTAG Port Interface Figure .184
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Features
Narrowband Switch Element (NSE-20G): Implements Scaleable Bandwidth Interconnect (SBITM) granularity Space switch. Implements SONET/SDH VT1.5/VT2/TU11/TU12 granularity Space switch serial 777.6 LVDS TelecomBus. With allied SBS-lite device, implements granularity Memory-SpaceMemory switch. Supports STS-12 equivalent serial ports 777.6 MHz, 8B/10B encoded LVDS links (each port either Serial TelecomBus Serial SBI336S) When configured mode, switches N*DS0 tributaries aggregate columns switching TVT1.5, TVT2, tributaries. When configured serial 777.6 TelecomBus interface, switches SONET/SDH virtual tributary tributary unit STS-1. Supports switching arbitrary non-standard octet aggregates. Supports unicast, multicast, broadcast switching modes. Provides Gbit/s (258,048 DS0s, 10,752 T1s/VT1.5s, 8,064 E1s/VT2s, DS3s/E3s) switching. Works with devices that support four 19.44 buses 77.76 SBI336 that communicates with PMC-Sierra's device family. Alternatively, SBS-lite devices support four 19.44 STS-3 TelecomBuses 77.76 STS-12 TelecomBus connection with PMC-Sierra's SPECTRAfamily devices. combined applications with PMC-Sierra's CHESSSet devices (PM5374 PM5307 TBS). Supports microprocessor interface which used configure/control NSE, make DS0-granularity switch settings. Supports clean error checked Mbit/s full-duplex, in-band communications channels from NSE's attached microprocessor attached microprocessors each attached SBS336S devices. This channel used initialize control SBSs, other such devices, implement call-establishment set-up changes. Supports JTAG non-LVDS signals. Requires dual power supplies Packaged ball UBGA. conjunction with SBS-lite, supports "1+1" "1:N" fabric redundancy.
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Applications
PM8620 Narrowband Switch Element (NSE) supports variety flexible Layer Layer architectures combination with following PMC-Sierra devices: PM8610 PM8611 SBS-lite (SBI Serializer Memory switching stage) devices (PM8315 TEMUXTM/PM5365 TEMAP, FREEDMdevices, S/UNI®-IMA devices, AAL1gatordevices, other future devices) CHESS chip devices (PM5374 TSE, PM5307 TBS, PM5315 SPECTRATM-2488, PM7390 S/UNI®-MACH48)
These architectures include: T1/E1 SONET Add/Drop Multiplexers (ADMs) ASAP applications cards with (and above) level switching PSTN replacement switching cores, part any-service-any-port applications Voice Gateways
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References
ANSI T1.105-1995, "Synchronous Optical Network (SONET) Basic Description including Multiplex Structure, Rates, Formats", 1995. Telcordia SONET Transport Systems: Common Generic Criteria, GR-253-CORE, Issue Revision January 1999. ITU, Recommendation G.707 "Digital Transmission Systems Terminal equipments General", March 1996. IEEE 802.3, "Carrier SeNSE-20G Multiple Access with Collision Detection (CSMA/CD) Access Method Physical Layer Specifications", Section 36.2, 1998. A.X. Widmer P.A. Franaszek, DC-Balanced, Partitioned-Block, 8B/10B Transmission Code," Journal Research Development, Vol. September 1983, 440451. U.S. Patent 4,486,739, P.A. Franaszek A.X. Widmer, "Byte Oriented Balanced (0,4) 8B/10B Partitioned Block Transmission Code," December 1984. IEEE 1596.3-1996, "IEEE Standard Low-voltage Differential Signals (LVDS) Scalable Coherent Interface (SCI)", Approved March 1996 L.R. Ford, D.R. Fulkerson, "Flows Networks'', Maximum Cardinality Matchings Bipartite Graphs.
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Application Examples
Figure illustrates OC-48 SONET Ring Add/Drop Multiplexer. PM5363 TUPP-622 devices align paths transport frames preparation VT1.5/VT2 granularity switching. PM8610 SBI336 Serializer (SBSTM) PM8620 Narrowband Switching Element (NSE-20GTM) devices support VT1.5/VT2 above switching. Drop buses provided SBSs that SONET Ring path. this case, they connect mapper ports.
Figure OC-48 T1/E1 (Individually Drop/Add T1/E1 STS-48)
SPECTRA2488 TUPP622 TUPP622 SPECTRA2488
NSE20G
TEMAP
OCTAL -LIU
required terminate
links TEMAPS
Figure illustrates another OC-48 SONET Ring ADM. this application, network three PM5310 TelecomBus Serializers (TBSs) from PMC-Sierra's CHESSchip add, drop, groom traffic STS-1 granularities. four TUPP-622 devices align dropped STS-1s (paths transport frames). virtual tributary (VT) tributary unit (TU) switching solution provided SBS-NSE-20G-SBS network below TUPP-622s. Four SBSs support STS-48 amount add/drop traffic.
Figure OC-48 T1/E1 (Drop/Add STS-48 STS-1 Granularity)
SPECTA2488 SPECTA2488
TUPP622
NSE20G
device device device device device device device device device device device device device device device device
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Figure illustrates organization access line size card(s) from SONET Service Port (ASAP) product. traffic from NSE-20G link layer devices pathaligned. Figure description line cards compatible with system Figure
Figure Any-Service-Any-Port Access Solution
SBSlite
FREEDM336
Any-PHY (Packet)
NSE20G
IMA-84
Any-PHY (Cell)
AAL1gator32
Any-PHY (Cell)
TEMUX-84
H-MVIP
Processors
T1/E1/DS0/N*DS0 Layer Processing
Figure shows organization SONET card compatible with Figure shown, both Figure Figure have NSE-20Gs, only instance this device required connect SBSs. likely packaging this combined system would place NSE-20G (and standby NSE-20G) separate fabric cards. Figure four PM8315 TEMUXs align paths transport frames. Note: Figure assumes this alignment.
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Figure Any-Service-Any-Port DS0-Granularity Card
TEMUX-84
SPECTRA2488
TEMUX-84
NSE20G
TEMUX-84
TEMUX-84
SONET/T1/E1 Termination VT/TU/DS0 Switching
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Block Diagram
NSE-20G organized granularity space switch. NSE-20G also organized (with respect STS-12 boundaries TelecomBus mode) self aligning VT1.5/VT2 granularity space switch. Refer Figure
Figure NSE-20G Block Diagram Showing TSBs
RP[0] RN[0]
LVDS Receiver (RXLV)
Data Recovery Unit (DRU)
Receive 8B/10B Decoder (R8TD)
In-Band Link Controller (ILC) In-Band Link Controller (ILC)
In-Band Link Controller (ILC) In-Band Link Controller (ILC)
Transmit 8B/10B Encoder (T8TE)
LVDS Transmit Transmitt Serializer (PISO) (TXLV)
TP[0] TN[0]
RP[1] RN[1]
LVDS Receiver (RXLV)
Data Recovery Unit (DRU)
Receive 8B/10B Decoder (R8TD)
Transmit 8B/10B Encoder (T8TE)
LVDS Transmit Transmitt Serializer (PISO) (TXLV)
TP[1] TN[1]
RP[31] RN[31]
LVDS Receiver (RXLV)
Data Recovery Unit (DRU)
Receive 8B/10B Decoder (R8TD)
In-Band Link Controller (ILC)
In-Band Link Controller (ILC)
Transmit 8B/10B Encoder (T8TE)
LVDS Transmit Transmitt Serializer (PISO) (TXLV)
TP[31] TN[31]
Crossbar Switch (DCB) Clock Synthesis Units RC1FP SYSCLK
Microprocessor Interface
JTAG
A[11:0]
D[31:0]
INTB
TRSTB
RSTB
R8TD block, combination with RXLV receive, decode align incoming SBI336/STS-12-equivalent LVDS links. Outputs provided primary switching flow, in-band signaling channel. These provide analog digital functions terminate full-duplex 777.6 serial SBI336S 777.6 serial TelecomBus LVDS. Crossbar Switch (DCB) stage switches data control signals between ports. switching instructions stored pages configured offline online allowing user modify offline page.
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T8TE block, combination with PISO TXLV perform 8B/10B coding emits LVDS streams. These provide analog digital functions launch full-duplex 777.6 serial SBI336S 777.6 serial TelecomBus LVDS. microprocessor interface in-band signaling units (ILC) provide clean (error checked) channel between NSE-20G SBSs. This used send messages between NSE-20G microprocessor-and microprocessors user defined format.
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Description
PM8620 NSE-20G monolithic CMOS integrated circuit packaged ball UBGA that performs above granularity space switching SBI336 streams carried serial SBI336S 8B/10B coding over LVDS 777.6 Mbit/s. NSE-20G also performs VT1.5/VT2 above granularity switching STS-12/STM-4 SONET/SDH streams, carried Serial TelecomBus signals 8B/10B coding over LVDS 777.6 Mbit/s. NSE-20G typically used with PM8610 PM8611 SBS-lite devices provide Memory-Space-Memory switching systems. each supports either four buses 19.44 SBI336 77.76 MHz, overall system supports mixture SBI336 byte serial buses, ranging from 19.44 buses SBI336 77.76 buses that exceed aggregate bandwidth STS-384, about Gbit/s. TelecomBus mode, devices support same range flexibility 19.44 77.76 TelecomBuses VT1.5/VT2 granularity Central NSE-20G cross switch. every clock cycle, cross switches byte data with control signals from each input port output port. byte data channel from T1/E1 byte column comprising DS3, VT1.5, STS-1. order switching take place input output streams must synchronized. This done RC1FP input signal. When switching T1s, E1s, other higher order units only SBI336 multiframe alignment required. same applies TelecomBus mode where only frame alignment required. in-band control link over serial LVDS interface allows NSE-20G communicate with microprocessors attached SBS, SBS-lite other serial SBI336S devices. effective bandwidth each inband link each device Mbit/s. inband link provides error detection 32-byte user messages some near realtime control signals between devices. Using near realtime control signals, NSE-20G able synchronize page switching, indicate switchover between working protected links, exchange three user defined signals (software) Auxilliary signals (software). user auxilliary signals used indicates interrupts initiate handshaking between point microprocessors. message format left user devices. only constraint that each message maximum bytes long.
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Diagram
NSE-20G packaged ball UBGA.
Figure NSE-20G UBGA-480 Ball Diagram (Bottom-View)
VDDO
Reserved
Reserved
Reserved
VDDI
AVDH
VDDO
VDDO
VDDO
VDDI
VDDI
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RSTB
AVDH
AVDH
VDDO
VDDI
Reserved
VDDI
Reserved
VDDI
Reserved
Reserved
Reserved
Reserved
VDDI
AVDH
AVDH
AVDH
VDDO
Reserved
VDDI
VDDO
Reserved
VDDO
Reserved
Reserved
Reserved
VDDO
VDDI
RESK1
RES1
RN[32]
RP[32]
RN[31]
RP[31]
AVDL1
Upper Left
RN[30]
RP[30]
RN[29]
RP[29]
TP[32]
TN[32]
AVDH
TP[31]
TN[31]
TP[30]
TN[30]
TP[29]
TN[29]
VDDI
RN[28]
RP[28]
RN[27]
RP[27]
RN[26]
RP[26]
AVDH
VDDI
AVDL2
RN[25]
RP[25]
TP[28]
TN[28]
VDDI
TP[27]
TN[27]
TP[26]
TN[26]
TP[25]
TN[25]
AVDL4
AVDL3
RN[24]
RP[24]
AVDL5
CSU_A
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SYSCLK
Reserved
Reserved
VDDI
Reserved] Reserved
Reserved
Reserved
Reserved
VDDO
VDDO
VDDO
Reserved
VDDI
VDDI
Reserved
Reserved
Reserved
Reserved
VDDI
VDDO
VDDO
AVDH
RC1FP
VDDI
TRSTB
VDDI
VDDO
VDDI
Reserved
VDDO
Reserved
Reserved
VDDO
AVDH
AVDH
AVDH
ATB0[1] AVDH
AVDH
ATB1[1] TN[1]
TP[1]
Upper Right
TN[3]
TP[3]
TN[2]
TP[2]
AVDH
VDDI
RP[1]
RN[1]
TN[4]
TP[4]
VDDI
RP[2]
RN[2]
VDDI
AVDL14 RP[3]
RN[3]
AVDH
RP[4]
RN[4]
TN[6]
TP[6]
TN[5]
TP[5]
VDDI
TN[7]
TP[7]
RP[5]
RN[5]
TN[8]
TP[8]
AVDH
VDDI
AVDL13
RP[7]
RN[7]
RP[6]
RN[6]
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RN[22]
RP[22]
RN[23]
RP[23]
AVDL6
VDDI
AVDH
TP[24]
TN[24]
RN[21]
RP[21]
TP[23]
TN[23]
VDDI
Lower Left
TP[21]
TN[21]
TP[22]
TN[22]
RN[20]
RP[20]
AVDH
RN[19]
RP[19]
AVDL7
VDDI
RN[18]
RP[18]
VDDI
TP[20]
TN[20]
RN[17]
RP[17]
VDDI
AVDH
TP[18]
TN[18]
TP[19]
TN[19]
TP[17]
TN[17]
ATB1[2]
AVDH
AVDH
ATB0[2] AVDH
AVDH
AVDH
VDDO
VDDI
VDDO
A[6]
A[2]
VDDI
VDDO
D[27]
VDDI
VDDI
AVDH
VDDO
VDDO
VDDI
A[9]
A[5]
A[3]
D[31]
D[29]
VDDI
D[25]
VDDI
D[21]
D[20]
VDDO
VDDO
VDDO
INTB
A[10]
A[7]
A[4]
A[0]
D[30]
D[28]
D[26]
D[22]
D[19]
A[11]
A[8]
A[1]
D[24]
D[23]
D[18]
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CSU_A
AVDL12 RP[8]
RN[8]
AVDL10 AVDL11 TN[9]
TP[9]
TN[10]
TP[10]
TN[11]
TP[11]
Lower Right
VDDI
TN[12]
TP[12]
RP[9]
RN[9]
AVDL9
VDDI
AVDH
RP[10]
RN[10]
RP[11]
RN[11]
RP[12]
RN[12]
VDDI
TN[13]
TP[13]
TP[14]
TN[14]
TN[15]
TP[15]
AVDH
TN[16]
TP[16]
RP[13]
RN[13]
RP[14]
RN[14]
AVDL8
RP[15]
RN[15]
RP[16]
RN[16]
RES2
RESK2
D[17]
VDDO
D[13]
D[11]
D[8]
VDDO
D[5]
D[3]
D[0]
VDDO
VDDO
AVDH
AVDH
AVDH
VDDI
D[15]
VDDI
D[10]
D[9]
D[7]
D[2]
D[1]
VDDO
AVDH
AVDH
D[16]
D[14]
D[12]
VDDI
D[6]
D[4]
VDDI
VDDO
VDDO
VDDO
AVDH
VDDI
VDDI
VDDO
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Description
Description Table
Name
LVDS Ports (128 Balls) RP[1] RN[1] RP[2] RN[2] RP[3] RN[3] RP[4] RN[4] RP[5] RN[5] RP[6] RN[6] RP[7] RN[7] RP[8] RN[8] RP[9] RN[9] RP[10] RN[10] RP[11] RN[11] RP[12] RN[12] RP[13] RN[13] RP[14] RN[14] RP[15] RN[15] RP[16] RN[16] RP[17] RN[17] Analog LVDS Input AF31 AF32 Receive Serial Data. differential receive serial data links (RP[31:0]/RN[31:0]) carry receive SBI336S SONET/SDH STS-12 frame data from upstream sources serial format. Each differential pair RP[X]/RN[X] carries constituent SBI336 STS-12 stream. Data RP[X]/RN[X] encoded 8B/10B format extended from IEEE Std. 802.3. 8B/10B character transmitted first transmitted last. RP[X]/RN[X] differential pairs must frequency locked phase aligned (within certain tolerance) each other. RP[31:0]/RN[31:0] nominally 777.6 Mbit/s data streams. unused, available inputs should tied using resistor.
Type
Function
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Name
RP[18] RN[18] RP[19] RN[19] RP[20] RN[20] RP[21] RN[21] RP[22] RN[22] RP[23] RN[23] RP[24] RN[24] RP[25] RN[25] RP[26] RN[26] RP[27] RN[27] RP[28] RN[28] RP[29] RN[29] RP[30] RN[30] RP[31] RN[31] RP[32] RN[32]
Type
Analog LVDS Input
AE32 AE33 AD33 AD34 AC32 AC33
Function
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Name
TP[1] TN[1] TP[2] TN[2] TP[3] TN[3] TP[4] TN[4] TP[5] TN[5] TP[6] TN[6] TP[7] TN[7] TP[8] TN[8] TP[9] TN[9] TP[10] TN[10] TP[11] TN[11] TP[12] TN[12] TP[13] TN[13] TP[14] TN[14]
Type
Analog LVDS Output
Function
Transmit Serial Data. differential transmit working serial data links (TP[31:0]/TN[31:0]) carry transmit SBI336S SONET/SDH STS-12 frame data downstream sinks serial format. Each differential pair carries constituent STS-12 stream. Data TP[X]/TN[X] encoded 8B/10B format extended from IEEE Std. 802.3. 8B/10B character transmitted first transmitted last. TP[X]/TN[X] differential pairs frequency locked phase aligned (within certain tolerance) each other. TP[31:0]/TN[31:0] nominally 777.6 Mbit/s data streams.
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Name
TP[15] TN[15] TP[16] TN[16] TP[17] TN[17] TP[18] TN[18] TP[19] TN[19] TP[20] TN[20] TP[21] TN[21] TP[22] TN[22] TP[23] TN[23] TP[24] TN[24] TP[25] TN[25] TP[26] TN[26] TP[27] TN[27] TP[28] TN[28] TP[29] TN[29] TP[30] TN[30] TP[31] TN[31] TP[32] TN[32]
Type
Analog LVDS Output
AJ33 AJ32 AH34 AH33 AH32 AH31 AF34 AF33 AB34 AB33 AB32 AB31 AA33 AA32
Function
NSE-20G Control Clocking Balls) SYSCLK Input System Clock. system clock signal (SYSCLK) master clock NSE-20G device. SYSCLK must 77.76 clock, with nominal duty cycle. RC1FP sampled rising edge SYSCLK.
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Name
RC1FP
Type
Input
Function
Receive Serial Interface Frame Pulse. receive serial interface frame pulse signal (RC1FP) provides system timing receive serial interface. RC1FP supplied common devices system containing more NSE-20G devices. TelecomBus mode RC1FP high once every frames, mode without switching, when switching DS0s (WITHOUT CAS) RC1FP also high once every frames, multiple thereof. When mode switching DS0s WITH RC1FP indicates signaling multiframe alignment pulsing once every frames multiples thereof. software configurable delay from RC1FP used indicate that multiframe boundary 8B/10B characters have been delivered receive serial data links (RP[32:1]/RN[32:1]) ready processing time-space-time switching elements. RC1FP sampled rising edge SYSCLK.
Reserved
Output Input
Reserved pin, must left floating Connection Memory Page. connection memory page select signal (CMP) controls selection connection memory page NSE. When high, connection memory page selected. When low, connection memory page selected. Changes connection memory page selection synchronized boundary next C1FP frame multiframe depending mode: 4-Frame SBI/SBI336 mode: sampled byte position incoming first frame four-frame multiframe. Changes connection memory page selection synchronized frame boundary byte position) next four-frame multiframe. 48-Frame SBI/SBI336 mode: sampled byte position incoming first frame 48-frame multiframe. Changes connection memory page selection synchronized frame boundary byte position) next 48-frame multiframe. TelecomBus mode: sampled byte position every frame incoming bus. Changes connection memory pate selection synchronized frame boundary byte position) next frame. sampled rising edge SYSCLK RC1FP frame position.
RSTB
Input
Reset Enable Bar. active reset signal (RSTB) provides asynchronous reset NSE. RSTB Schmitt triggered input with integral pull-up resistor
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Name
Type
Input
AM30
Function
Chip Select Bar. active chip select signal (CSB) controls microprocessor access registers NSE20G device. during NSE-20G Microprocessor Interface Port register accesses. high disable microprocessor accesses. required (i.e. register accesses controlled using signals only), should connected inverted version RSTB input.
Microprocessor Interface Balls)
Input
AM29
Read Enable Bar. active read enable signal (RDB) controls microprocessor read accesses registers NSE-20G device. also during NSE-20G Microprocessor Interface Port register read accesses. NSE-20G drives D[31:0] with contents addressed register while low. Write Enable Bar. active write enable signal (WRB) controls microprocessor write accesses registers NSE-20G device. also during NSE-20G Microprocessor Interface Port register write accesses. contents D[31:0] clocked into addressed register rising edge while low.
Input
AN29
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Name
D[31] D[30] D[29] D[28] D[27] D[26] D[25] D[24] D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[16] D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[11 A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A{0]
Type
AM24 AN23 AM23 AN22 AL22 AN21 AM21 AP20 AP19 AN19 AM19 AM18 AN18 AP18 AL17 AN17 AM16 AN16 AL15 AN15 AL14 AM14 AM13 AL13 AM12 AN12 AL11 AN11 AL10 AM10
Function
Microprocessor Data Bus. bi-directional data bus, D[31:0] used during NSE-20G Microprocessor Interface Port register reads write accesses. D[31] most significant data words D[0] least significant bit.
Input
AP28 AN27 AM27 AP26 AN26 AL26 AM26 AN25 AM25 AL25 AP24 AN24
Microprocessor Address Bus. microprocessor address (A[11:0]) selects specific Microprocessor Interface Port registers during NSE-20G register accesses.
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Name
Type
Input
AL30
Function
Address Latch Enable. address latch enable signal (ALE) active high latches address (A[11:0]) when low. internal address latches transparent when high. allows NSE-20G interface multiplexed address/data bus. integral pull resistor. Interrupt Request Bar. active interrupt enable signal (INTB) output goes when NSE-20G interrupt source active that source unmasked. INTB returns high when interrupt acknowledged appropriate register access. INTB open drain output. Test Clock. JTAG test clock signal (TCK) provides timing test operations that carried using IEEE P1149.1 test access port. Test Mode Select. JTAG test mode select signal (TMS) controls test operations that carried using IEEE P1149.1 test access port. sampled rising edge TCK. integral pull-up resistor. Test Data Input. JTAG test data input signal (TDI) carries test data into NSE-20G IEEE P1149.1 test access port. sampled rising edge TCK. integral pull-up resistor. Test Data Output. TheJTAG test data output signal (TDO) carries test data NSE-20G IEEE P1149.1 test access port. updated falling edge TCK. tri-state output which inactive except when scanning data progress. Test Reset Bar. active JTAG test reset signal (TRSTB) provides asynchronous NSE-20G test access port reset IEEE P1149.1 test access port. TRSTB Schmitt triggered input with integral pullup resistor. Note that when TRSTB being used, must connected RSTB input.
INTB
Open Drain Output
AN30
JTAG Port Balls) Input
Input
Input
Tri-state
TRSTB
Input
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Name
Reserved Reserved
Type
Input
Function
These pins reserved. Must left floating (internally pulled up.)
External Resistors Balls) RES[2] RES[1] Analog Input Reference Resistor Connection. off-chip 3.16 resistor connected between these positive resistor reference Kelvin ground contact RESK. on-chip negative feedback path will force 1.20 VREF voltage onto RES, therefore forcing current flow through resistor.
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Name
RESK[2] RESK[1]
Type
Analog Input
Function
Reference Resistor Connection. off-chip 3.16 resistor connected between these positive resistor reference Kelvin ground contact RESK. on-chip negative feedback path will force 1.20 VREF voltage onto RES, therefore forcing current flow through resistor. Analog test validation testing. This must grounded.
Analog Test Balls) ATB0[2] ATB0[1] ATB1[2] ATB1[1] Analog Analog AK32 AJ31 This must grounded. Analog test validation testing.
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Name
VDDI[44:0]
Type
Power
AN10 AN13 AP13 AP15 AM15 AM17 AL18 AM20 AL21 AM22 AL24 AM28 AL28 AG32 AE31 AD31 AA31
Function
digital core power pins (VDDI[44:0]) should connected well-decoupled +1.8 supply.
Digital Core Power Balls)
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Name
VDDI[44:0]
Type
Power
Function
Digital Power Balls) VDDO[33:0] Power AL12 AL16 AL23 AL27 AL31 AM31 AM32 AN31 AN32 AN33 digital power pins (VDDO[33:0]) should connected well-decoupled +3.3 supply.
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Name
VDDO[33:0]
Type
Power
Function
Digital Ground Balls) [71:0] Ground AP10 AP12 AP14 AP16 AP21 AP23 digital ground pins (VSS [71:0]) should connected GND.
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Name
[71:0]
Type
Ground
AP25 AP27 AP29 AP31 AP32 AP33 AP34 AA34 AC34 AE34 AG34 AJ34 AL34 AM34 AN34
Function
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Name
Analog Power Balls) AVDL[7:0]
Type
Power
AD32
Function
analog power pins (AVDL[7:0]) should connected well-decoupled +1.8 supply. These pins supply RXLVs.
Clock Synthesis Power Balls) CSU_AVDL[5:0] Power Clock Synthesis Power Balls) CSU_AVDH[0:1] Power These pins should connected well-decoupled +3.3 supply. clock synthesis pins (CSU_AVDL[5:0]) should connected well-decoupled +1.8 supply. These pins supply CSUs.
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Name
AVDH[33:0]
Type
Power
AG31 AC31 AK31 AK33 AK34 AL32 AL33 AM33
Function
analog power pins (AVDH[33:0]) should connected well-decoupled +3.3 supply.
Analog Power Balls)
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Name
Connect Balls) NC[49:0]
Type
AG33 AP30 AL29 AN28 AP22 AN20 AL20 AL19 AP17 AN14 AM11 AP11
Function
Connect pins (NC[49:0]) should left floating.
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Name
Type
Function
TOTAL Notes Description
NSE-20G inputs bi-directional balls except LVDS links present minimum capacitive loading operate logic levels. Inputs RSTB, ALE, TMS, TRSTB have internal pull-up resistors. outputs have minimum drive capability this includes TDO, INTB D[31:0]). VDDI AVDL power pins internally connected each other. Failure connect these pins externally cause malfunction damage device. AVDH, CSU_AVDH VDDO power pins internally connected each other. Failure connect these pins externally cause malfunction damage device. VDDI, VDDO, AVDH, CSU_AVDH AVDL power pins share common ground VSS. prevent damage device ensure proper operation, power must applied simultaneously power pins followed power power pins followed input pins driven signals. prevent damage device, power must first removed from input pins followed removal power from power supply pins followed simultaneous removal power from power pins. supplies should never less than supplies time during power-up power-down.
Analog Power Filtering Recommendations
achieve best performance LVDS links, analog filter network should installed between power balls supply.
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Table Analog Power Filters
AVDH balls) AVDL balls) AVDH AVDL Note power-gnd pairs same filter. balls) balls) 0.47
Notes
Filter network ball. Filter network ball. balls filter network Filter network ball.
Figure Analog Power Filter Circuit
Supply Device
Supply
Device
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Functional Description
LVDS Overview
LVDS family cells allow implementation 777.6 Mbit/s LVDS links. reference clock 77.76 required. generic LVDS link according IEEE 1596.3-1996 illustrated Figure below. transmitter drives differential signal through pair characteristic interconnects, such board traces, backplane traces, short lengths cable. receiver presents differential termination impedance terminate lines. Included standard sufficient common-mode range receiver accommodate much common-mode ground difference.
Figure Generic LVDS Link Block Diagram
Transmitter
Interconnect Zo=50
Receiver
Zo=50
Complete Serializer/Deserializer (SERDES) transceiver functionality provided. Ten-bit parallel data sampled line rate divided-by-10 clock (77.76 SYSCLK) then serialized line rate LVDS output pins 777.6 clock synthesized from SYSCLK. Serial line rate LVDS data sampled de-serialized 10-bit parallel data. Parallel output transfers synchronized gated line rate divided-by-10 clock. 10-bit data passed 8B/10B decoding block. gating duty cycle adjusted such that throughput parallel interface equals receive input data rate (Line Rate ppm). expected that clock source transmitter same clock source receiver ensure data throughput both ends link identical. Data guaranteed contain sufficient transition density allow reliable operation data recovery units 8B/10B block coding decoding provided T8TE R8TD blocks. system level, reliable operation will obtained proper signal integrity maintained through signal path receiver requirements respected. Namely, worst case opening 0.7UI differential amplitude needed. These conditions should achievable with system architecture consisting board traces, sets backplane connectors, backplane interconnect. This assumes proper design differential lines minimization discontinuities signal path. power constraints, output differential amplitude approximately
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LVDS system comprised LVDS Receiver (RXLV), LVDS Transmitter (TXLV), Transmitter reference (TXREF), data recovery unit (DRU), parallel serial converter (PISO Clock Synthesis Unit (CSU).
9.1.1
LVDS Receiver (RXLV)
RXLV block 777.6 Mbit/s Voltage Differential Signaling (LVDS) Receiver according IEEE 1596.3-1996 LVDS Specification. RXLV block receiver Figure accepting 777.6 Mbit/s LVDS signals from transmitter, over RP[X]/RN[X] pins, amplifying them converting them digital signals, then passing them data recovery unit (DRU). Holding IEEE 1596.3-1996 specification, RXLV differential input sensitivity better than includes least hysteresis. There RXLV blocks NSE.
9.1.2
LVDS Transmitter (TXLV)
TXLV block 777.6 Mbit/s voltage Differential Signaling (LVDS) Transmitter according IEEE 1596.3-1996 LVDS Specification. TXLV accepts 777.6 Mbit/s differential data from "parallel-in, serial-out" (PISO) circuit then transmits data off-chip voltage differential signal TP[X]/TN[X] pins. TXLV uses reference current voltage from TXREF block control output differential voltage amplitude output common-mode voltage. There instances TXLV block NSE-20G.
9.1.3
LVDS Transmit Reference (TXREF)
TXREF provides on-chip bandgap voltage reference (1.20 ±5%) precision current TXLV (777.6 Mbit/s LVDS Transmitter) block's. reference voltage used control common-mode level TXLV output, while reference current used control output amplitude. precision currents generated forcing reference voltage across external, off-chip 3.16 k(±1%) resistor. resulting current then mirrored through several individual reference current outputs, each TXLV receives reference current. There instances TXREF NSE-20G.
9.1.4
Data Recovery Unit (DRU)
fully integrated data recovery serial parallel converter that used 777.6 Mbit/s data. 8B/10B block code used guarantee transition density optimal performance.
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recovers data outputs ten-bit word synchronized with line rate divided ten, gated clock allow frequency deviations between data source local oscillator. output clock recovered clock. accumulates data bits outputs them next clock edge. 10-bits available transfer given clock cycle, output clock gated. provides moderate high frequency jitter tolerance suitable inter-chip serial link applications. support frequency deviations ±100ppm. There instances NSE-20G.
9.1.5
Parallel Serial Converter (PISO)
PISO parallel-to-serial converter designed high-speed transmit operation, supporting 777.6 Mbit/s. There instances PISO NSE-20G.
9.1.6
Clock Synthesis Unit (CSU)
fully integrated clock synthesis unit. generates jitter multi-phase differential clocks 777.6 transmitter. There instances NSE-20G.
Receive 8B/10B Frame Aligner (R8TD)
Receive 8B/10B serial SBI336S frame aligner, R8TD, frames receive stream find 8B/10B character boundaries. also contains FIFO bridge between timing domain receive LVDS links system clock timing domain. R8TD blocks perform framing elastic store functions data retrieved from receive LVDS links, RP[x]/RN[x].
9.2.1
FIFO Buffer
FIFO buffer sub-block provides isolation between timing domains associated receive LVDS link that system clock, SYSCLK. Data with arbitrary alignment 8B/10B characters, written into 10-bit 24-word deep FIFO link clock rate. Data read from FIFO every SYSCLK cycle.
Transmit 8B/10B Encoder (T8TE)
Transmit 8B/10B Encoder blocks, T8TE, construct 8B/10B character stream from incoming translated SBI336 TelecomBus carrying STS-12/STM-4 equivalent channelized stream. T8TE block corrects running disparity 8B/10B character stream buffers data FIFO before transmission transmit serializer block. total T8TE blocks instantiated NSE-20G device.
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mode, these blocks encode SBI336S stream shown Table When configured Synchronous mode switching, 8B/10B encoder transmits signaling multiframe alignment across SBI336S interface generating C1FP character every frame times. When configured switching, C1FP character sent every four frames.
9.3.1
SBI336S 8B/10B Character Encoding
Table shows mapping SBI336S control bytes signals into 8B/10B control characters. linkrate octet location in-band programming channel, octet when contains data carried data. Justification requests master timing carried character there three characters used: nominal, negative timing adjustment request, positive timing adjustment request.
Table SBI336S Character Encoding Code Group Name
K28.5 K23.7-
Curr. RDabcdei fghj
001111 1010 111010 1000
Curr. abcdei fghj
110000 0101
Encoded Signals Description
IC1FP='b1 C1FP frame multiframe alignment Overhead Bytes (columns 1-60 1-72 except in-band programming channel), byte except during negative justification, byte after byte during positive justification, unused bytes fraction rate links byte, justification request byte, negative justification request byte, positive justification request byte byte, justification request byte, negative justification request* byte, positive justification request* byte, send extra byte request** byte, send less byte request** byte IV5=1, IDATA[0,4] ERDI[1:0] `b00, IDATA[5] byte IV5=1, IDATA[0,4] ERDI[1:0] `b00, IDATA[5]
Common Link Types
Asynchronous T1/E1 Links Rate Links K28.7K29.7K27.7001111 1000 101110 1000 110110 1000 110110 1000 001111 1000 101110 1000 110110 1000 110110 1000 001111 1000 101110 1000
Synchronous T1/E1 Links Asynchronous DS3/E3 Links
Floating Transparent Virtual Tributaries
K27.7+
001001 0111
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Code Group Name
K28.7-
Curr. RDabcdei fghj
001111 1000
Curr. abcdei fghj
Encoded Signals Description
byte IV5=1, IDATA[0,4] ERDI[1:0] `b01, IDATA[5] byte IV5=1, IDATA[0,4] ERDI[1:0] `b01, IDATA[5] byte IV5=1, IDATA[0,4] ERDI[1:0] `b10, IDATA[5] byte IV5=1, IDATA[0,4] ERDI[1:0] `b10, IDATA[5] byte IV5=1, IDATA[0,4] ERDI[1:0] `b11, IDATA[5] byte IV5=1, IDATA[0,4] ERDI[1:0] `b11, IDATA[5]
K28.7+
110000 0111
K29.7-
101110 1000
K29.7+
010001 0111
K30.7-
011110 1000
K30.7+
100001 0111
Note there multiple frame when mode only justification occur frame. Positive negative justification request through required SBI336S interface should limited frame. Note fractional rate links symmetric transmit receive direction over SBI336S. When using clock slave mode with fractional rate link clock master makes single byte adjustments slaves rate once frame.
9.3.2
Serial TelecomBus 8B/10B Character Encoding
Table shows mapping TelecomBus control bytes signals into 8B/10B control characters. When TelecomBus control signals conflict each other, 8B/10B control characters generated according sequence table, with characters table taking precedence over those lower table.
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Table Serial TelecomBus Character Encoding Code Group Name
K28.5
Curr. RDabcdei fghj
001111 1010
Curr. abcdei fghj
110000 0101
Encoded Signals Description
IC1FP='b1 IPL='b0 C1FP frame multiframe alignment IPL='b0 High-order path byte position, negative justification event.
High Order Path Termination (HPT) Mode
K28.0-
001111 0100
K28.0+
110000 1011
IPL='b0 High-order path byte position, positive justification event.
K28.6
001111 0110
110000 1001
IC1FP='b1, IPL='b1 High-order path frame alignment (J1).
Order Path Termination (LPT) Mode K28.4+ K27.7110110 1000 110000 1101 ITAIS='b1 Low-order path AIS. IV5='b1, IDATA[0,4] ERDI[1:0] `b00, IDATA[5] order path frame alignment. ERDI encoded byte. K27.7+ 001001 0111 IV5='b1, IDATA[0,4] ERDI[1:0] `b00, IDATA[5] order path frame alignment. ERDI encoded byte. K28.7001111 1000 IV5='b1, IDATA[0,4] ERDI[1:0] `b01, IDATA[5] order path frame alignment. ERDI encoded byte. K28.7+ 110000 0111 IV5='b1, IDATA[0,4] ERDI[1:0] `b01, IDATA[5] order path frame alignment. ERDI encoded byte. K29.7101110 1000 IV5='b1, IDATA[0,4] ERDI[1:0] `b10, IDATA[5] order path frame alignment. ERDI encoded byte. K29.7+ 010001 0111 IV5='b1, IDATA[0,4] ERDI[1:0] `b10, IDATA[5] order path frame alignment. ERDI encoded byte. K30.7011110 1000 IV5='b1, IDATA[0,4] ERDI[1:0] `b11, IDATA[5] order path frame alignment. ERDI encoded byte.
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Code Group Name
K30.7+
Curr. RDabcdei fghj
Curr. abcdei fghj
100001 0111
Encoded Signals Description
IV5='b1, IDATA[0,4] ERDI[1:0] `b11, IDATA[5] order path frame alignment. ERDI encoded byte.
K23.7-
111010 1000
000101 0111
ITPL='b0 low-order path payload bytes.
9.3.3
Serial SBI336S TelecomBus Alignment
alignment functionality preformed each receiver broken down into parts, character alignment frame alignment. Character alignment finds 8B/10B character boundary arbitrarily aligned incoming data. Frame alignment finds SBI336S TelecomBus frame multiframe boundaries within Serial link. character frame alignment expected robust enough operation over cabled interconnect.
9.3.4
Character Alignment Block
Character alignment locates character boundaries incoming 8B/10B data stream. character alignment algorithm states, in-character-alignment state outof-character-alignment state. states character alignment algorithm shown Figure When character alignment state machine out-of-character-alignment state, maintains current alignment, while searching C1FP character. finds C1FP character will re-align C1FP character move in-character-alignment state. C1FP character found searching 8B/10B C1FP character, K28.5+ K28.5-, simultaneously possible locations. While in-character-alignment state, state machine monitors LCVs. more LCVs detected within character window character alignment state machine transitions out-of-character-alignment state. special characters listed Table Table ignored purposes. Upon return incharacter-alignment state count cleared.
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Figure Character Alignment State Machine
5-in-15 LCVs
out-ofcharacteralignment
incharacteralignment
Found C1FP Character
9.3.5
Frame Alignment
Frame alignment locates TelecomBus frame multiframe boundaries incoming 8B/10B data stream. frame alignment state machine states, in-framealignment state out-of-frame-alignment state. Each SBI336S frame duration. mode: Encoded over SBI336S frame alignment SBI336S multiframe alignment which every four SBI336S frames When carrying traffic synchronous mode, signaling multiframe alignment also necessary also encoded over SBI336S alignment. Signaling multiframe alignment every frames links every frames links, therefore signaling multiframe alignment covering both multiframe alignment every SBI336S frames Therefore C1FP characters sent every four every frames. TelecomBus mode: Encoded over serial link tributary multiframe alignment, which every four frames Multiframe alignment required that downstream device extract data from tributary. multiframe information preserved only sending C1FP characters every four frames.
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frame alignment state machine establishes frame alignment over link based frame multiframe alignments. When frame alignment state machine outof-frame-alignment state, maintains current alignment, while searching C1FP character. When finds C1FP character state machine transitions in-framealignment state. While in-frame-alignment state, state machine monitors out-of-place C1FP characters. Out-of-place C1FP characters identified maintaining frame counter based C1FP character. counter initialized C1FP character when out-ofcharacter-alignment state, unaffected in-character-alignment state. three consecutive C1FPs have been found that agree with expected location defined frame counter, state will change out-of-frame-alignment state. frame alignment state machine also sensitive character alignment. When character alignment state machine out-of-character-alignment state, frame alignment state machine forced out-of-alignment, held that state until character alignment state machine transitions in-character alignment state.
Figure Frame Alignment State Machine
consecutive out-of-place C1FPs out-of-character alignment
out-offramealignment
in-framealignment
Found C1FP (out-of-character alignment)
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9.3.6
SBI336S Multiframe Alignment
SBI336S multiframe alignment communicated across link controlling frequency C1FP character. most frequent transmission C1FP character every four SBI336S frame times. This SBI336S multiframe used when there synchronous tributaries requiring signalling multiframe alignment SBI336S bus. When there synchronous tributaries SBI336S C1FP character transmitted every frame times. This signaling multiframe lowest common multiple frame multiframe frame multiframe. SBI336S multiframe signaling multiframe alignment based free running multiframe counter that reset with each C1FP character received. Under normal operating conditions each received C1FP character will coincide with free running multiframe counter. SBI336S multiframe alignment always required, SBI336S signaling multiframe alignment optional only required when synchronous tributaries supported with level switching.
Cross switch (DCB)
Each R8TD blocks provides eight-bit data signal each 77.76 clock edge. These signals STS-12 frame aligned ingress octets. Likewise, each egress T8TE blocks expects receive STS-12 frame aligned signal each clock edge. Cross switch (DCB) connects these inputs these outputs. constitutes Space switch that connects each output some input during each clock period STS-12 frame structure. STS-12 frame structure consists 12*9*90 9720 octets overheads payload). Being granularity space switch, must provide separate switch settings each these 9720 octet times. These 9720 switch settings stored on-chip SRAM. Each egress ports must told which each thirty-two ingress ports should read during each 9720 clock periods. Five bits required specify which ingress port should read each output. Thus, require 9720 words five bits each thirty-two egress ports. Thus each clock period requires bits. support controlled switchover from switch settings another, require banks 9720 words each. aggregate memory requirement 9720 160b 3,110,400b SRAM. table below illustrates mapping this memory. Each control page table vector bits containing five bits (specifying source port) each egress ports. page will on-line translating ports core switch while other offline update. When configuration ready, appropriate system synchronized frame boundary arrives, pages will swapped.
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Table Switching Control layout Control Page Address
Control Page
9719
multiplexers that select inputs each egress port straight forward 32-to-1 multiplexers. They require five bits control during each 77.76 clock cycle. Their outputs T8TEs. This design permits unicast, multicast, broadcast.
Clock Synthesis Transmit Reference Digital Wrapper (CSTR)
CSTR contains configuration registers TXREF LVDS analog locks.
Fabric Latency
flow octets from ingress LVDS egress LVDS variable latency, depending timing arriving LVDS stream, clock variation egress LVDS drivers. reasonable estimate NSE's latency arrived making assumptions about depths receive transmit FIFOs: assume "C1" timing maintain about four samples ingress FIFO; egress FIFO designed centered four samples typically delay FIFOs will eight clock cycles. latency through space switch stage three clock cycles. Data latency through analog blocks around typical latency NSE-20G clock cycles With worst case conditions both FIFOs, latency rises clock cycles
JTAG Support
NSE-20G provides JTAG support testing device interconnection board.
Microprocessor Interface
Microprocessor Interface Block provides logic required interface normal mode test mode registers within NSE-20G generic microprocessor bus. normal mode registers used during normal operation configure monitor NSE. register accessed shown Register Memory table below. Addresses that shown used must treated Reserved.
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In-band Link Controller (ILC)
order permit centralized control distributed NSE/SBS fabrics from NSE-20G microprocessor interface (for applications which NSEs located fabric cards, SBSs located multiple line cards), in-band signaling channel provided between NSE20G over Serial SBI336S interface. Each NSE-20G control SBSs that attached LVDS links. NSE-SBS in-band channel full duplex, NSE20G active control link. in-band channel carried first columns four rows structure, rows overall in-band channel capacity thus 36*4*64 Kbit/s 9.216 Mbit/s. Each bytes allocated in-band signaling channel in-band message between points. Four bytes each byte inband message reserved end-to-end control information error protection, leaving 8.192 Mbit/s available data transfer between points. data transferred between points fixed format, effectively providing clear channel packet transfer between attached microprocessors each LVDS link terminating devices. user able send receive packet bytes length. last reserved bytes byte in-band message CRC-16 which detects errors message. This block provides microprocessor interface in-band signaling channel. This in-band channel expected used almost entirely carry switching control changes SBSs. configure device most often requires local microprocessor write memory location consisting 16-bit address 16-bit data. Using this baseline assuming efficient in-band channel bandwidth maximum (32bytes/row rows/frame 8000 frames/sec bytes/write) 256,000 configurations second. Considering that configuring when switching DS0s requires writes indicates that in-band signaling channel bandwidth sets maximum limit over 9000 configurations second. real life these limits will achieved this shows that in-band link should bottleneck. TelecomBus mode this same configuration will require only three writes link. Another more efficient communication scheme could used increase this performance. protected architectures likely that full configuration port card will necessary during switchover. This would require entire connection memory reconfigured. Assuming connections overhead bytes also reconfigured, fastest that complete reconfiguration take place 9720 register writes each configuration pages SBS. This equates 9720 writes bytes/write bytes/row rows/frame 8000 frames/second)) milliseconds. also possible that spare card could hold connection configurations port cards protecting locally, even faster switch over.
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9.9.1
In-Band Signaling Channel Fixed Overhead
In-Band Link Controller block generates terminates bytes fixed header CRC-16 every byte in-band message (total bytes). byte header provides control status between devices ends LVDS link. CRC-16 calculated over byte (and header bytes) in-band message provides terminating ability detect errors in-band message. format in-band message header bytes shown Figure Figure
Figure In-Band Signaling Channel Message Format
byte Header1 byte Header2 bytes Free Format Information bytes CRC-16
Figure In-Band Signaling Channel Header Format
Header1 VALID LINK[1:0] Bit4 PAGE[1:0] Bit3 Bit2 USER[2:0] Bit1
Header2 AUX[7:0] Bit4 Bit3 Bit2 Bit1
Table In-band Message Header Fields
Field Name Valid NSE-20G Message slot contains message(1) empty(0). empty this message will into Message FIFO (other header information processed usual) These bits optional SBI336S devices, intended devices which have multiple redundant links. Each either indicates which Link use, Working(0) Protect(1) when sourced from master device, which link being used, when sourced from slave device. Other algorithms possible indicate Working Protect over these bits SBI336S devices must able revert back this meaning. Transmitted immediately. Message slot contains message(1) empty(0). empty this message will into Message FIFO (other header information processed usual) These bits optional SBI336S devices, intended devices which have multiple redundant links. Each either indicates which Link use, Working(0) Protect(1) when sourced from master device, which link being used, when sourced from slave device. Other algorithms possible indicate Working Protect over these bits SBI336S devices must able revert back this meaning. Transmitted immediately.
Link[1:0]#
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Field Name Page[1:0]#
NSE-20G Each indicates which control page use, page bits, ingress egress MSU. Only transmitted from beginning first message frame
Each shows current control page use, page bits, ingress egress MSU. Only transmitted from beginning first message frame. User defined register indication NSE-20G from external hardware inputs SBS. Transmitted immediately. User defined auxiliary register indication NSE. Transmitted immediately.
User[2:0]#
User defined register indication reflected external hardware signal outputs. Transmitted immediately. User defined auxiliary register indication SBS. Transmitted immediately.
Aux[7:0]#
Change these bits(received side) will processed received message CRC-16 indicates error. Interrupts generated when errors detected USER LINK bits change state. There inherent flow control provided In-Band Link Controller. attached microprocessor able provide flow control interrupts when in-band message FIFO overflows USER Auxiliary bits header. each message arrives, CRC-16 valid checked; valid message discarded, fails check flagged being error interrupt generated enabled. CRC-16 regardless valid bit, Page Link, User bits passed immediately. fifo erroneously overflows, interrupt generated.
9.10
Microprocessor Interface
following register shows registers used provide control NSE. first 100h addresses provide access level NSE-20G configuration control registers, Clock synthesis units through CSTR blocks Crossbar (DCB) space switch core NSE. From 100h identical, spaces used control ports NSE-20G individual basis. Each port In-Band Link Controller (ILC), 8B/10B encoder (T8TE) 8B/10B decoder (R8TD). These blocks provide functions specific ports such Line Code Violation counts (for data integrity monitoring) receive transmit in-band link message buffers. Table shows registers. Only port fully described other ports identical, being incrementally distributed from address 100h steps.
Table NSE-20G Register Address
Register
NSE-20G Master Reset NSE-20G Individual Channel Reset NSE-20G Master JTAG Page select Page Page select Page
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Address
01C-01F 027-03F
Register
NSE-20G Master Interrupt Source NSE-20G Master Interrupt Source NSE-20G Master R8TD Interrupt Source NSE-20G Master T8TE Interrupt Source NSE-20G Master Clock Monitor NSE-20G select NSE-20G Master Interrupt Enable NSE-20G Subsystem Interrupt Enable NSE-20G R8TD User Bits User Bits User Bits NSE-20G FREE User Register R8TD_RX_C1 Pulse Monitor Register Unexpected R8TD_RX_ Interrupt Register Missing R8TD_RX_ Interrupt Register Unexpected R8TD_RX_ Interrupt Enable Register Missing R8TD_RX_ Interrupt Enable Register RSTD Reserved CSTR Control CSTR Interrupt Enable Lock Status CSTR Interrupt Indication Reserved CSTR Control CSTR Configuration Status CSTR Interrupt Status Reserved CONFIGURATION PORT 31-30 REGISTER CONFIGURATION PORT 29-24 REGISTER CONFIGURATION PORT 23-18 REGISTER CONFIGURATION PORT 17-12 REGISTER CONFIGURATION PORT 11-6 REGISTER CONFIGURATION PORT REGISTER CONFIGURATION OUTPUT REGISTER ACCESS MODE REGISTER DELAY (RC1FP) REGISTER FRAME SIZE REGISTER CONFIGURATION REGISTER INTERRUPT REGISTER
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Address
Register
Reserved
100-1FF 0106 118-11F 120-13F 140-15F 160-17F 180-19F 1A0-1BF 1C0-1DF 1E0-1FF 200-21F 220-23F 240-25F 260-27F 280-29F 2A0-2BF 2C0-2DF 2E0-2FF
Port Register Port (Channel Port Register R8TD Control Status Port Register R8TD Interrupt Status Port Register R8TD Count Port Register RXLV Control Port Register Reserved Port Register T8TE Control Status Port Register T8TE Interrupt Status Port Register T8TE Time-slot Configuration Port Register T8TE Time-slot Configuration Port Register T8TE Test Pattern Port Register TXLV PISO Control Port Register Reserved Port Register Transmit Message FIFO Data Port Register Transmit Control Port Register Transmit Status FIFO Synch Port Register Receive Message FIFO DATA Port Register Receive Control Port Register Receive Status FIFO Synch Port Register Interrupt enable Control Port Register Interrupt reason Register Reserved Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel
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Address
300-31F 320-33F 340-35F 360-37F 380-39F 3A0-3BF 3C0-3DF 3E0-3FF 400-41F 420-43F 440-45F 460-47F 480-49F 4A0-4BF 4C0-4DF 4E0-4FF 500-7FF
Register
Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Port Register Port (Channel Reserved
Reserved Test
Notes Register Memory register accesses, must low. Addresses that shown must treated Reserved.
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Normal Mode Register Description
Normal mode registers used configure monitor operation NSE. Normal mode registers opposed test mode registers) selected when A[11] low.
Notes Normal Mode Register Bits
Writing values into unused register bits effect. However, ensure software compatibility with future, feature-enhanced versions this product, unused register bits must written with logic zero. Reading back unused bits produce either logic logic zero; hence, unused register bits should masked software when read. configuration bits that written into also read back. This allows processor controlling determine programming state block. Writeable normal mode register bits cleared logic zero upon reset unless otherwise noted. Writing into read-only normal mode register locations does affect NSE-20G operation unless otherwise noted. registers above 100H, only port ports shown. Register addresses shown example 0100H N*20H, here port number between This done prevent unnecessary duplication otherwise identical register sets.
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Register 000H: NSE-20G Master Reset
29:0
Type
Function
DRESET ARESET Unused
Default
This register allows separate software reset digital analog circuitry NSE. ARESET ARESET allows analog circuitry NSE-20G reset under software control. ARESET logic one, NSE-20G analog circuitry held reset. ARESET must held logic least 100us ensure correct reset CSU. This self-clearing. Therefore, logic zero must written bring NSE-20G reset. Holding NSE-20G reset state places into power, analog stand-by mode. hardware reset clears ARESET bit, thus negating analog software reset. DRESET DRESET allows digital circuitry NSE-20G reset under software control. DRESET logic one, NSE-20G digital circuitry held reset. This self-clearing. Therefore, logic zero must written bring NSE-20G reset. Holding NSE-20G reset state places into power, digital stand-by mode. hardware reset clears DRESET bit, thus negating digital software reset.
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Register 001H: NSE-20G Individual Channel Reset
31:0
Type
Function
RESET[31:0]*
Default
This register allows power saving holding individual channels reset. RESET[n] RESET[n] allows channel circuitry NSE-20G reset under software control. RESET[n] logic one, NSE-20G channel circuitry particular channel held reset. RESET[n] does affect reset CSU. This selfclearing. Therefore, logic zero must written bring channel reset. Holding channel reset state places into power, analog stand-by mode. hardware reset software DRESET 000h sets RESET[n] bit.
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Register 002H: NSE-20G Master JTAG
31:28 27:12 11:0
Type
Function
ID[3:0] DEVID[15:0] JTAG Identification Code [MID[10:0] JID]
Default
8620h 0CDh
NSE-20G Master JTAG registers hold JTAG identification code device. device revision number device available through these registers. ID[3:0] bits read provide binary NSE-20G revision number. DEVID[15:0] DEVID bits read distinguish NSE-20G from other members NSE20G family devices. MID[10:0] bits provide manufacturer identity field JTAG identification code. JTAG identification code.
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Register 003H: Page select Page
31:0
Type
Function
Page0_SBS[31:0]*
Default
Page0_SBS[n] This will Page sent SBSn over In-Band channel where connected LVDS links numbered from
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Register 004H: Page select Page
31:0
Type
Function
Page1_SBS[31:0]*
Default
Page1_SBS[n] This will Page sent SBSn over In-Band channel where connected LVDS links numbered from
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Register 005H: NSE-20G Master Interrupt Source
31:8
Type
Function
Unused R8C1EXTRAINT R8C1MISSINT CSU2INT CSU1INT R8TDINT T8TEINT ILCINT DCBINT
Default
R8C1EXTRAINT R8C1EXTRAINT logic one, interrupt unexpected character R8TD_C1_INT blocks occurred. source R8C1EXTRAINT comes from Register 013h. R8C1MISSINT R8C1MISSINT logic one, interrupt missing characters R8TD_C1_INT blocks occurred. source R8C1MISSINT comes from Register 014h. CSU2INT CSU2INT logic one, interrupt been generated CSTR Interrupt register must read clear this interrupt. CSU1INT CSU1INT logic one, interrupt been generated CSTR Interrupt register must read clear this interrupt. R8TDINT R8TDINT logic one, interrupt been generated R8TD blocks. internal R8TD Interrupt register must read clear this interrupt. Which R8TD caused interrupt ascertained reading NSE-20G R8TD Interrupt Source Register.
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T8TEINT T8TEINT logic one, interrupt been generated T8TE blocks. internal T8TE Interrupt register must read clear this interrupt. Which T8TE caused interrupt ascertained reading NSE-20G T8TE Interrupt Source Register. ILCINT ILCINT logic one, interrupt been generated blocks. relevant Interrupt register must read clear this interrupt. Which caused interrupt ascertained reading NSE-20G Interrupt Source Register. DCBINT DCBINT logic one, interrupt been generated block. Interrupt register must read clear this interrupt.
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Register 006H: NSE-20G Master Interrupt Source
31:0
Type
Function
ILCINT[31:0]*
Default
ILCINT[n] ILCINT[n] logic one, interrupt been generated that block. relevant Interrupt register must read clear this interrupt.
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Register 007H: NSE-20G Master R8TD Interrupt Source
31:0
Type
Function
R8TDINT[31:0]*
Default
R8TDINT[n] R8TDINT[n] logic one, interrupt been generated that R8TD block. relevant R8TD Interrupt register must read clear this interrupt.
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Register 008H: NSE-20G Master T8TE Interrupt Source
31:0
Type
Function
T8TEINT[31:0]*
Default
T8TEINT[n] T8TEINT[n] logic one, interrupt been generated that T8TE block. relevant T8TE Interrupt register must read clear this interrupt
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Register 009H: NSE-20G Master Clock Monitor
31:2
Type
Function
Unused RC1FPA SYSCLKA
Default
When monitored clock signal makes high transition, corresponding register high. will remain high until this register read, which point bits this register cleared. lack transitions indicated corresponding register reading low. This register should read periodic intervals detect clock failures. SYSCLKA SYSCLK active (SYSCLKA) detects high transitions SYSCLK input. SYSCLKA high rising edge SYSCLK, when this register read. RC1FPA RC1FP active (RC1FPA) detects high transitions RC1FP input. RC1FPA high rising edge RC1FP, when this register read.
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Register 00AH: NSE-20G select
31:2
Type
Function
Unused CMP_SRC CMP_VAL
Default
connection memory page select signal (CMP) controls selection connection memory page NSE. When high, connection memory page selected. When low, connection memory page selected. Changes connection memory page selection synchronized boundary next C1FP multiframe. This Register controls software override pin. CMP_SRC This dictates whether sourced from software when from external when CMP_VAL CMP_VAL used provide signal when CMP_SRC other wise this ignored.
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Register 00BH: NSE-20G Interrupt Enable Register
31:1
Type
Function
Unused INTE
Default
This register allows disable enable NSE-20G interrupts with single write. INTE This bit, when `1', enables INTB NSE. When INTB held `1'.
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Register 00CH: NSE-20G Subsystem Interrupt Enable Register
31:6
Type
Function
Unused TOPINTE CSUINTE R8TDINTE T8TEINTE ILCINTE DCBINTE
Default
This register allows disable enable NSE-20G Subsystem interrupts with single write. TOPINTE This bit, when `1', enables generation interrupts from Top_level i.e. R8C1EXTRAINT R8C1MISSINT interrupts. When R8C1EXTRAINT R8C1MISSINT interrupts disabled CSUINTE This bit, when `1', enables generation interrupts from CSU1 CSU2 control. When CSU1 CSU2 control interrupts disabled R8TDINTE This bit, when `1', enables generation interrupts from R8TD blocks. When R8TD interrupts disabled T8TEINTE This bit, when `1', enables generation interrupts from T8TE blocks. When T8TE interrupts disabled ILCINTE This bit, when `1', enables generation interrupts from blocks. When interrupts disabled DCBINTE This bit, when `1', enables generation interrupts from block. When interrupts disabled
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Register 00DH: NSE-20G R8TD Rgister
31:1
Type
Function
Unused
Default
This register allows determine signals from R8TDs inactive indicating transfers progress. This bit, when `1', indicates more signals from each R8TDs active. result signals ORed together.
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Register 00EH: User
31:0
Type
Function
SBS_USER_0[31:0]
Default
SBS_USER_0[n] This will USER sent SBSn over In-Band channel where connected LVDS links numbered from
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Register 00FH: User
31:0
Type
Function
SBS_USER_1[31:0]
Default
SBS_USER_1[n] This will USER sent SBSn over In-Band channel where connected LVDS links numbered from
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Register 010H: User
31:0
Type
Function
SBS_USER_2[31:0]
Default
SBS_USER_2[n] This will USER sent SBSn over In-Band channel where connected LVDS links numbered from
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Register 011H: NSE-20G FREE User Register
31:8
Type
Function
Unused FREE[7:0]
Default
FREE[7:0] software register (FREE) holds whatever value written into Reset clears contents this register. This register impact operation NSE.
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Register 012H: Correct R8TD_RX_C1 Pulse Monitor
31:0
Type
Function
R8C1_OK_INT[31:0]
Default
R8C1_OK_INT[n] This will both oc1fp[n] r8_rx_c1[n] have occurred same time. Otherwise, will stay `0'. Read access will clear this bit. section 12.5 description proper this register.
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Register 013H: Unexpected R8TD_RX_C1 Interrupt
31:0
Type
Function
R8C1_EXTRA_INT[31:0]
Default
R8C1_EXTRA_INT[n] This will oc1fp[n] occurred time when r8_rx_c1[n] occurred. Otherwise, will stay `0'. Read access will clear this bit. section 12.5 description proper this register.
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Register 014H: Missing R8TD_RX_C1 Interrupt
31:0
Type
Function
R8C1_MISS_INT[31:0]
Default
R8C1_MISS_INT[n] This will r8_rx_c1[n] occurred time when oc1fp[n] occurred. Otherwise, will stay `0'. Read access will clear this bit. section 12.5 description proper this register.
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Register 015H: Unexpected R8TD_RX_C1 Interrupt Enable
31:0
Type
Function
R8C1_EXTRA_INTE[31:0]
Default
R8C1_EXTRA_INTE[n] R8C1_EXTRA_INTE[n] used enable/disable enable; disable) R8C1_EXTRA_INT[n] (defined 013h) cause interrupt. This channel basis.
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Register 016H: Missing R8TD_RX_C1 Interrupt Enable
31:0
Type
Function
R8C1_MISS_INTE[31:0]
Default
R8C1_MISS_INTE[n] R8C1_MISS_INTE[n] used enable/disable enable; disable) R8C1_MISS_INT[n] (defined 014h) cause interrupt. This channel* basis.
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Register 020H, 024H: CSTR Control*
31-16
Type
Function
Unused Reserved[11] Reserved[10] Reserved[9] Reserved[8] Reserved[7] Reserved[6] Reserved[5] Reserved[4] Reserved[3] Reserved[2] Reserved[1] CSU_ENB CSU_RSTB Unused Unused Reserved[0]
Default
This register provides reset control enable control CSTR blocks through Reserved[11:0] Reserved bits must indicated default value correct operation NSE. CSU_RSTB CSU_RSTB signal software reset signal that forces into reset. reset when CSU_RSTB logic zero. also reset NSE-20G master analog reset signal. When reset, reset signal should held least 100us. CSU_ENB enable control signal (CSU_ENB) forces into power configuration. disabled when CSU_ENB logic one. enabled when CSU_ENB logic zero.
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Register 021H, 025H: CSTR Interrupt Enable Lock Status
31-2
Type
Function
Unused LOCKV LOCKE
Default
This register configures operation CSTR blocks through #2*. LOCKE lock interrupt enable (LOCKE) controls contribution lock state interrupts CSTR device interrupt INTB. When LOCKE high, INTB asserted when lock state changes. Interrupts lock state masked when LOCKE low. LOCKV lock status (LOCKV) indicates whether clock synthesis unit successfully locked with system clock. LOCKV when successfully locked with reference clock. LOCKV high when locked with reference clock.
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Register 022H, 026H: CSTR Interrupt Indication
31-1
Type
Function
Unused LOCKI
Default
LOCKI lock interrupt status (LOCKI) reports acknowledges changes lock state. LOCKI high when achieves lock with reference clock loses lock reference clock. LOCKI cleared read this register when WCIMODE logic zero. LOCKI cleared write value) this register when WCIMODE logic one. INTB asserted when both LOCKE LOCKI high. LOCKE asserted, LOCKI must cleared before INTB will reasserted.
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Register 040H: Configuration port 31-30 Register (NSE-20G only)
31-10
Type
Function
Unused Port31[4:0] Port30[4:0]
Default
Port31[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port30[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame.
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Register 041H: Configuration port 29-24 Register (NSE-20G only)
31-30 29-25 24-20 19-15 14-10
Type
Function
Unused Port29[4:0] Port28[4:0] Port27[4:0] Port26[4:0] Port25[4:0] Port24[4:0]
Default
Port29[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port28[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port27[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port26[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port25[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port24[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame.
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Register 042H: Configuration port 23-18 Register (NSE-20G only)
31-30 29-25 24-20 19-15 14-10
Type
Function
Unused Port23[4:0] Port22[4:0] Port21[4:0] Port20[4:0] Port19[4:0] Port18[4:0]
Default
Port23[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port22[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port21[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port20[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port19[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port18[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame.
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Register 043H: Configuration port 17-12 Register
31-30 29-25 24-20 19-15 14-10
Type
Function
Unused Port17[4:0] Port16[4:0] Port15[4:0] Port14[4:0] Port13[4:0] Port12[4:0]
Default
Port17[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port16[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port15[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port14[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port13[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port12[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame.
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Register 044H: Configuration port 11-6 Register
31-30 29-25 24-20 19-15 14-10
Type
Function
Unused Port11[4:0] Port10[4:0] Port9[4:0] Port8[4:0] Port7[4:0] Port6[4:0]
Default
Port11[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port10[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port9[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port8[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port7[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port6[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame.
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Register 045H: Configuration port Register
31-30 29-25 24-20 19-15 14-10
Type
Function
Unused Port5[4:0] Port4[4:0] Port3[4:0] Port2[4:0] Port1[4:0] Port0[4:0]
Default
Port5[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port4[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port3[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port2[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port1[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame. Port0[4:0] This register selects input port number output port arbitrary position SBI336/TelecomBus frame.
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Register 046H: Configuration Output Register
31-30 29-0
Type
Function
Unused CFG_O[29:0]
Default
CFG_O[29:0] This field contains configuration data read from offline connection memory page. Configuration data this field read from location specified WORDADDR PORTADDR fields specified Access Mode register. There SYSCLK cycle latency from when indirect read requested until time when correct data appears this register.
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Register 047H: Access Mode Register
28-24 23-21 20-16 15-14 13-0
Type
Function
ACCMDE Unused PORTCFG[4:0] Unused PORTADDR[4:0] Unused WORDADDR [13:0]
Default
Writing this register with register high initiates indirect read from offline connection memory page. WORDADDR selects offline connection memory page read from. There latency SYSCLK cycles from when this register written with high until when valid data appears Configuration Output register. Indirect reads should spaced least SYSCLK cycles apart permit valid data appear Configuration Output register. Writing this register with register initiates indirect write offline connection memory page. WORDADDR selects offline connection memory page write Indirect writes should spaced least four SYSCLK cycles apart ensure writes complete successfully. While page copy progress (UPDATEV register `1'), writing this register will cause data updated to/from offline connection memory page. While page swap pending (SWAPV register `1'), writing this register cause unpredictable results data transferred while page swap occurring, causing data updated different connection memory page from intended. indirect access control selects between write read access offline connection memory page. ACCMDE These bits indicate access mode offline connection memory page. PORT transfer mode. WORD transfer mode. port transfer mode, port updated word offline connection memory page.
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PORTCFG: port mapping updated connection memory page. WORDADDR: specifies address offline connection memory page. PORTADDR: port address offline connection memory page. word transfer mode, entire word offline connection memory page updated. PORTCFG: ignored. WORDADDR: specifies address offline connection memory page. PORTADDR: ignored. either mode, contents read from off-line connection memory page read microprocessor through Configuration Output register. PORTCFG[4:0] This field contains input port mapping particular output port specified PORTADDR. Used only PORT transfer mode. other modes, this field ignored. PORTADDR[4:0] When performing writes offline connection memory page, this field indicates output port updated with mapping PORTCFG. PORTADDR relates output port DCB. This field valid PORT transfer mode during reading from Configuration Output register ignored WORD transfer mode. Valid values 0-31 when performing writes. When performing reads through Configuration Output register, PORTADDR indicates ports being read follows 000xx ports 001xx ports 11-6 010xx ports 17-12 011xx ports 23-18 100xx ports 29-24 101xx ports 31-30 least significant bits 110xx ports 111xx ports WORDADDR[13:0] This field indicates address update connection memory page accessed. This field relates time location within SBI/TelecomBus frame. I.e. Location would first byte frame location character. This field ignored page copy mode. Valid values 0-9719.
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Register 048H: delay (RC1DLY) Register
31-6 13-0
Type
Function
Unused RC1DLY[13:0]
Default
RC1DLY This value, .equaling delay 77.76 clock periods), between RC1FP arrival characters R8TD. This delay will synchronize input R8TD blocks assuming characters have arrived. delay those links dependent system design, backplane propagation delays, cable lengths etc. This value will have arrived empirically. will have upper lower limit which middle value should selected. Operations section more detail some recommended starting values. MF_SWAP Legal Range (clock cycles) 9716 16383 16383 16383
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Register 04AH: Frame size Register
31-14 13-0
Type
Function
Unused FRMSZ[13:0]
Default
9719
This register specifies frame size TelecomBus frame. FRMSZ[13:0] This register specifies size connection memory page various switching modes. Legal values 1079: 1079: 9719: 9719: TelecomBus switching. column switching. switching. switching with CAS.
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Register 04CH: Configuration Register
Type
Function
Unused MF_SWAP[1:0] AUTO SWAP_PE UPDATEE FRAMEE SWAPPV UPDATEV
Default
MF_SWAP [1:0] This selects when RC1FP expected synchronizes when page swaps occur. table below relates MFSWAP vital variables from DCB:
MFSWAP Config-uration Page Size Frame Switching (9720 byte frame)
frame frame frame frame
Frame Interrupt
RC1FP expected every
frame frame frame frame
Switching Mode
1080 1080 9720 9720
frame frame frame frame
TelecomBus column mode mode with
AUTO This enables automatic copy online connection memory page offline connection memory page after connection memory page switched. Toggling AUTO while page copy progress will terminate page copy process. automatic update disabled. automatic update enabled. automatic page copying used, page copy will take place automatically whenever connection memory page swaps. This means that UPDATEV register will asserted immediately following change from SWAPV register bit. When AUTO set, access offline connection memory page restricted from when page swap pending until when page copy complete.
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SWAP_PE This enables propagation interrupt output change state SWAPV. This does have impact SWAPI bit. disables interrupt propagation output. enables interrupt propagation output. UPDATEE This enables propagation interrupt output when UPDATEV changes state from This does have impact UPDATEI disables interrupt propagation output. enables interrupt propagation output. FRAMEE This enables propagation interrupt output when sampled expected RC1FP position. This does have impact FRAMEI bit. disables interrupt propagation output. enables interrupt propagation output. SWAPV SWAPV contains current state page swap. This logic when switch connection memory page (CMP) input been recognized page swap happened. This logic zero when page swap pending. When page swap pending, writing offline page initiating page copy cause corruption memory pages. UPDATEV This updated when active connection memory page copied offline connection memory page. copying completed. copying progress. duration page copy highly dependent MF_SWAP. MF_SWAP SYSCLK Clock cycles required "00" 1083
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"01" "10" "11"
1083 9723 9723
When page copy progress, attempting write offline connection memory page will ignored attempting read from offline connection memory page will return unpredictable results.
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Register 04DH: Interrupt status Register.
31-3
Type
Function
Unused SWAPI UPDATEI FRAMEI
Default
Writing this register initiates copying active connection memory page offline connection memory page. When page swap pending (SWAPV ='1') writing this register cause corruption connection memory pages. SWAPI This reports acknowledges change state SWAPV Configuration register. This cleared when this register read. When enabled SWAPE, output reflects state this bit. UPDATEI offline page copy interrupt status bit, UPDATEI reports acknowledges change state from UPDATEV Configuration register. This signifies that page copy complete. This cleared when read. When enabled UPDATEE bit, output reflects state this bit. FRAMEI frame interrupt status reports sampling expected RC1FP position. When enabled FRAMEE, frequency occurrence FRAMEI dependent MF_SWAP. When enabled FRAMEE bit, output reflects state this bit. MF_SWAP FRAMEI occurs every frame frame frame frame
This cleared when read. change input should sequenced occur soon possible after occurrence FRAMEI. Changing prior occurrence FRAMEI cause unpredictable behavior cause sampled later than expected.
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Register 100H N*20H: R8TD Control Status
31:16 13:10
Type
Function
Unused Reserved[1] Reserved[0] Unused RXINV Reserved FUOE LCVE OFAE OCAE OFAV OCAV FOFA FOCA
Default
This register provides control reports status R8TD blocks. FOCA force out-of-character-alignment (FOCA) control operation character alignment block R8TD block. transition this forces character alignment block out-of-character-alignment state where will search transport frame alignment character (K28.5). Before another force operation performed, FOCA must first logic zero. FOFA force out-of-frame-alignment (FOFA) controls operation frame alignment block R8TD block. transition this forces frame alignment block out-of-frame-alignment state where will search transport frame alignment character (K28.5). Before another force operation performed, FOFA must first logic zero. OCAV out-of-character-alignment status (OCAV) reports state character alignment block R8TD block. OCAV high when character alignment block outof-character-alignment state. OCAV when character alignment block in-character-alignment state.
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OFAV out-of-frame-alignment status (OFAV) reports state frame alignment block R8TD block. OFAV high when frame alignment block out-of-framealignment state. OFAV when frame alignment block in-framealignment state. OCAE character alignment interrupt enable (OCAE) masks contribution change character alignment event indication (OCAI) R8TD block INTB. When OCAE high, INTB asserted when OCAI high. INTB affected value OCAI when OCAE low. OFAE frame alignment interrupt enable (OFAE) masks contribution change frame alignment event indication (OFAI) R8TD block INTB. When OFAE high, INTB asserted when OFAI high. INTB affected value OFAI when OFAE low. LCVE line code violation interrupt enable (LCVE) masks contribution line code violation event indication (LCVI) R8TD block INTB. When LCVE high, INTB asserted when LCVI high. INTB affected value LCVI when LCVE low. FUOE FIFO underrun/overrun status interrrupt enable (FUOE) masks contribution FIFO underrun/overrun event indication (FUOI) R8TD block INTB. When FUOE high, INTB asserted when FUOI high. INTB affected value FUOI when FUOE low. RXINV receive data invert (RXINV) controls active polarity incoming data stream. When RXINV high, data complemented before processing R8TD. When RXINV low, data complemented before R8TD processing. Reserved[2:0] Reserved[1:0] bits must indicated default value correct operation NSE.
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Register 101H N*20H, R8TD Interrupt Status
31:8
Type
Function
Unused FUOI LCVI OFAI OCAI Unused
Default
These registers reports interrupt status change character alignment events detection line code violations R8TD block. OCAI out-of-character-alignment interrupt status (OCAI) reports acknowledges change character alignment state events R8TD block. OCAI high when character alignment block changes state out-of-character-alignment state in-characteralignment state since last clear register. OCAI cleared read this register when WCIMODE logic zero. OCAI cleared write value) this register when WCIMODE logic one. INTB asserted when both OCAE OCAI high. OCAE asserted, OCAI must cleared before INTB will reasserted. OFAI out-of-frame-alignment interrupt status (OFAI) reports acknowledges change frame alignment state events R8TD block. OFAI high when frame alignment block changes state out-of-frame-alignment state in-frame-alignment state. OFAI cleared read this register when WCIMODE logic zero. OFAI cleared write value) this register when WCIMODE logic one. INTB asserted when both OFAE OFAI high. OFAE asserted, OFAI must cleared before INTB will reasserted. LCVI line code violation event interrupt status (LCVI) reports acknowledges line code violation events R8TD block. LCVI high when character alignment block detects line code violation incoming data stream. LCVI cleared read this register when WCIMODE logic zero. LCVI cleared write value) this register when WCIMODE logic one. INTB asserted when both LCVE LCVI high. LCVE asserted, LCVI must cleared before INTB will reasserted.
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FUOI FIFO underrun/overrun event interrupt status (FUOI) reports acknowledges FIFO underrun/overrun events R8TD block. FUOI high when R8TD detects that FIFO read write pointers within slot each other. FUOI cleared read this register when WCIMODE logic zero. FUOI cleared write value) this register when WCIMODE logic one. INTB asserted when both FUOE FUOI high. FUOE asserted, FUOI must cleared before INTB will reasserted.
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Register 102H N*20H, R8TD Line Code Violation Count
31:16 15:0
Type
Function
Unused LCV[15:0]
Default
These registers reports number line code violations previous accumulation period R8TD blocks. LCV[15:0] LCV[15:0] bits reports number line code violations that have been detected since last time registers were polled. registers polled writing register writing this register. Within either event, internally accumulated error count transferred registers internal error coun
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