Section Introduction CLC3790093 Data Capture Board enables simple

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CLC-CAPT-PCASM Data Capture Board User's Guide
Section Introduction
CLC3790093 Data Capture Board enables simple evaluation National Semiconductor's High Speed Analog Digital Converters (ADCs) Diversity Receiver Chip (DRCS). Data Capture Board interfaces outputs these devices standard serial port available back most Personal Computers (PCs). have provided software control data capture function Matlab® scripts data analysis. block diagram evaluation test shown below. Data Capture Board contains field-programmable gate array (FPGA) that controls operation. EPROM configures FPGA after power applied. serial interface provided UART (Universal Asynchronous Receiver/Transmitter), oscillator, level translator captured data stored either three static RAMs (organized into 24-bit words) FIFO containing 18-bit words. LEDs provide visual indication activity. switches jumper configure several capture functions.
1999 1.0.0
CLC-CAPT-PCASM Data Capture Board User's Guide
Table Contents
Introduction Capturing Data from Evaluation Boards III. Capturing Data from DRCS Evaluation Boards Data Analysis using Matlab Script Files
Section Capturing Data from Evaluation Boards
Getting Started Data Capture board capture data from National Semiconductor Analog Digital converter, will need following hardware, software, documentation.
CLC5956 Evaluation Board
National Semiconductor High-Speed Converter Evaluation Test
CLC5958 Evaluation Board
Digital Receiver ChipSet (DRCS) Evaluation Board
1999 National Semiconductor Corporation
Printed U.S.A.
Data Capture Board
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FILTERED SIGNAL SOURCE OPTIONAL CLOCK SOURCE
(2A)
Optional Oscillator
Clock
10-16dBm
Data Capture Board
Data
Clock Source. wish test with fixed clock frequency, install standard oscillator socket provided evaluation board. Otherwise, will need provide phase noise sinewave square wave clock source appropriate connector evaluation board. amplitude 16dBm recommended. Here, again, 8644B good choice.
Software
Serial
Power
Evaluation Board
CONNECTOR Serial COMM PORT
Hardware
CLC3790093 Data Capture Board (CLC-CAPT-PCASM) Evaluation Board. Several products evaluated with this system. Currently, choices CLC5956 (12-bit 65MSPS ADC), CLC5958 (14-bit 52MSPS ADC). Each product unique evaluation board (CLC5956PCASM CLC5958PCASM) which plugs into data capture board. Personal Computer. IBM-Compatible running Windows® Windows® Windows® should have available serial port capable operating 115,200 baud. These ports usually labeled referred COM1 COM2. captured data stored file allow custom analysis. Serial Cable. standard serial interface cable provided. This cable connects data capture board Power Supply. data capture board requires single supply. This power applied connector 2-amp supply will provide enough current evaluation board data capture board. Note that power evaluation board provided from data capture board through 64-pin connector Input signal. provide type input signal that feel appropriate your system testing. data analysis software provided with data capture board oriented toward analysis single tone sinewave inputs. recommendation high purity, phase noise reference signal sources Hewlett Packard HP8644B synthesizer. provides excellent input stimulus evaluating performance. Bandpass lowpass filter. Even with good sinewave source, will need filter harmonics signal source. bandpass filter also enables filtering wideband noise reference source. example, Allen Avionics (Mineola, passive filters used most converter testing.
National Semiconductor Software. required software provided CD-ROM. install software now, insert CD-ROM into your computer follow directions. default installation copies files directory called "c:\nsc". data capture software called "capture.exe". Matlab. copy Matlab version later required operate analysis routines. simply wish capture data file your process data with your analysis software, then will need Matlab. more information about Matlab, please their website http:// www.mathworks.com. Matlab script files. Matlab script files data analysis located "c:\nsc\mfiles" directory. These script files from Matlab command prompt.
Documentation
CD-ROM includes following documentation, with most current versions available website http:// www.national.com: CLC5956 data sheet CLC5958 data sheet Data Capture Board User's guide (this document). Additional information included other products their evaluation boards. evaluating Diversity Receiver Chip Set, please refer Section this manual. Operation Data Capture Board When evaluating performance ADC, data capture board main modes operation. first mode, data captured from evaluation board under test full sample rate ADC. contiguous data samples captured into FIFO memory board, then this data moved over slower rate. data stored file hard drive later analysis. data stored ASCII file exactly format that output from converter. CLC5956, two's complement 12-Bit data stored numbers ranging from 4095. case 14-bit ADC5958, two's complement data ranges from 16383. Each value terminated with carriage return, hexadecimal Note that two's
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complement number converted offset binary inverting MSB. This first step Matlab routine analysis.
RDY2
FIFO 18-bits depth
UART
CLC5956 Data Analog Input Ain- Ain- AinAin AinCLC5958 Data Analog Input Ain- Ain- AinAin Ain-
Clock
Condition Full Scale Scale Scale Full Scale Condition Full Scale Scale Scale Full Scale Offset Binary Number 0000 0000 0000 0111 1111 1111 1000 0000 0000 1111 1111 1111 Offset Binary Number 0000 0000 0000 0111 1111 1111 0000 0000 0000 1111 1111 1111 Two's Complement 1000 0000 0000 1111 1111 1111 0000 0000 0000 1111 1111 1111 Two's Complement 0000 0000 0000 1111 1111 1111 0000 0000 0000 1111 1111 1111 ASCII Value Stored 2048 4095 2047 ASCII Value Stored 8192 16383 8191
WCLK
Data 12-18 Bits
FPGA
Serialized Data Stream SRAM 24-bits depth
9-pin Serial Cable Connector
FPGA Performs: State Machine Signal Format Conversion Data Routing
Note: Primary data path shown. Control lines shown
Eurocard Connector
Histogram Mode
second mode operation, "Histogram" mode, data capture board operates hardware histogrammer. board does collect contiguous record from ADC; instead, compiles statistical information counting number times that outputs each code. most significant bits converter define histogram bins. data inverted before being stored (all data treated offset binary format). data aligned least significant bit, unused higher bits Each cleared initially. output code used address SRAM board, each code read Data Capture board, data that location SRAM read, incremented written back SRAM. This counting requires multiple clock cycles, data counted real time. fact, samples data missed each sample that counted. histogram capture terminates when reaches count specified switches histogram counts then returned serial port. input signal pure sinusoid, then histogram information compared theoretical probability density sinusoid linearity calculated. supplied Matlab script DNL_INL uses this method. Please refer IEEE Standard Digitizing Waveform Recorders (IEEE 1057-1994) more information about this technique. Hardware Configuration
Jumpers
Data Capture Board Block Diagram
Switches
Five eight switches used configure several capture functions follows.
switch This switch specifies whether Diversity Receiver Evaluation Board Evaluation Board attached Data Capture Board. Evaluation Board attached. Captured data aligned least significant with unused higher bits switches When switch indicate that Evaluation Board attached, switches specify width data aligned least significant unused higher bits
Switch: Number Bits
data capture board jumpers that must configured before use. first jumper, VCORE, sets core voltage used FPGA. This jumper always voltage regulator board reduces supplied +3.3V FPGA other components board.) second jumper, WCLK, selects clock source FIFO. When capturing data from evaluation board, WCLK should always RDY2. This selects (Data Ready) clock line from evaluation board 20B. third jumper block, unused.
switches These switches specify maximum histogram count. histogram capture terminates when reaches count specified these switches.
Switch: Maximum Count 16384 8192 4096 2048
maximum count 16384 corresponds approximately million total samples 12-Bit ADC. capture very fast order second MSPS clock rate) there much advantage setting switches lower maximum count. other settings more useful DRCS evaluations because effective clock rate become very with certain output formats decimation ratios.
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Connectors
output clock connector provides signal that used phase lock signal source. frequency that input clock signal divided example, with attached CLC5958 evaluation board 52MSPS clock output signal will 26MHz square wave. second connector currently unused.
Serial Port
When capture.exe, will following window onto your
serial port configured 115,200 baud with stop bit, parity, 8-bits character. Although DSR, CTS, control signals connected, they used. XON/XOFF flow control supported. flow returned data pauses after XOFF character (DC3, ctrl-S, hexadecimal been received. flow returned data resumes after character (DC1, ctrl-Q, hexadecimal been received. Data Capture Board initializes character been received. Power System Once WCLK jumper switches have been set, (for example, CLC5956 have WCLK RDY2 switches 1,2,3,4,5 ON,ON,ON,OFF,OFF) connect evaluation board data capture board, apply power, clock, signal boards, connect serial cable Some will need rebooted this point, necessary with your software configuration section, next, will check communication between data capture board.
Light Emitting Diode (LED) Status Monitors
This data capture control panel. small conserve monitor area other programs. main function panel initiate data capture. Before capture data must configure computer board. clicking control panel with RIGHT mouse button (right click), bring following configuration menu:
first thing configure port computer, move mouse "Configure I/O" click with LEFT mouse button. This will bring following menu:
LEDs used provide status indications.
This connected address line static ICs. While static being written read, blinks. After Data Capture Board powered FPGA initialized, indicate that board ready. After SRAM data been output, off. This when captured data available output serial port. After data been output, off. This connected clock signal selected switch When clock toggling, will less than full intensity.
this point your setup, should have full intensity reduced intensity. ready configure software data capture. Software Configuration program "capture.exe". located directory that chose during CD-ROM installation. default directory "c:\nsc\". also start menu: start programs capture.
Select port that have attached data capture board, press "OK". computer will then send command data capture board. data capture board responds port interface operating correctly, "Configure I/O" menu will disappear, Data Capture control panel will return. there problem with port interface, will following message:
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Verify connections and, necessary, other port. (Note that must have clock applied Evaluation board during this communication verification stage. Check make sure that either external clock oscillator installed, that LED6 reduced intensity.) Once proper exit from this step, ready configure capture board. Right click capture control panel, then left click "Configure Capture." will following screen:
"Default" then "OK". have C:\temp directory, please make one. reason this that Matlab script files data analysis look automatically file C:\temp\data.dat. wish store data elsewhere, will need modify Matlab m-files look your data file different location. Obviously, using your software data analysis this concern.
Capture Data! finally ready capture data from ADC. final check, move mouse until progress (the data capture control panel that reads (0%). should little yellow appear that confirms your capture settings.
configure capture board direct capture contiguous point record output codes, click selections shown above. Left click "Capture Debug" select "Upper Bits." names these selections seem rather cryptic when simply capturing data. label names derived from functions DRCS CLC5902, they might seem context capture uses. Don't worry about label names, just make sure have selected modes shown above. Then click "OK." final configuration remains. need tell program where store your data. Right click capture control panel, then left click "Change Data File." will following menu:
Now, simply left-click "Start" button capture control panel start process. will light board, capture control panel will show progress data transfer. 52MSPS, 32768 samples collected only microseconds; rest time serial port transfer. Typical times this transfer order seconds. analyze data using Matlab Mfiles that have provided, please start Matlab this time. include provided script files your Matlab path, type following command Matlab command prompt:
path(path,'c:\nsc\mfiles')
Alternatively, change directories Matlab prompt until this current directory. From Matlab command prompt, type "analysis_menu". This will bring following menu:
left clicking little right text entry window, select disk, directory, file name that suits you. However, recommend that start with default file name location shown. Click
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look data that have just captured, left click "Plot_Data" button. have collected data with 12-bit 52MSPS -2dBFS sinewave input 5MHz, will two's complement data that looks like this:
Select "Histogram Debug", shown above, click "OK". When data capture control panel returns, verify your capture settings positioning mouse over progress bar. will following display:
Next, left click 12B_FFT button, will following plot performance summary. (Note that testing 14-bit should accordingly click 14B_FFT button instead.)
When press Start now, SRAM will cleared then board will count number times each code output. When count reaches number that with switches counting will stop data will transferred. MSPS maximum count 16384, counting takes about second. will LED1 flash data written read from SRAM. LED2 will again light about 10-15 seconds data transferred stored file that have selected. included m-files analyze histogram data extract ADC, start Matlab "analysis_menu". still have Matlab analysis menu visible again click "Plot_Data" histogram information:
more information Matlab routines, please refer section this manual "analysis.txt" file Mfiles directory. Configuring Histogram Capture (DNL Analysis) configure board histogram capture, right click capture control panel, then left click "Configure Capture." will capture configuration menu:
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this example, have captured data from 12-Bit ADC. Remember that data that plotting count information. output codes that were exercised ranged from code code 3865. maximum count 16384 (with switches OFF) this particular data record maximum count reached output code 3864. analyze converter's linearity, left click "DNL_INL" button, will following analysis window:
Getting Started Data Capture board capture data from National's DRCS Evaluation Board, will need following hardware, software, documentation. Several analysis tools provided form Matlab scripts. will prove helpful user some familiarity with CLC5902 data sheet Diversity Receiver Evaluation Board User Manual document.
Hardware
CLC730093 Data Capture Board. (CLC-CAPT-PCASM) CLC730090 DRCS Evaluation Board. (CLC-DRCS-PCASM) Power Supply DRCS Evaluation Capture Board combination require >1A. IBM-Compatible Personal Computer running Windows Windows Windows with serial port capable 115,200 baud. Serial data cable connect data capture board noise, filtered, Signal source analog input DRCS. OPTIONAL jitter clock source 16dBm sinewave) DRCS crystal oscillator removed.
Software
more information about this analysis technique, please refer Section this document, comments DNL_INL script file, IEEE Standard Digitizing Waveform Recorders (IEEE 1057-1994).
"Capture.exe" Contained provided CDROM. Data storage space hard drive (default path name "c:\temp\data.dat"). Matlab (version higher) analysis routines.
Documentation
Section III. Capturing Data from Diversity Receiver Chipset (DRCS) Evaluation Board
following applicable documents found provided CDROM, with most current versions available website http:// www.national.com: CLC5526 Data sheet Digitally controlled Variable Gain Amplifier (DVGA). CLC5956 Data sheet 12-bit, 65MSPS, sampled ADC. CLC5902 Data sheet Dual Digital Tuner/ (DDC/AGC). Diversity Receiver ChipSet Evaluation Board User's Manual (for CLC-DRCS-PCASM). General Description Program Options Data from Diversity Receiver ChipSet (DRCS) Evaluation Board captured from either serial outputs, parallel outputs, debug outputs. serial in-phase quadrature-phase data also captured simultaneously quadrature data analyses. Data Capture Board always returns 32,768
FILTERED I.F. SOURCE OPTIONAL CLOCK SOURCE
(2A)
Ain1
Ain2
10-16dBm
Serial
Serial COMM PORT
CONNECTOR
Data Capture Board
DRCS Evaluation Board
Serial COMM PORT
Diversity Receiver Chipset Evaluation Setup
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24-bit words serial port bytes. Each word interpreted 24-bit two's complement integer stored ASCII words user defined file. Each value terminated with carriage return (hexadecimal 0D). When Diversity Receiver Evaluation Board attached Data Capture Board, data narrower than bits aligned most significant with unused lower bits Serial data always 24-bits wide. Because various DRCS data output formats, care must exercised ensure that configuration conflicts occur between Data Capture board DRCS board. Such conflicts usually lead unpredictable data formats. default DRCS settings, "I/Q_Packed, Mux_Mode", compatible with Data Capture Board's 24-bit serial 16-bit parallel formats. "CLK" connector provides buffered output DRCS Serial Clock (SCLK) divided CLC5902 "RATE" register used further divide this clock. This clock output intended phase locking signal source DRCS XTAL oscillator. Because FPGA speed limitations, DRCS Serial Clock "RATE" settings recommended. default DRCS settings XTAL oscillator yield 13MHz output from this jack. Serial data from CLC5902 (DDC/AGC) configured "I/Q_Packed, Mux_Mode" majority evaluations (refer CLC5902 data sheet DRCS Evaluation Board User Manual). proper operation, decimation least required complete transfer whole 96-bit word (24-bits each phase phase). Data Capture board de-serializes DRCS data stream, registers selected channel phase, stores data SRAM, then reads formats SRAM data 24-bit word transmission serial communications port. Parallel Debug port data written directly 18-bit FIFO 24-bit SRAM. Because FIFO address counter, capable contiguous block capture 75MSPS recommended means data capture Fourier Analysis high speed data. SRAM address write controlled FPGA, which requires about clock strobes write cycle resulting data decimation. SRAM useful displaying time records data collecting contiguous blocks slower data that have been decimated CLC5902 DDC. SRAM memory element used board's hardwired histogram data generation. Capture Board Hardware Configuration Options DRCS data capture Place WCLK (FIFO write clock) jumper "PIN 120" position, VCORE should "5V" position eight switches their "OFF" position.
Using DATA CAPTURE Control Panel Data Capture Program, "capture.exe", must copied into directory user's setup/install program CDROM automatically places this program default directory (c:\nsc\). program generates user *.ini file within this same directory. file used store user options updated each time user changes options runs program. When Data Capture Program started, graphical user interface (GUI) Control Panel placed desktop.
left mouse button used drag control panel desired position desktop. Data Capture control panel should placed Windows task bar, otherwise software behave erratically. left click the? button will open informational text file. program configuration variables must setup prior running program using "Start" button. Clicking right mouse button within control panel brings user configuration options menu. left mouse button again used select desired menu option. following discusses function various menu options:
"Exit" button terminates Data Capture Program. "About" button opens window that displays version Data Capture Program well firmware revision FPGA Data Capture Board. Clicking left mouse button "SysInfo" button About window replaces with System Information window that displays some details about your Clicking left mouse button "OK" button System Information window closes returns About window. Clicking left mouse button "Visit page" text will open National Semiconductor's page using your internet browser. Clicking left mouse button "OK" button "About" window will close "Auto Hide" "Always Top" selections enable disable these functions. check mark left each selection indicates when enabled.
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"Configure I/O" button opens user port option menu window. Clicking left mouse button selects desired port (the default Windows address assumed). Clicking "OK" button sends identification command selected port listens Capture board echo back command. This function requires that power data clock present. hardware functional proper port connected, Configure window will then close return back user Control Panel. Capture Board LED#6 will data clock present.
"Configure Capture" button invokes user dialog window remainder configuration options. After selecting desired options, left mouse click "OK" stores configuration variables returns Control Panel. Positioning mouse pointer over Progress inside Control Panel pops text bubble which displays configuration variables used when Capture Program started. Next discussion Mode functions related sub-functions: MODES There four primary modes which data capture system, each with associated options: Capture mode configures Capture Board data reception from DRCS evaluation board. Both serial parallel output ports used source data path. 24-Bits option captures serial DRCS data FROM either serial data ports. Capture option should selected this mode data capture. With CLC5902 "packed" "mux_mode", AOUT data source contains both phases both channels. Channel buttons select desired channel stored SRAM. four Phase buttons select either phase ordering alternating phases. this latter case, space shared. Therefore, only points each phase collected. BOUT data source selected, CLC5902 must instructed accordingly (i.e. "packed" "mux_mode" off). With default output format, BOUT serial port disabled. Upper 16-Bits Lower 16-Bits options enable CLC5902 DDC's parallel outputs. this configuration parallel output controlled FPGA through Euro connector sure that DRCS board "POUT" switches OFF/OPEN). user selects Channel Phase FPGA instructs which channel, phase, which half 32-bit output word send parallel data bus. This configuration uses FIFO temporary data storage. Histogram mode returns Capture Board 24-bit serial data mode. before, with CLC5902 "packed" "mux_mode", AOUT data source contains both phases both channels. change required enable BOUT. Capture option should selected before. Histogram configuration, program Start button first sets every SRAM location value zero. hardware then samples data, reads value that memory location, increments value, writes back updated value. process continues until memory values reach target value
incorrect serial port selected hardware dysfunctional (i.e. missing power clock) program will return error-warning window.
Click "OK" button clear warning then other serial port "I/O Configuration" window correct hardware problem. "Change Data File" button enables dialog window where user direct location captured data file. desired file name path typed into box. Clicking left mouse button right side file name opens standard browser window search appropriate file name. "Default" button restores default directory file name. attached Matlab script analysis routines (*.m files) assume that data located this location; however, user edit routines load from appropriate location. Clicking "OK" button updates Capture program's *.ini file returns Capture Control Panel.
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indicated Histogram Target table. high data resolution relatively slow data rate, relatively long period time required generating histogram data from DRCS with high decimation values DDC. Under some circumstances, serial interface will time out. program detects this condition queries user continue. Click "Yes" continue wait Progress completion. patient, could take several minutes depending input amplitude decimation value Histogram Target Value. last mode description, Debug Histogram, provides further description output file generated hardwired histogram generator. Histogram Target Table
gram data DRCS output generated Capture Board input frequency 150MHz 16dBm amplitude using default DRCS settings. data source serial output (Capture Histogram mode used where Fsample 270KHz) therefore took several minutes collect. this scenario 24-bit data source resolution truncated 15-bits (32K) available SRAM. histogram peak target which required over million data points processed input level -2dB below full scale. number data points proportional Target amplitude range data (the Xaxis). "Plot Data" menu function analysis tools used generate actual Matlab plot figure.
SW1;
SW1;
Histogram Target Value
Capture Debug mode configures Capture Board collect data from DRCS evaluation board's 20-bit parallel debug data bus. Because FIFO memory limited bits, user given option collect full data width SRAM selecting Bits menu button. previously mentioned, parallel data which runs full clock speed (i.e. Mixer Debug port) gets decimated fact that FPGA requires multiple clock strobes address write data into SRAM. Choosing Upper Bits option will high speed FIFO memory element collect contiguous block data. Debug data port provides users access nodes internal CLC5902 DDC. Refer DRCS Evaluation Board User Manual CLC5902 data sheet more detailed information. Histogram Debug mode configures Capture Board generate histogram file using parallel data source. hardware requires multiple clock strobes increment each SRAM value. Even though data used contiguous block, probability density information retained. SRAM depth (32K) used store data values; therefore, histogram generator limited 15-bits resolution (there only 32,767 bins). values bins will read SRAM sent users regardless resolution data source. DRCS Debug data will displayed 15-bit resolution limit (this also case DRCS 24-bit Serial data) histogram will centered about 16,384 assuming there intentional offset. following figure displays sine wave histohttp://www.national.com
DRCS Evaluation Setup Sanity Check following discussion confirm DRCS evaluation setup. example uses Fourier analysis simple, single tone, sinusoidal input DRCS. assumed that Setup.exe evaluation kit's CDROM installed necessary files user's DRCS Data Capture hardware configured shown diagram front Section III. also assumed that Matlab (version higher) available. Reconfiguration DRCS through Control Panel software required these tests. DRCS default values contained within micro-controller with SW2:1-8 DRCS board) will configure CLC5902 with proper values. power been applied while another state user RESET micro-controller with different switch setting, then switches press RESET button DRCS Evaluation board. Apply input signal AIN1 jack DRCS Evaluation board 150MHz 0dBm. mixer -5.97MHz which brings aliased (Fclk 52MHz; alias 156MHz) signal down +30KHz. then filters decimates data sends serial port (AOUT) "packed", "muxed_mode" format.
From Windows Start Programs menu, launch Capture program (it's inside C:\nsc folder). Right click inside Control Panel select Configure click appropriate port button. Next, right click inside Control Panel select Configure Capture. Select following options: Mode Capture; Bits =24; Channel From AOUT; Capture Bit; Phase Phase Only. Click "OK" then click Start button Control Panel start data capture. progress should conclude about seconds. Launch Matlab. Matlab path browser include analysis Mfiles. installed default path "c:\nsc\mfiles". this Matlab paths, save directory file exit path browser. Matlab command line enter "analysis_menu". will appear. Left click DRCS_Serial button perform captured data.
plot above analysis results highlight several setup issues. poor SINAD (and corresponding ENOB) phase jitter (spec'd Phase Noise) signal source HP8656 used here). better choice signal synthesizer HP8644B, which yields SINAD about 60dB under same conditions. main portion noise power contained carrier's immediate sidebands (±5KHz). Another point interest that there several spectral lines about -75dBFS 25KHz either side fundamental. These have been traced ground loop created serial interface. Both serial interface cables were connected while this data being collected. Removing cable DRCS will reduce amplitude these spurs. Some ground loop remains because required Capture Board's serial interface
menu disappears while analysis routine running. process takes seconds 133MHz plots results when finished. should report input power about -18dBFS.
32768 Point Analysis
Pinput (dBFS) -18.1087 Output SINAD 51.7058 Output SFDR 56.0663 (dBFS) -100.7444 floor -69.448 -100 ENOB 11.302 -120 -140 -160
Section Data Analysis Tools
Matlab scripts contained Evaluation CDROM provide convenient toolset evaluation National's Diversity Receiver ChipSet (DRCS) high speed ADCs like CLC595x family. There routines Sine Histogram routine which called from user interface menu, "analysis_menu". Matlab path working directory that "Mfiles" provided Evaluation CDROM. "analysis_menu" from Matlab command window open graphical user interface. Each called routines appropriate variables prior data analysis. These variables explained adjacent text easily edited adjust particular application from Matlab's script editor. There also comments within routines that highlight various analysis blocks.
Magnitude (dBFS)
Frequency
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DRCS_Serial "DRCS_ser_fft.m" script intended analysis DRCS 24-bit serial output data. Fsample default 52e6/192 which standard output rate 270.833KS/s. "search' option enabled; therefore, excluding bins, peak assumed input fundamental. default 4term data window used. DRCS_Debug "DRCS_par_fft.m" script intended analysis DRCS 16-20 parallel debug data. hardware setting will determine actual Fsample variable needed. data always placed within 24-bit word with justification. default Fsample assumed clock frequency 52MHz with decimation. debug port selected which decimated data, Fsample variable will require appropriate adjustment. Carefully edit save value into script file. original file recovered from CDROM. 14-bit "b14_FFT.m" script intended data analysis conjunction with CLC5958 Evaluation Board. routines with rectangular window setting variable "0". Setting "Dither" variable excludes lower portion spectrum from analysis intended used conjunction with base-band dither signal being present analog input.
12-bit "b12_FFT.m" script intended data analysis conjunction with CLC5956 Evaluation Boards. DNL_INL "dnl_inl.m" script intended data analysis histogram data file generated Data Capture Board. data file fixed 2^15 length (i.e. number histogram bins). Capture Board justify data within 2^15 bins. 12-18 histograms supported. This Matlab script automatically scales data source. addition graphic plots, routine gives number samples, input amplitude (dBFS ADC), data offset LSBs). Data Capture Board User Manual more info. Plot_Data this script contained within "analysis_menu.m". simply clears figure, loads data file from default location, plots data. data manipulation occurs. user wishes view offset binary formatted data which been normalized should first appropriate analysis, then clear plot figure (use "clf"at Matlab command line) plot variable (use "plot(u,'.')" Matlab command line).
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CLC-CAPT-PCASM Evaluation Board Layer
CLC-CAPT-PCASM Evaluation Board Layer
CLC-CAPT-PCASM Evaluation Board Layer
CLC-CAPT-PCASM Evaluation Board Layer
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5$0B$ 5$0B 8B,2 8B,2 8B,2 8B,2 8B,2 5$0B$ 8B,2 5$0B$ 5$0B 5$0B$ 5$0B$ 5$0B$ 5$0B$ 5$0B
2+06 9,17
5$0B$ 5$0B 8B,2 8B,2 8B,2 8B,2 8B,2
2+06
/0,03B
9287
%2$5' *5281' 7(67 32,176
8B,2
5$0B$ 5$0B$ 5$0B$
5$0B$ 8B,2 8B,2 5$0B$ 5$0B$ 5$0B$ 5$0B$ 5$0B$ 5$0B$ 8B,2 8B,2 5$0B$ 5$0B$ 5$0B$ 5$0B$ 5$0B$ 5$0B$
9&&'
9&&'
8B,2 8B,2 5$0B$ 5$0B$
5$0B$
5$0B$
5$0B$
5$0B$
5$0B$
5$0B$
CLC-CAPT-PCASM Data Capture Board User's Guide
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Section Introduction CLC3790093 Data Capture Board enables simple

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