SILICON DELAY LINES HYBRID NETWORKS Figure shows internal views t

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Application Note Design Considerations All-Silicon Delay Lines
SILICON DELAY LINES HYBRID NETWORKS
Figure shows internal views typical 5-tap hybrid delay line silicon counterpart. hybrid manufactured using commercially available inverter (e.g., 74LS04) with small board placed supply ground plane. Next, several
leads bent over board. Five chip capacitors terminating resistor soldered ground plane 5-tap ferrite inductor positioned above. Note that nearly dozen solder joints required electrically connect various components. Finally, entire assembly placed into oversized plastic filled with potting material.
INTERNAL VIEWS Figure
HYBRID DALLAS SEMICONDUCTOR SILICON
ORDINARY VIEW BEFORE "POTTING"
CUT-AWAY VIEW
comparison, silicon delay line consists laser- optimized bonded conventional lead frame molded into auto-insertable industry standard surface mount SOIC package. low-power CMOS design fabricated six-inch wafers Dallas Semiconductor's Class facility. Using lasers late definition finished wafers provides both economy maximum flexibility; both rising falling edges programmed standard custom delays over wide range values. post-laser final passivation step protects against contamination covering laser fuse windows before packaging.
basic building block silicon delay line consists ramp generator with associated logic (Figure input signal triggers ramp generator that supplies laser-adjusted voltage-to-time relationship (Figures comparator used detect ramp reaching reference voltage (VREF); this sets resets output latch. DS1013 family three independent blocks parallel while DS1000, DS1005, DS1010 families have blocks connected series with single external input (Figure silicon delay lines, unlike most TTL-based hybrids, have true CMOS output levels.
ECopyright 1995 Dallas Semiconductor Corporation. Rights Reserved. important information regarding patents other intellectual property rights, please refer Dallas Semiconductor data books.
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BASIC BUILDING BLOCK Figure
INPUT OUTPUT
RAMP
LOGIC
VOLTAGE TIME CONVERSION Figure
VOLTAGE CAPACITORS
VREF
TIME
VOLTAGE COMPARATOR
DELAY
TIME
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EXPANDED BASIC BLOCK Figure
INPUT RISE EDGE RAMP GENERATOR OUTPUT
VREF RESET
FALL EDGE RAMP GENERATOR
COMPARATORS
DELAY LINE FAMILIES Figure Tapped Delays (e.g., DS1000 DS1010)
DELAY DELAY DELAY DELAY
Multiple Independent Delays (e.g., DS1013, DS1007, DS1044)
TOTAL DELAY
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linear ramp generator implemented with constant current sources charging capacitors (Figure using combination several large current sources capacitors binary weighted smaller current sources capacitors, maximum flexibility with subnanosecond adjustment obtained single silicon
(Figure Under direction computer-controlled tester with picosecond resolution, proper slope ramp (Figure obtained directing laser remove unnecessary current sources capacitors. This accomplished opening polysilicon fuses (Figure
BASIC RAMP GENERATOR Figure
VREF
CONSTANT CURRENT SOURCE(S)
COMPARATOR LATCH
CAPACITOR(S)
LASER PROGRAMMABLE ELEMENTS Figure
CONSTANT CURRENT SOURCES
LASER FUSES
COMPARATOR LASER FUSES CAPACITORS
MAINS
BINARY WEIGHTED
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RANGE ADJUSTMENT Figure
CAPACITORS MANY CURRENT SOURCES MANY CAPACITORS CURRENT SOURCES
VOLTAGE CAPS VREF
TIME
LASER BLOWING POLYSILICON FUSE Figure
CAPACITORS LASER BEAM
LENS
GLASS
FROM CONSTANT CURRENT SOURCES
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DELAY TEMPERATURE Figure
SILICON LOGIC DELAY (ONLY) SLOW
NOMINAL DELAY
FAST
COLD
ROOM TEMP.
SILICON RAMP DELAY (ONLY) SLOW
NOMINAL DELAY
FAST
COLD
ROOM TEMP.
SILICON DELAY LINE SLOW
NOMINAL DELAY
FAST
COLD
ROOM TEMP.
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Timing hybrid lines determined coil winding and/or capacitor selection trimming. Achieving both rising falling edge accuracy same time difficult achieve comes premium price. Furthermore, timing subject variations 74LS04 devices procured from other manufacturers. silicon delay lines, temperature compensation implemented balancing positive temperature coefficient CMOS logic against negative coefficient ramp generator. Figure shows that logic portion circuit, like hybrid delay lines general, slows linearly with increasing temperature. Since ramp speeds non-linearly, effects tend cancel, minimizing effects temperature. Because result resembles parabolic shape, temperature
coefficients specified parts million (ppm) inappropriate describe behavior silicon delay lines. more meaningful parameter maximum shift from nominal, anywhere over rated temperature range. Figure compares technologies over temperature. While some silicon delay line families (DS1000, DS1010) provide minimal voltage independence delay change supply variation), newer designs (DS1005 DS1013) provide higher degree supply isolation delay change supply variation). newer designs achieve supply voltage independence employing positive ramps referenced ground rather than negative ramps referenced (Figure 12).
HYBRID SILICON OVER TEMPERATURE Figure
SLOW
NOMINAL DELAY
KEY: SILICON HYBRID FAST COLD ROOM TEMP.
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COMPARISON DELAY DESIGNS Figure
VREF
DS1000
OUTPUT
INDEPENDENT
VREF
DS1005
OUTPUT
NEARLY INDEPENDENT
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While hybrids offer little flexibility packaging, silicon lines available variety industry standard SOIC packages (Figure 13). maintain compatibility with existing designs based hybrids having missing pins, clipped lead version offered. Finally, surface mount applications, solutions available: DIPs with leads trimmed "gull winged," industry standard SOIC packages. Table summarizes some disadvantages hybrid design some advantages silicon solution.
TABLE
Disadvantages Hybrids: Unreliable solder joints Difficult control falling edge accuracy output levels Large, non-standard package dimensions Advantages Silicon Reliable all-silicon design Accurate rise fall edges Easily customized CMOS output levels inductors Industry standard SOIC packaging Standard handling including reflow soldering
PACKAGING OPTIONS Figure
DUAL-IN-LINE (DIP) packages available counts pins. Three lead-forming options available: Straight lead. This conventional package used through-hole mounting PCBs. Gullwing. leads formed flat surface surface mount applications. Sheared connect" (NC) leads sheared package. This package commonly used hybrid replacement applications. NOTE: gullwing sheared packages encouraged designs; however, these packages will continue made available existing designs. SMALL OUTLINE (SOIC) Small outline surface mount packages available counts pins. package widths also available: mil. PACKAGE AVAILABILITY/LETTER DESIGNATIONS PINS Default package, letter designator required. Tape reel packaging also available; contact factory more information none* GULLWING SHEARED SOIC
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QUESTIONS ANSWERS
QUESTION: silicon timed delays differ from hybrid devices? ANSWER: typical hybrid consists inverter DIP, board acting ground plane plus chip capacitors, terminating resistor multiple ferrite inductor. Timing determined coil winding and/or capacitor selection trimming. Dallas Semiconductor Silicon Timed Circuit (STC) design uses laser-optimized bonded conventional lead frame molded into auto-insertable SOIC package. (500 pulse width, period) will timing correlation when measured volt levels. QUESTION: does laser-adjustment time delay? ANSWER: Under direction computer-controlled tester with picosecond resolution, proper slope ramp obtained directing laser open polysilicon fuses removing unnecessary current sources capacitors.
QUESTION: delay time need? QUESTION: What advantages silicon timed circuits over hybrid devices? ANSWER: (Silicon Timed Circuits) offer advantages design, packaging manufacture over hybrids. Specifically, STCs offer increased reliability silicon greater accuracy both rise fall edges. Unlike devices, STCs CMOS devices offer true output levels. Using standard SOIC packaging, STCs well suited standard handling including reflow soldering. ANSWER: Yes, custom delay lines customized meet your design timing requirements. even supply sample quantities ceramic packages evaluation.
QUESTION: STCs need compensate temperature like hybrids? ANSWER: silicon delay lines, temperature compensation implemented balancing positive temperature coefficient CMOS logic against negative coefficient ramp generator. logic portion circuit speeds linearly with increasing temperature while ramp speeds non-linearly. These effects tend cancel, minimizing effects temperature. Rather than measuring coefficients parts million, silicon delay lines meaningfully measured maximum shift from nominal anywhere along rated temperature range. delays require
QUESTION: Whats basic operation silicon delay line device? ANSWER: basic building block silicon delay line ramp generator associated logic. input signal triggers ramp generator that supplies laser- adjusted voltage-to-time relationship.
QUESTION: there correlate performance silicon time delays against hybrids? ANSWER: Following this procedure will provide correlation. fast(3ns) rise/fall input pulses with volt logic levels, inductance decoupling techniques using 0.01 capacitors, capacitance measurement probes placed close possible package, relaxed timing
QUESTION: silicon timed decoupling? ANSWER:
STCs contain noise sensitive voltage detection circuits fast rise time output circuits decoupling indicated. 0.01 inductance capacitor should used close proximity delay line assure highest performance.
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QUESTION: silicon delay lines also function glitch discriminators? ANSWER: Yes, pulse glitch less than about first stage delay 10-tap serial device (DS1000, DS1005 1010) less than about 3-in-1 parallel device (DS1013) there will output.
QUESTION: daisy chain several devices achieve longer delay? ANSWER: Daisy chaining silicon delay lines presents problem that increased with number packages chain. voltage chopped stabilization circuit design causes slight time jitter (well within specifications almost transparent circuit) output. When packages daisy chained, time jitter cumulative degrades accuracy downline stages. four packages chained series, results generally unacceptable.
QUESTION: silicon delay line used time-shift square wave? ANSWER: Yes, good solution. Just certain period specification met.
QUESTION: What temperature parameters silicon timed delays meet? ANSWER: STCs function over full military (-55°C +125°C) temperature range, have been optimized commercial (0°C +70°C range. product family DS1000-Ind available industrial temperature range. Other parts specified industrial temperature range custom basis.
QUESTION: What about daisy chaining stages parallel STC? ANSWER: With exception fast taps DS1007, some jitter will added with each stage when added series. This will problem most cases. Users report that daisy chaining this convenient method implementing standard series delays.
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SILICON DELAY LINES HYBRID NETWORKS Figure shows internal views t

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