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Microcontrollers ApNote AP163702
Reset System Startup Configuration PORT0
This application note presents overview about different reset types behaviour concerning system startup configuration PORT0. calculation Pull-up/down resistors PORT0 also included.
Author: Mariutti
Semiconductor Group
6.98,
Reset System Startup
Contents
Page
Overview about different Reset Sources Hardware Reset Software Reset Watchdog Timer Reset Bidirectional Reset
System Startup Configuration Overview about PORT0 Configuration during Reset PORT0 Sample Timing different Reset Types Calculation Pull-up/down Resistors PORT0 Startup Configuration Pull-down Calculation Pull-up Calculation Port_0 Appendix PORT0 Configuration during Reset Clock Options Steps
AP163702 ApNote Revision History Actual Revision 6.98 Previous Revision 9.97 Page actual Rev. Page prev.Rel. Subjects (changes since last release) Bidirectional Reset: Device list updated line' replaced line with integrated pull-up resistor' Table Column added Figure Sign corrected Order CSSEL pins corrected Appendix clock options steps updated
Semiconductor Group
AP163702 6.98
Reset System Startup
Overview about different Reset Sources
During reset, device executes special internal sequence order inside signals special function registers their specified default values. contents some special function registers controlled during system startup configuration PORT0. system startup configuration sampled upon different reset events. table Hardware Reset: Power-on Reset Short Hardware Reset (Warm Reset) Long Hardware Reset (Power Down Wakeup Reset)
Software Reset Watchdog Timer Reset
Reset Source Power-on Reset Short Hardware Reset Long Hardware Reset Watchdog Timer Reset Software Reset Table Reset Sources Reset Conditions
Short-cut PONR SHWR LHWR WDTR
Condition Power-on tRSTIN 1024 tRSTIN 1024 overflow SRST command
Hardware Reset
hardware reset triggered when reset input signal RSTIN latched low. ensure recognition RSTIN signal (latching), must held least clock cycles nsec Clock). Also shorter RSTIN pulses trigger hardware reset, they coincide with latch's sample point. However, microcontrollers with on-chip recommended keep RSTIN msec guarantee that locked. After reset sequence been completed, RSTIN input sampled. When reset input signal active that time internal reset condition prolonged until RSTIN gets inactive. input RSTIN provides internal pullup device equalling resistor (the minimum reset time must determined lowest value). Simply connecting external capacitor sufficient automatic power-on reset. RSTIN also connected output other logic gates.
Three different kinds external hardware resets have considered: Power-on Reset complete power-on reset requires active RSTIN time reset sequences 1024 51.2 µsec Clock) after stable clock signal available.
Semiconductor Group
AP163702 6.98
Reset System Startup
Depending oscillation frequency on-chip oscillator needs about 2.50 stabilize. Long Hardware Reset long hardware reset requires active RSTIN time longer than duration internal reset sequence. duration internal reset sequence 1024 (1024 25.6 µsec Clock). long hardware reset also named power down wakeup reset. Short Hardware Reset active RSTIN time short hardware reset between 1024 TCL. RSTIN signal active least clock cycles (100 nsec Clock) internal reset sequence started (1024 TCL, 25.6 µsec Clock). After internal reset sequence been completed, RSTIN input sampled. When reset input still active that time internal reset condition prolonged until RSTIN gets inactive. RSTIN signal active more then 1024 then behaviour PORT0 latch mechanism equal long hardware reset.
Software Reset
reset sequence triggered time protected instruction SRST (Software Reset). This instruction executed deliberately within program, e.g. leave bootstrap loader mode, upon hardware trap that reveals system failure.
Watchdog Timer Reset
When watchdog timer disabled during initialization serviced regularly during program execution will overflow trigger reset sequence. watchdog timer reset releases automatically software reset. Other than hardware reset watchdog timer reset completes running external cycle this cycle either does READY all, READY sampled active (low) after programmed waitstates. When READY sampled inactive (high) after programmed waitstates running external cycle aborted. Then internal reset sequence started. Note: watchdog timer reset cannot occur while device bootstrap loader mode! Bidirectional Reset
bidirectional reset feature implemented since devices steps listed below. steps parentheses only reflect software- watchdog timer Reset RSTIN short hardware reset shown figure C161RI Step C161CI Step C164CI-8EM Step C167CS-32FM Step C167CR-LM (CA), Step C167S-4RM (BA), Step C167CR-4RM (AB), Step
Semiconductor Group
AP163702 6.98
Reset System Startup
bidirectional reset mode device's line RSTIN (normally input) driven active chip logic e.g. order support external equipment which required startup (e.g. flash memory).
RSTIN
Internal Circuitry
Reset sequence active BDRSTEN
Figure Bidirectional Reset Operation
Bidirectional reset reflects internal reset sources (software, watchdog) also RSTIN converts short hardware reset pulses minimum duration internal reset sequence. Bidirectional reset enabled setting BDRSTEN register SYSCON (SYSCON.3) changes RSTIN from pure input open drain line with integrated pull-up resistor. When internal reset triggered SRST instruction watchdog timer overflow level applied RSTIN line, internal driver pulls duration internal reset sequence. After that released then controlled external circuitry alone. bidirectional reset function useful applications where external devices require defined reset signal cannot connected device's RSTOUT signal, e.g. external flash memory which must come reset deliver code well before RSTOUT deactivated EINIT. following behaviour differences must observed when using bidirectional reset feature application:
BDRSTEN register SYSCON cannot changed after EINIT. After reset BDRSTEN cleared (bidirectional reset disabled). WDTR will always '0', even after watchdog timer reset. PORT0 configuration treated like hardware reset. Especially bootstrap
loader maybe activated when P0L.4 low. RSTIN only connected external reset devices with open drain output driver.
Semiconductor Group
AP163702 6.98
Reset System Startup
System Startup Configuration
Some system features have selected before first program execution performed. These selections made during reset Pins PORT0, which latched reset.
Overview about PORT0 Configuration during Reset
PORT0 startup configuration sampled either with internal reset sequence with external hardware reset. external RSTIN signal deactivated before internal reset sequence (short hardware reset) then internal reset signal (IRS) device used latch system startup configuration PORT0, else (power-on reset long hardware reset) PORT0 latched after rising edge RSTIN with IRS. sampling point PORT0 (prescaler enabled) (direct drive PLL) after rising edge RSTIN shown PORT0 sample timing (see figures below). duration internal reset sequence 1024 initializing internal special function registers plus jump address 00'0000 after internal reset sequence. already mentioned bidirectional reset feature converts software reset, reset short hardware reset externally visible hardware reset with duration 1024 TCL. This feature disabled after hardware reset enabled software.
sampled
PORT0 Mode Invert P0H.7 Ext. Access Enable P0L.0 (OWD disable) Adapt Mode P0L.1 Config. Addr. Lines
Reserved
Reserved P0L.3
BDRST
Selects
Clock options
Segm.
Type
transparent sampled
P0H.7
P0H.6
P0H.5
P0H.4
P0H.3
P0H.2
P0H.1
P0L.7
P0L.6
P0L.5
P0L.4
Sample event PONR LHWR SHWR WDTR/SWR SHWR WDTR/SWR
ON/OFF
P0L.2
P0H.0
Reserved
Chip
Table System Startup Configuration PORT0
Semiconductor Group
AP163702 6.98
Reset System Startup
PORT0 Sample Timing different Reset Types
different reset sources timing relations PORT0 during reset shown below. reset event occurs then PORT0 switched input mode internal pull-ups active. During that time possible that desired input voltage levels PORT0 forced internal/external pull-ups pull-downs startup configuration) reached. Therefore PORT0 transparent 1024TCL (power-on reset 2048 TCL) prevent unexpected behaviour system. After that time part PORT0 becomes transparent reset these pins sampled with signal. Depending reset type some PORT0 pins transparent, e.g. P0L.1 P0L.0 which control Adapt Mode Emulation Mode. Noise these lines during reset would force microcontroller Adapt Mode Emulation Mode. Therefore both pins transparent until sample point reset condition. PORT0 sample timings shown below based following conditions: tP0fix: tSHR: IRS: During tP0fix PORT0 constant System Startup Configuration latched correctly. Duration short hardware reset. tSHR 1024 Internal Reset Signal: Sampling point PORT0 configuration bits (prescaler enabled) (direct drive PLL) after rising edge RSTIN after internal reset sequence. *fCPU), nsec Clock
TCL:
2048 RSTIN P0[15:2] P0[1:0] System clock available Figure PORT0 sample Timing: Power-on Reset transparent transparent transparent tP0fix
Semiconductor Group
AP163702 6.98
Reset System Startup
1024 RSTIN P0[15:2] P0[1:0] transparent transparent transparent tP0fix
Figure PORT0 sample Timing: Long Hardware Reset, Bidirectional Reset enabled disabled
tSHR RSTIN P0[12:2] P0[15:13] P0[1:0] transparent transparent transparent 1024
transp.
tP0fix
Figure PORT0 sample Timing: Short Hardware Reset, Bidirectional Reset disabled
1024 P0[12:6] transparent tP0fix transp.
P0[15:13] P0[5:0] Reset
transparent
Figure PORT0 sample Timing: Software Reset Reset, Bidirectional Reset disabled
Semiconductor Group
AP163702 6.98
Reset System Startup
1024 RSTIN P0[15:2] P0[1:0] Reset transparent transparent transparent tP0fix
Figure PORT0 sample Timing: Software Reset Reset, Bidirectional Reset enabled
1024 RSTIN P0[15:2] P0[1:0] transparent transparent tP0fix transparent
Figure PORT0 sample Timing: Short Hardware Reset, Bidirectional Reset enabled
Semiconductor Group
AP163702 6.98
Reset System Startup
Calculation Pull-up/down Resistors PORT0 Startup Configuration
specification Data Sheet includes values PORT0 configuration currents IP0H. Pull-down Calculation
IP0L base calculation Pull-down resistors PORT0 startup configuration. IP0Lmin -100 VILmax. That means that port configuration current more equal than input voltage lower equal VILmax. system current ISYSL direct influence value needed pull-down resistor. relation between different parameters calculation with example shown below. Note: currents flowing into microcontroller defined positive currents flowing defined negative. Because internal pull-up transistor direction IP0L device therefore sign current specification negative.
RESET 100µA Port VILmax leakage current
C16x
System
Figure System Environment Pull-down Resistor Startup Current Specification Data Sheet: 4.5V 5.5V 0.8V 1.0V IP0L |-100µA|
0.2Vcc 0.1V IP0Lmin -100µA
Semiconductor Group
AP163702 6.98
Reset System Startup
Pull-down resistor calculation:
SYSL
Example without system current: (ISYSL recommended maximum value:
100µA
Pull-up Calculation
IP0H base calculation pull-up resistors PORT0 startup configuration. IP0Hmax VIHmin. already mentioned PORT0 supplies internal pull-up resistors which only active during Reset, during Hold-or Adapt-mode. normal systems this internal pull-up resistors sufficient reach input high voltages PORT0 pins. This situation changes when system current ISYSH exceeds Then additional external pull-up resistors mandatory. example system flash memory with high leakage current cause increased ISYSH. calculation example shown below.
RESET 10µA Port VIHmin
leakage current
C16x
System
Figure System Environment Pull-up Resistor Startup
Semiconductor Group
AP163702 6.98
Reset System Startup
Current Specification Data Sheet: IP0H |-10
IP0Hmax
Pull-up resistor calculation:
CCmin IHmin SYSH
Example: ISYSH 50µA:
67.5 50µA 10µA
recommended maximum value: 67.5
Semiconductor Group
AP163702 6.98
Reset System Startup
Appendix PORT0 Configuration during Reset
CLKCFG
SALSEL
CSSEL
BUSTYP
SMOD
SMOD (P0L.5:2) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Mode Emulation Mode Adapt Mode Special Modes Reserved Reserved Reserved Reserved Reserved Reserved Reserved External Host Mode (EHM)1) Reserved Reserved Bootstrap Loader Host Mode1) Bootstrap Loader Reserved Reserved Host Mode (CHM)1) Normal Start
Comment Condition Quality P0H.7 inverted
this combination this combination this combination this combination this combination this combination this combination Requires Emulation Mode this combination this combination Serial programming Start from internal boot this combination this combination programming mode Normal start defined
Semiconductor Group
AP163702 6.98
Reset System Startup
BUSTYP (P0L.7:6) CSSEL (P0H.2:1) SALSEL (P0H.4:3) CLKCFG (P0H.7-5)
External Data Width 8-bit Data 8-bit Data 16-bit Data 16-bit Data Write Configuration Chip Select Lines Max: CSx.CS0 None Two: CS1.CS0 Three: CS2.CS0 Segment Address Lines Two: A17.A16 Axx.A16 None Four: A19.A16 Frequency fCPU fXTAL fXTAL fXTAL fXTAL fXTAL fXTAL fXTAL fXTAL fXTAL
External Address Mode Demultiplexed Addresses Multiplexed Addresses Demultiplexed Addresses Multiplexed Addresses
Default without pull-downs Port pins free
Directly accessible Address Space KByte (Default, without pull-downs) (Maximum) KByte (Minimum) MByte Notes2) Default configuration
Direct drive
Prescaler
This modes only valid C161CI, C164CI C167CS User's Manuals detailed information.
clock configuration bits fully decoded devices steps. Please Appendix
Semiconductor Group
AP163702 6.98
Reset System Startup
Clock Options Steps
Device SAx-C161V SAx-C161RI SAx-C161SI SAx-C163 SAx-C163-16F SAx-C163-16F SAx-C164CI SAx-C165 SAx-C165 SAx-C167-LM SAx-C167SR-LM SAx-C167SR-LM SAx-C167SR-LM SAx-C167CR-LM SAx-C167CR-LM SAx-C167S-4RM SAx-C167CR-4RM SAx-C167CR-16RM SAx-C167CR-16FM SAx-C167CS-32FM
Step1)
OWD2)
VPP/OWE VPP/OWE
PM3) Clock Options Factors 1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 1.5/2/2.5/3/4/5 2/3/4/5 1.5/2/2.5/3/4/5 2/3/4/5 2/3/4/5 1.5/2/2.5/3/4/5 2/3/4/5 1.5/2/2.5/3/4/5
AA,BA,
Semiconductor Group
AP163702 6.98
Reset System Startup
described options implemented since steps listed below.
Oscillator Watchdog (OWD) disabled different kinds. implemented.
VPP/OWE level VPP/OWE disables OWD. level type reset disables OWD. level latched with IRS. figure figure level disables OWD.
Besides other features Power Management (PM) includes Slow Down Devider. separate clock path selected Slow Down operation bypassing basic clock path used standard operation. programmable Slow Down Devider devides oscillator frequency factor
Prescaler option Direct drive option clock used prescaler option fOSC 0.5) direct drive option (fCPU fOSC 1.0).
Semiconductor Group
AP163702 6.98
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