Program Memory Expansion using Bankswitching Capability C5xx/80C5xx Fa

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Program Memory Expansion using Bankswitching Capability C5xx/80C5xx Fa

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AP0824
Program Memory Expansion using Bankswitching Capability C5xx/80C5xx Family
This application note describes proceeding external program memory expansion from KByte KByte using bankswitching capability C5xx/80C5xx Family
Author: Klaus Scheibert Microcontroller Application Support
Semiconductor Group
06.97, Rel.
C5xx/80C5xx Bankswitching Capability
Introduction.3 Memory Organization External Memory Organization External Memory Organization Hardware Description.6 Software Proceeding Timing Considerations concerning External Program Memory Access Conclusion
AP0824 ApNote Revision History Actual Revision Rel.01 Previous Revison: none (Original Version) Page Page Subjects changes since last release) actual Rel. prev. Rel. Original Version
Semiconductor Group
AP0824 06.97
C5xx/80C5xx Bankswitching Capability
Introduction
some applications, using 80C5xx/C5xx architecture, there need more than kByte external program memory space. This request becomes more more important increased usage high level language C51. following apnote proposes solution with standard device 74HC257 used external glue logic solve kByte boundary problem external program memory.
Memory Organization
memory partitioning C5xx/80C5xx microcontrollers typically Harvard architecture where program data areas held seperate memory areas. program data memory areas same physical address range from 0000H FFFFH instruction code/data format. External Memory Organization
When using external memory resources, external program data memories expanded kByte each external multiplexed memory interface C5xx/80C5xx architecture. Locations 0000H 0100H program memory used hard-wired interrupt vector addresses corresponding interrupt service routines. external program memory automatically selected (External Access) held logic level. external data memory selected MOVX instructions from C5xx/80C5xx 8-bit instruction set. following figure shows this external memory resources with
Semiconductor Group
AP0824 06.97
C5xx/80C5xx Bankswitching Capability
Code Memory
FFFFH
Data Memory
FFFFH
kByte
kByte
ext. Program Memory AREA
ext. Data Memory AREA
0100H 0000H
Interrupt Vector Addresses
0000H
Figure External Memory Organization External Memory Organization
this application example, external program memory expanded kByte data memory remains program memory split into sixteen kByte banks (named Bank 0-15); each addressed address lines combination with bank select lines A18. C5xx/80C5xx external interface supports address lines 8-bit ports address lines microcontrollers external interface used directly interface external program memory. Additionally, four normal standard pins used interfacing bank select lines external program memory.
Semiconductor Group
AP0824 06.97
C5xx/80C5xx Bankswitching Capability
P2.7/A15 address line microcontroller used connection with external glue logic select between fixed bank address range 0000H 7FFFH preselected upper bank 1-15 (preselected four standard pins program memory address lines A18). address line P2.7/A15 microcontroller selected (logic level), always lowest kByte bank external program memory accessed external glue logic. With activation microcontrollers address line P2.7/A15 (logic each remaining fifteen kByte banks 1-15 accessed connection with four standard pins. external glue logic used synchronize external program memory access timing between directly connected microcontrollers address lines four indirectly connected standard pins bank selection bank 1-15 (A15 A18). interrupts used, always hard-wired interrupt vector addresses from 0000H 0100H lowest kByte bank becomes active therefore automatically deselects addressline P2.7/A15. exist code size overlapping within complete external program memory area. following figure gives overview
Code Memory
7FFFFH
Bank
kByte ext. Program Memory AREA
Bank
3FFFFH
Bank Bank Bank Bank
kByte
1FFFFH
Bank Bank Bank Bank kByte)
kByte
FFFFH 7FFFH 0000H
Data Memory
FFFFH 0000H
64kByte
Interrupt Vector Addresses 0000H 0100H
Figure External Memory Organization
Semiconductor Group AP0824 06.97
C5xx/80C5xx Bankswitching Capability
Hardware Description
following schematic shows example connect external kByte program memory kByte data memory C5xx/80C5xx microcontroller family. program memory, standard EPROM/EEPROM/FLASH used. static serves external data memory. x573 works address latch multiplexed port quad 2-line 1-line data multiplexer 74HC257 (standard device) used select between fixed bank (0000H 7FFFH) four standard pins PX.0 PX.3 bank 0-15 selection. microcontrollers P2.7/A15 address line used switching between bank bank 1-15 according characteristics external program memory. tied low, program memory accesses performed from external program memory. Port multiplexed address/data while port pins P2.0 P2.6 emits high address lines A14. P2.7/A15 connected SELECT input line 74HC257 selecting upper fifteen kByte memory bank 1-15 portions. Therefore, this configuration port port must used general-purpose ports.
P0.0 P0.7 (A0-7/D0-7)
x573
A0-7
A0-7
C5xx 80C5xx
P2.0 P2.6 (A8-A14) P2.7/A15
SELECT
Program Memory
D0-7
DATA Memory
D0-7
A8-14
A8-15
Standard Pins Bank 1-15 Selection
PX.0 PX.1 PX.2 PX.3
74HC257
kByte
kByte
P3.6
P3.7 PSEN#
Bank Selection
Figure Schematic External Memory Interface
Semiconductor Group
AP0824 06.97
C5xx/80C5xx Bankswitching Capability
following table shows logic table 74HC257. Table 74HC257 Logic Table Select
address line P2.7/A15 shows logic multiplexer 74HC257 always selects bank (A15 Every software jump interrupt service routine within hard-wired interrupt vector addresses 0000H 0100H uses this mechanism automatic deselection P2.7/A15. addressline P2.7/A15 shows logic multiplexer switched transparent corresponding four standard pins PX.0 PX.3. this way, every upper kByte program memory bank 1-15 accessed. time delay t257DELAY between changing SELECT input line 74HC257 updating corresponding output lines approximately
t257DELAY
Note: there used slower multiplexer types (e.g.not HC-Types), t257DELAY adapted corresponding data sheet value.
Semiconductor Group
AP0824 06.97
C5xx/80C5xx Bankswitching Capability
Software Proceeding
program memory software take care about hardware situation following list gives rough overview about recommended software items: selection upper bank 1-15 (see table always executed lowest kByte bank (located 0000H 7FFFH) setting corresponding standard pins PX.0 PX.3. Table Bank Selection Standard Pins PX.3 PX.2 PX.1 PX.0 selected bank [Dec] physical address range [Hex] allowed 8000 FFFF 10000 17FFF 18000 1FFFF 20000 27FFF 28000 2FFFF 30000 37FFF 38000 3FFFF 40000 47FFF 48000 4FFFF 50000 57FFF 58000 5FFFF 60000 67FFF 68000 6FFFF 70000 77FFF 78000 7FFFF
bank switching algorithm itself automatically performed software jump microcontrollers address range 8000H FFFFH. This software jump activates P2.7/A15 address line microcontroller therefore accesses fifteen upper kByte memory banks 1-15 external glue logic. Every software jump below microcontrollers address range 8000H FFFFH accesses physically lowest kByte memory bank from 0000H 7FFFH deselection P2.7/A15 SELECT address line. Therefore, combination PX.0 PX.3 allowed. software jump microcontrollers address range 8000H FFFFH this case would result access physical address range between 0000H 7FFFH bank
Semiconductor Group
AP0824 06.97
C5xx/80C5xx Bankswitching Capability
Direct bank switching within banks 1-15 allowed because multiplexer 74HC257 this case directly connects standard pins PX.0 PX.3 with program memory address lines A18. Every change PX.0 PX.3 then causes direct change corresponding program memory input address line, which allowed according characteristics timings microcontroller. Interrupt service routines should located lowest kByte memory bank RETI (Return from Interrupt) instruction interrupt service routine automatically branches back upper bank 1-15, where last source code been executed before. Software (sub-)routines bigger than kByte each. Software (sub-)routines should completely located within kByte memory bank. Branches fixed data tables stored upper program memory bank MOVC access should executed only within same upper bank from lower bank LCALL-routines have regard Therefore direct LCALL branches within different upper banks allowed.
Timing Considerations concerning External Program Memory Access
fixed characteristics external multiplexed interface C5xx/80C5xx family, simple program memory expansion using general purpose pins direct switching kByte bank possible. switching time general purpose synchronized address output time external program memory access. Therefore interface address output line P2.7/A15 used synchronize preprogrammed ports PX.0 PX.3 upper kByte memory bank 1-15 access. following, some considerations concerning external program memory characteristic timings found. condition external program memory parameter tACC (address output delay)
tACC tAVIV
where tAVIV (address valid instr. parameter found characteristics corresponding C5xx/80C5xx data sheets. program memory selection, time t257DELAY (see chapter regarded. valid instr. calculation 74HC257 configuration
tAVIV257 tAVIV t257DELAY tAVIV
Semiconductor Group
AP0824 06.97
C5xx/80C5xx Bankswitching Capability
tAVIV257
address valid instr.
Figure Program Memory Read Cycle following table, some data sheet values program memory parameter tAVIV257 (calculated with formula tAVIV257 tAVIV t257DELAY tAVIV found. Table Valid Instruction tAVIV257 fOSC [MHz] tAVIV257 [ns]
Conclusion
proposed solution shows efficent overcome kByte boundary problem C5xx/80C5xx architecture. With hardware efforts only small software restrictions, bankswitching ability opening code size limitation become feasible. This application example easily adapted code size ranges with more than kByte using more then four standard pins program memory expansion.
Semiconductor Group AP0824 06.97

Program Memory Expansion using Bankswitching Capability C5xx/80C5xx Fa

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