Comparators Voltage comparators high gain differential input-logic out

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Comparators Voltage comparators high gain differential input-logic out

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AND8176/D Applications NE521/522
Comparators Voltage comparators high gain differential input-logic output devices. They specifically designed open-loop operation with minimum delay time. Although variations comparator used host applications, uses depend upon basic transfer function. Device operation simply change output voltage dependent upon whether signal input above below threshold input. Comparator inputs customarily marked with plus minus signs indicate their polarity. example, circuit Figure produces logic level when non-inverting input more positive than reference voltage.
VREF VSIGNAL
than linear. Hence, input offset voltage defined comparators voltage required input force output logic threshold ensuing devices (1.2 TTL).
Input Offset Current
Imbalances input bias current arise from small variances junction geometry differential input amplifier. amps, imbalance referred input offset current.
Bias Current
with amps input structure comparators usually differential bipolar stage. Input bias current average input currents.
Common-Mode Range
LOGIC OUTPUT
Figure Basic Comparator Circuit
Definitions Many similarities exist between operational amplifiers amplifier section voltage comparators. fact, amps used implement comparator function frequencies. Thus, characteristic definitions presented here similar those reviewed amps.
Input Offset Voltage
When specifying voltage comparators, parameters common-mode range, which defined range voltages over which both inputs varied simultaneously without abnormal output voltage transitions device degradation. This parameter must kept uppermost designer's mind because reference signal voltages become common-mode signals threshold. ranges input signals thus must within common-mode range input amplifier.
Voltage Gain
with operational amplifiers, non-ideal comparator possesses some offset voltage. definition differs slightly that output structure comparators digital rather
Specifications voltage gain refer overall gain device, bulk which occurs amplifier section. general, higher gains would advantageous resolving smaller input signals. course, propagation delay suffers more severe saturation transistors. Typical gains output devices 5000 V/V. This gain provides output swing with input signal change reasonable accuracy, does contribute severely overload recovery delay.
Semiconductor Components Industries, LLC, 2005
November, 2005 Rev.
Publication Order Number: AND8176/D
AND8176/D
OUTPUT VOLTAGE
Propagation Delay
Voltage comparisons analog signals with reference voltage usually require that operation take little time possible. Long delays comparator cause pulse position error output since analog signal meantime changed value. frequencies delay small consequence, higher frequencies, transit time becomes intolerable. Design voltage comparator devices includes, prime goal, minimizing transit times. Propagation delay testing done under worst-case conditions. recovery from saturation varies, depending upon initial state amplifier overdrive. Worst-case conditions begin applying signal reference terminal. With signal applied, amplifier saturation direction. step input pulse signal line ±VOS will bring amplifier threshold level. Propagation delay this point undefined since output switched. attain output switching, small overdrive necessary. Propagation delay tested configuration such Figure input step function plus specified excess overdrive signal. This causes amplifier exercised from saturation direction saturation other worst-case propagation delay. Note that larger overdrive reduces delay time seen Figure overdrive causes delay, whereas overdrive improves transit time only measurement were made without initial saturation (less than mV/V threshold) delay time would less, decreased storage times unsaturated transistors.
SIGNAL 100mV PLUS OVERDRIVE 100mV
100mV 20mV 10mV OVERDRIVE
25oC THRESHOLD
INPUT VOLTAGE (mV)
TIME
Figure Response Time NE521 Comparator Various Input Overdrives
Figure Propagation Delay Test Setup
State- -the-of-Art Comparator design always been optimized four basic parameters. They are: High Speed Wide Input Voltage Range Input Current Good Resolution Unfortunately, these four parameters compatible. instance, gain input current improved using thinner diffusions higher beta, only expense input voltage range. Higher gain also means higher saturation increase delay time. becomes obvious that older comparators such were designed with best compromises mind using standard processing. method improving overall response adds gold doping processing flow. gold dopant causes decrease minority carrier lifetime which aids recombination process shortens saturation recovery time. Unfortunately, transistor beta adversely affected gold, causing slightly higher bias offset currents. until advent Schottky clamp that vast improvement speed without input degradation possible. very familiar term semiconductor industry, Schottky Barrier Diode's (SBD) location illustrated Figure
Figure Schottky Clamped Transistor
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AND8176/D
Schottky clamped transistor formed paralleling Schottky diode with base-collector junction transistor. Without clamp, base drive increased collector voltage falls until hard saturation occurs. this point collector voltage very near emitter voltage, stored charges junctions causes slow recovery from saturation after base drive been removed. forward voltage drop Schottky diode V-less than forward drop silicon diodes. This difference forward drop used placing diode across transistor base-collector junction. Schottky diode becomes forward-biased when collector voltage falls below base voltage. Excess base drive then shunted into collector circuit, prohibiting transistor from reaching classic saturation. With almost stored charge either transistor, there large reduction storage time. Thus, transistor switching time significantly reduced. cross sectional area Schottky diode shown Figure
SIS2 ISOLATION COLLECTOR CONTACT EMITTER CONTACT BASE CONTACT ISOLATION
Comparing Comparators Presently available comparator range from ultra fast SE/NE521 general purpose comparator fashioned from inexpensive amp. Selection device depends upon application which will used. Speed conversion often primary importance minimize pulse position errors high frequency signals. other times requirements much less stringent, allowing general purpose comparator. handy reference guide major parameters summarized Table necessary parameters chosen select proper device. general description comparator devices included here familiarize user with available devices their advantages.
NE521/522 Comparators
Processed with state- -the- Schottky barrier diodes, -of- -art NE521/522 series devices provide good input characteristics while providing fastest analog- -TTL -toconversion. Total delay from input output typically with guaranteed speed Additional features this device include dual configuration individual output strobes simplify system logic. NE522, although sacrificing some speed, features open-collector outputs party line wired-OR configurations additional system flexibility.
TYPE SUBSTRATE SCHOTTKY DIODE GUARD RING
Figure Schottky Clamped Transistor Geometry
Table Comparator Selection Guide (Parameters based min/max limits 25°C defined individual data sheet.)
Device NE521 NE522 LM311 LM319 LM333 LM393 Prop Delay (ns) 1300 1300 (mV) (mA) 0.05 0.05 0.05 IBIAS (mA) 0.25 0.25 0.25 Gain 5000 5000
Benefits Dual, very fast, standard supplies compatible, individual common strobe. Same NE521 plus open-collector outputs additional decoding. High common-mode input range, supply, strobe input, open-collector output. input bias, dual, supply, open-collector output. input bias, dual, supply, open-collector output. Same LM339 dual.
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AND8176/D
Applications High-speed comparators capable making logic decisions less than 10ns. They easily applied possess good input power supply noise rejection. with linear ICs, however, some preliminary steps should taken their use. General Precautions
Layout
provide means utilizing Schottky gate other system logic functions. strobe inputs used, they should connected output logic gate that always high, supply through resistor. They should never tied directly supply relatively minor spiking supply damage these inputs.
Common-Mode Signals
comparator capable resolving sub-millivolt signals. prevent unwanted signals from appearing signal ports, good physical layout required. high-speed design, ground planes should used guard against ground loops other sources spurious signals. high frequencies, hidden signal paths become dominant. Distributed capacitance particular nuisance. care taken isolate output from input, distributed capacitance couple millivolts into input, causing oscillation. Another source spurious signals ground current. Input structures relatively high impedance while gate structures comparators with large signal ground currents. this gate ground current allowed pass near input signal path, small impedances ground circuit will cause millivolt changes reference signal voltages producing errors, sustained oscillation, ringing, excessive VOS. ground plane arranged such that output currents flow near input areas highly recommended.
Power Supplies
Another general precaution that should always exercised power supply bypassing. mentioned, name game speed. Very high-speed gates used produce desired output logic levels. Maximizing response speed also requires higher current levels, giving rise power supply noise. this reason, good power supply bypassing very close device itself always mandatory. tantalum capacitor parallel with 1000 will prove effective most cases. Lead lengths should short physically possible preserve impedances high frequency.
Unused Inputs
Manufacturers specify maximum voltage range over which inputs taken. addition, maximum differential voltage that safely applied inputs specified. case NE521 comparator, differential voltage restricted less than with common-mode That these quantities interact cannot overlooked. instance, with both inputs common-mode restriction satisfied. VREF left signal input taken more than below ground because differential signal becomes important observe this maximum rating since exceeding differential input voltage limit drawing excessive current breaking down emitter-base junctions input transistors could cause gross degradation input offset current bias current parameters. also important note that response time specified common-mode voltage zero degrade when common-mode voltage approaches common-mode specification limits. Exceeding absolute maximum positive input voltage limit device will saturate input transistor possibly cause damage through excessive current. However, even current limited reasonable value that device damaged, erratic operation result.
Input Impedance
differential bias offset currents comparators minimized design. pointed amps, input resistance seen both inputs should equal. This reduces minimum contribution offset current threshold error. Unbalanced input impedance also adds offset error difference voltage drop across input resistances. Basic Applications basic comparator circuit transfer function were presented Figure When input exceeds reference voltage, output switches either positive negative, depending inputs connected. vast majority specific applications involve only basic configuration with change reference voltage. converters realized applying signal terminal voltage derived from ladder network other. Limit detectors likewise made from only very basic circuit. Both only small deviation from basic level detector.
Some currently available comparators such NE521 NE522 dual devices. Most often both sections these devices will utilized. Should system utilize device, unused inputs should biased known condition. high gain-bandwidth otherwise cause oscillations unused comparator section. impedance should provided from both unused inputs ground. resistor relatively high impedance then used supply differential input order insure comparator assumes known state. inverting input tied positive differential voltage gate output will low. strobe inputs then
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AND8176/D
Hysteresis
Normally saturated high low, amplifiers used voltage comparators seldom held their threshold region. They possess high gain-bandwidth products compensated preserve switching speed. Therefore, compared voltages remain near threshold long periods time, comparator oscillate respond noise pulses. instance, this common problem with successive approximation converters where differential voltage seen comparator becomes successively smaller until noise signals cause indecision. avoid this oscillation linear range, hysteresis employed from output input. Figure defines arrangement. Both positive negative feedback provided
Hysteresis occurs because small portion "one" level output voltage back phase added input signal. This feedback aids signal crossing threshold. When signal returns threshold, positive feedback must overcome signal before switching occur. switching process then assured oscillations cannot occur. threshold "dead zone" created this method, illustrated Figure prevents output chatter with signals having slow erratic zero crossings. shown Figure voltage feedback calculated from expression: VHYST where EOUT gate high output voltage. hysteresis voltage bounded common-mode range ability gate source current required feedback network. symmetrical hysteresis desired, additional inverting gate required comparator does have differential outputs. NE521 NE522 devices will require inverter. Care should taken selection inverter that propagation delay minimum, especially very high-speed comparators such NE521.
Line Receiver
EOUT NOTE: VHYST
Figure Level Detector With Hysteresis
OUTPUT 1V/cm
INPUT (10mV/cm)
Figure Level Detector With Hysteresis
Retrieving signals which have been transmitted over long cables presence high electrical noise perfect application differential comparators. Such systems automated production lines large computer systems must transmit high frequency digital signals over long distances. twisted-pair system driven differentially from ground, signals reclaimed easily differential line receiver. Since electrical noise imposed upon pair wires takes form common-mode signal, very high common-mode rejection NE521/522 makes unit ideal differential line receivers. Figure depicts simple schematic arrangement. NE521 used differential amplifier having logic level output. Because common-mode signals rejected, noise cable disappears only desired differential signal remains. Figure illustrates NE521 response mVP-P differential signal. Figure same signal been buried VP-P common-mode "noise."
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AND8176/D
STROBE EOUT CHARACTERISTIC LINE IMPEDANCE -EOUT UNLATCH ENABLE
Figure Line Receiver
EOUT VOLTS
circuit suffers degradation signal. desired, several NE522 comparators "wire-ORed," latched output built shown Figure NE521 comparator advantage wider bandwidth permit higher data rates.
TRANSFER CURVE
OUTPUT 2V/DIV.
-VTH
+VTH
Figure Double-Ended Limit Detector
INPUT 100mV/DIV. 20MHz
HORIZ. 100ns/DIV.
Each half NE522 referenced desired upper lower voltage limit producing desired transfer curve shown. Taking advantage dual configuration open-collectors NE522 minimizes external components connections.
Crystal Oscillator
Figure Line Receiver Response
device with reasonable gain made oscillate applying positive feedback controlled amounts. NE521 will lend itself crystal control easily, provided crystal used fundamental mode. Figure shows typical oscillator circuit.
OUTPUT 2V/DIV. -1/2
INPUT 2V/DIV. 1MHz COMMON MODE HORIZ. 100ns/DIV.
10pF -RADJ
CRYSTAL (FUNDAMENTAL MODE)
Figure Response During Common-Mode Noise Double-Ended Limit (Window) Detector
Figure Crystal Oscillator
Many system designs require that known when signal level lies between limits. This function easily accomplished with single NE522 package. schematic transfer curve circuit shown Figure
crystal operated series-resonant mode, providing necessary feedback through capacitor input NE521. resistor RADJ used control amount feedback symmetry. Oscillations will start whenever circuit disturbance such turning power supplies occurs. NE521 will oscillate MHz.
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AND8176/D
However, crystals with frequencies higher than about usually operated their overtones. build oscillator specific overtone requires tuned circuits addition crystal provide necessary mode suppression. spurious modes tuned out, crystal will oscillate fundamental frequency. Higher frequency oscillators could realized using input output mode suppression tuning. NE522 especially desirable since open-collector topology allows output collector-tuned readily.
Analog- -Digital Converter -toVIN (LSB)
(MSB)
There many types converter designs, each having merits. However, where speed conversion prime interest, multi-threshold conversion type used exclusively. apparent from Figure that conversion speed this design delay through comparator decoding gates.
INPUT V/cm HORIZ. 5ns/cm OUTPUT V/cm
VREF
Vmax)
OVER RANGE
Figure 3-Bit Parallel Converter
Figure Parallel Response
sacrifices which must made obtain speed number components, accuracy cost. number comparators needed N-bit converter 2n-1. Although NE521 provides comparators package, length parallel converters usually limited less than bits. Accuracy multi-threshold converters also suffers since integrity each dependent upon comparator threshold accuracy. implementation parallel converter -bit shown Figure with digital equivalent -bit analog input shown Figure
Reference voltages each developed from precision resistor ladder network. Values chosen that threshold half least significant bit. This assures maximum accuracy bit. apparent from schematic that individual strobe line duality features NE521 have greatly reduced cost complexity design. speed converter graphically illustrated photo Figure outputs have settled true mere after -bit input step arrived. output usually strobed into register only after certain time elapsed insure that data arrived. Sense Amplifiers Closely related comparator sense amplifier. Signals derived from many sources, such transducers, sufficient amplitude compatible with subsequent logic. then becomes necessary amplify convert signal levels, which responsibility sense amplifier.
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AND8176/D
Some transducers produce output current. remains, then, user convert these currents levels. terminating resistor from drain ground provides voltage output proportional current resistor size. Larger signals produced larger resistors; practice, resistors larger than avoided because increasing access time. Distributed capacitance forms time constant with this output resistance causing slow rise fall times when resistor large, adding access time. Virtually voltage comparator sense amplifier used. Since total time delays, sense amplifier most often fastest available. Semiconductors comparators NE521 NE522 ideal this application because input offset voltages very fast response. Using these Schottky clamped comparators significantly reduces total cycle time memory. Design sense amplifier network depends upon transducer used input characteristics sense amplifier. significant specifications given Table
Table Important Sense Amplifier Parameters
DEVICE (mV) (MIN) (mV) SPEED (ns) (VIN=100mV) GAIN 5000 5000
Consideration must first given differential input voltage requirements sense amplifier. required reference voltage calculated from relationship:
VREF VDIFF
Where transducer output current, sense amplifier bias current VDIFF minimum differential voltage switch sense amplifier. large systems, noise coupled into sense lines stray capacitance very troublesome. Judicious layout patterns with sense lines short possible will help, will always sufficient. method eliminating noise balance sense line shown Figure dummy line should parallel actual sense line close proximity possible. connected sense amplifier VREF point while other left open. normal sense line connected usual. Electrical noise imposed upon pair sense lines takes form common-mode signal will rejected sense amplifier. Signal currents sense line, other hand, form differential signals sense amp, causing output switch.
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AND8176/D
DATA
Figure Balanced Sense Line Reduce Noise
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Comparators Voltage comparators high gain differential input-logic out

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