General Description NIS6111 Simplified Block Diagram NIS6111 simp

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AND8174/D NIS6111 Better ORing Diode Operation Notes
General Description NIS6111 Simplified Block Diagram
NIS6111 simple reliable device consisting integrated control with RDS(on) power MOSFET, using hybrid technology. designed replace Schottky diodes ORing applications obtain higher system power efficiency. connected allow load sharing with automatic switchover load between more input power supplies. single NIS6111 able without flow. meet high current requirement i.e. NIS6111 designed drive more than four paralleled additional NTD110N02 MOSFETs. unique package design NIS6111 offers higher thermal efficiency minimize cooling requirements. This application note presents more details demonstration boards. Both them easily connected power sources loads test purpose.
Applications
Paralleled Redundant Power Supplies Telecommunications Power Systems High-Reliability, Distributed Power Networks
Reg_in (Pin Input internal voltage regulator. Bias (Pin Output internal voltage regulator. under normal operating conditions. provides power internal components only. external connections necessary this pin. Gate (Pin Gate driver output internal external N-Channel MOSFET. gate turn time typically Source (Pin Power input, connected system power source output. This anode rectifier. Drain (Pin Power output, connected system load. This cathode rectifier will common cathodes other rectifiers, when used high side configuration. UVLO Function: UVLO trip point 3.85 rising 3.65 falling bias supply. Before bias voltage reaches 3.85 UVLO disables gate driver. soon bias voltage reaches 3.85 more, UVLO enables gate driver.
Reg_in
Bias
Gate
Drain
Voltage Regulator
UVLO NTD011N02 MOSFET
Source
Figure
Semiconductor Components Industries, LLC, 2005
September, 2005 Rev.
Publication Order Number: AND8174/D
AND8174/D
Reg_in Typically
UVLO "1'' "0'' V_gate 3.65 3.85 V_cap
Figure
NIS6111 Basic Operating Circuit Sequence
BERS will function normal silicon rectifier there bias power applied Reg_in. order achieve full benefit BERS internal MOSFET, Reg_in must more than volts above source (anode) This level will disable UVLO supply voltage input regulator.
Reg_in Source V_cap Reg_in Drain V_gate
Timing Sequence: ORing applications, Reg_in should energized before forward current applied BERS. This recommended procedure allows gate drive control circuit respond quickly current polarity changes. permissible allow voltage Reg_in input power supply (PS), rise simultaneously. Reg_in trail voltage, these methods would allow body diode conduction during interval where Reg_in lower than plus threshold. This mode operation will damage device long power dissipation does cause maximum junction temperature NIS6111 exceeded. Under circumstance should Reg_in voltage more negative than source (anode). recommended that signal diode (1N4148) installed series with Reg_in number external MOSFETs recommended Table based upon airflow heat sink other than normal printed circuits board (PCB) installation. test data taken from demonstration board. specific system application already provides cooling flow metal heatsinking, then actual number added MOSFETs decreased from recommendation.
Table Recommended Selection External MOSFETs Based Load Currents
Under Flow Heat Sink Condition
NIS6111
Output Load
Recommended Selection Single NIS6111 NIS6111 NTD110N02 NIS6111 NTD110N02
Load Current Rating
NIS110N02 (Optional)
NIS6111 Three NTD110N02 NIS6111 Four NTD110N02
Figure Basic Operation Circuit
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AND8174/D
TEST CIRCUIT
V_reg_in Lead1 Vin_1 ECAP NTD110N02 ECAP Rsnub1 Vin_2 ECAP NTD110N02 Ceramic Reg_in Lead2 Source V_cap Drain Gate Jump_2 Csnub1 Lstray2 Ceramic Reg_in Source V_cap Drain Gate Jump_1
NIS6111
Lstray1 Output RLoad CFilter Ceramic
NIS6111
Rsnub2
Csnub2
Figure Test Circuit Basic Test Circuit
test circuit Figure test peak reverse current recovery time multiple power source operation. With Vin_2 Vin_1, load current will flow through paralleled MOSFETs. After switching (Shut Vin_2), paralleled MOSFETs will take over power transfer path, current will through them instead paralleled MOSFETs. Meanwhile, since Vin_2 (after shutting Vin_2) small amount reverse current will forced through MOSFETs, which will terminate conduction this switch. Note that ORing applications probable have instance where voltages Vin_1, Vin_2 iterated Vin_n, higher than Reg_in power source. signal blocking diodes must used series with each Reg_in pins protect them from reverse voltages. high switching speed BERS diode makes distributed circuit board inductance capacitance
become non-trivial. demonstration board loops provided monitor currents with suitable probe. Specific applications will have wire distribution inductances. demonstration boards specific systems have combination ceramic filter some aluminum electrolytic (E-cap) type capacitors. E-caps give some energy storage, their ESRs provide needed circuit damping resistance. type (KME, LXF, LXV) Farad value selected optimum damping factor. NIS6111 attendant NTD110N02's require some amount reverse current achieve turn-off. This will generate some energy stray inductance which must dissipated. demonstration board with four MOSFETs, (turn-off) current will about This generates about 12.5 mJoule stray inductance. snubber resistors Rsnub1, Rsnub2 capacitors Csnub1 Csnub2 must applied across BERS anode cathode absorb energy prevent undamped oscillations.
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AND8174/D
Bias Power Circuit Notes: ORing circuits applied protect power busses from event (short circuit) that well controlled. result, circuit must resistant unpredictable response external components. Most power supplies execute controlled power-down after overcurrent detected. possible that failing would respond predictably cause voltage spikes short circuit bounces open closed. BERS part, tolerate over voltage from bus. NIS6201 rated internal Zener. boost converter NCP1403 rated should have Zener protection diode parallel. Both these voltage boosters should have current limiting resistor series with respective power voltage their protection from over-shoot.
Using NIS6111 ORing circuits
NIS6111 ideally suited ORing application compared Schottky diodes, there subtle performance differences. Application note AND8189/D describes reverse current required switch NIS6111. reverse current will provided applications failing required power ORing design. BERS Difference: obvious advantage BERS over Schottky diodes low-loss, highly conductive switch path that provides. incredibly RDS(on) creates interesting situation. benefit thermal loss obvious. side effect highly conductive channel that relatively large currents flow either direction with extremely small driving voltage. There barrier voltage other effect that would give zero-current condition ability switch state device. Semiconductor NIS6111 very sensitive comparator carefully placed near FET. still requires about reverse current generate sufficient offset voltage that reset device state. Schottky, other diode device which junction, also barrier voltage that must overcome before current will flow. forward current Schottky diode falls approaches zero, diode forward voltage collapses zero effectively shuts conduction channel.
ORing Diodes All? ORing diodes costly they waste power. true that multiple power supplies will work outputs just wired together parallel. 5-volt AC/DC power supplies taken shelf wired together parallel will give five volts output when they both powered they share load very well. with highest set-point will provide almost current. them powered off, other will supply entire load current. will also bias output filter capacitor first (off) power supply. ORing diodes used single purpose; protect system power bus. power supplies failure output rectifier filter capacitors that causes short-circuit, then ORing diode protects system from being shorted. ORing diode will also prevent system from dumping charge current into powered-down supply that installed while system still This function more business hot-swap controller, also works with ORing diodes. ORing system works best design forced current sharing greatest utilization. ORing does protect individual power supplies from catastrophic failures. aware Schottky-specific design constraints: Schottky been used ORing some time. design test specifications used ORing applications have included non-ORing, junction diode properties validation. Schottky ORing diode characteristic zero-current switch-off expected parameter even though this feature important function ORing. Test procedures individual power supply de-activation method power-down forced OVP, then voltage that verified zero. This test method does validate ORing function, easier quicker perform. proper test method ORing diode requires that test unit power supply must shorted have output current over load (OCP) applied. proper test method hot-swap must have system powered functional with test previously removed from system. must "cold" have voltage output terminals. input power test unit must start test must remain full length test. test must begin with insertion connection cold power supply system. cold output stays near zero volts, ORing diode passes test. cold output forced some voltage higher than volts, diode fails test.
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AND8174/D
Detection Notes: some cases, overvoltage protection (OVP) forced during test validate that individual functional item test level. This test also validate that forced results shut-down detection that particular supply. most operating current ranges, BERS will probably have slightly higher positive ratio dynamic impedance than Schottky diode. Therefore test will reach threshold then shut down before exceeds upper voltage limit. However, power supply which shuts down will sink enough reverse current switch BERS ORing diode. disabled will stop driving current system does OVP, also supplying power even though outputs floating range normal voltage. good design practice, system designer must detection depend solely upon power supply output voltage means detecting power supply failures. Another design problem that found ORing systems with forced current sharing that power supplies starts over-voltage, drives power voltage. current sharing method would cause power supplies system raise their voltages together. Each power supplies threshold that will identical others. more power supplies could reach their separate limits shut down sequence. Only power supplies control loop fault cause chain reaction multiple shut downs.
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V_reg_in_1 1N4148 Drain Gate 3.32 NTD110N02 1N4148 Vin_2 +C24 Source V_cap 3.32 V_reg_in_2 NIS6111 +C12 V_cap Reg_in +C11 0.12 Source
Vin_1
DEMONSTRATION BOARD
BAS16LT1
mF/50 NIS6201
BAS16LT1 BAS16LT1 PWRGND COMP PWRGND VREG SIGGND DRIVE PWRGND
Drain Reg_in Gate NIS6111 0.12 NTD110N02
AND8174/D
Figure Demonstration Board Schematic
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BAS16LT1 BAS16LT1 BAS16LT1 PWRGND COMP PWRGND VREG SIGGND DRIVE PWRGND NIS6201 mF/50
Charge Pump Circuit (Optional)
Vdc, 1200 1500 Aluminum Electrolytic Capacitor, Type equivalent.
Charge Pump Circuit (Optional)
AND8174/D
DEMONSTRATION BOARD (continued)
NOTE: selection input output capacitors vary, based layout maximum load applications.
Figure
Figure Layout
Figure Bottom Layout
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AND8174/D
DEMONSTRATION BOARD (continued)
Table Figure present current sharing data different load conditions.
CURRENT RATING Table Current Sharing Test Results
Current Sharing Rating Load Current NIS6111 10.5 NTD110N02
NTD110N02 NIS6111
LOAD CURRENT Figure Current Sharing Load Current
Table Thermal Test Results
Under Flow Heat Sink Condition Thermal Data Load Current NIS6111 Temp (5C) NTD112N02 Temp (5C)
Reverse Current Recovery Time Test Results
Figure shows waveforms typical load condition reverse current recovery time Figure slope (di/dt) waveform (Ch3) function parasitic inductance capacitance system. With increasing current path length component spaces PCB, decreasing slope (di/dt).
Ch1: Gate Voltage NIS6111 V/DIV) Ch2: Output Voltage V/DIV) Ch3: Current Through NIS6111 (5.0 A/DIV)
Figure
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V_reg_in_1 JUMPER JUMPER NTD110N02 1N4148 Vin_2 JUMPER C101 C102 C103 C104 C105 R101 JUMPER D104 M101
1N4148
Vin_1 Source V_cap Drain Gate NIS6111 3.32 0.12 Reg_in
+C22
JUMPER
DEMONSTRATION BOARD
V_reg_in_2
NTD110N02 NTD110N02 +C120 C106 C107 C108 NTD110N02 JUMPER C117 IC101
BAS16LT1 BAS16LT1 NIS6201 PWRGND
BAS16LT1 SIGGND
COMP PWRGND
JUMPER JUMPER L101 L106 Reg_in Drain Gate +C121 C114 C115 C116
DRIVE PWRGND
Source V_cap
NIS6111 R105 C118 0.12
C109 C110
C111 C112 C113 NTD110N02 R102 JUMPER L103 JUMPER L102
AND8174/D
Figure Demonstration Board Schematic
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C125 D102 BAS16LT1 D103 BAS16LT1 BAS16LT1 IC101 NIS6201 PWRGND COMP PWRGND SIGGND DRIVE PWRGND R106 R107 C124 mF/50 Charge Pump Circuit (Optional) M104 M103 M102 C119
mF/50
Charge Pump Circuit (Optional)
NTD110N02 R103 NTD110N02 R104 NTD110N02 JUMPER L105 JUMPER L104
Vdc, 1200 1500 Aluminum Electrolytic Capacitor, Type equivalent.
AND8174/D
DEMONSTRATION BOARD (continued)
Figure
Figure Layout
Figure Bottom Layout
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AND8174/D
DEMONSTRATION BOARD (continued)
Table Figure present current sharing data different load conditions.
Table Current Sharing Test Results
Current Sharing Ratings NIS6111 12.4 13.5 M101 10.8 M102 10.6 11.5 12.5 M103
CURRENT RATING NIS6111 NTD110N02 (M103) NTD110N02 (M104) NTD110N02 (M101) NTD110N02 (M102)
LOAD CURRENT Figure Current Sharing Load Currents
Table Thermal Test Results
Under Flow Heat Sink Condition Load Current Rating Thermal Rating Typical
Reverse Current Recovery Time Test Results
Figure presents waveforms typical load condition reverse current recovery time
Conclusion
Devices Single NIS6111 NIS6111 NTD110N02 NIS6111 NTD110N02 NIS6111 Three NTD110N02 NIS6111 Four NTD110N02
application note describes NIS6111 device operation details demonstration boards.
Ch1: Gate Voltage NIS6111 V/DIV) Ch2: Output Voltage V/DIV) Ch3: Output Current (5.0 A/DIV)
Figure
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AND8174/D
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AND8174/D

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