Paul Shockman Contents SECTION 1.UNLOADED VOLTAGE LEVELS OPEN) SECTION

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Paul Shockman Contents SECTION 1.UNLOADED VOLTAGE LEVELS OPEN) SECTION

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AND8173/D Termination Interface Semiconductor Devices With (Current Mode Logic) OUTPUT Structure
Paul Shockman Contents SECTION 1.UNLOADED VOLTAGE LEVELS OPEN) SECTION 2.DIRECT CONNECT (DC) LOAD TERMINATED LINE SECTION 3.Cap Coupled (AC) LOAD TERMINATED LINE Vterm SECTION 4.CML INTERFACE INTERCONNECTS Introduction
This document will discuss general termination interface interconnection Semiconductor devices with Current Mode Logic (CML) OUTPUT Structures. long history using coupled emitter differential pair output structure with Emitter Follower (EF) shown Figure This classic output displays about internal impedance both HIGH output states. constant internal current, ICS, steered through side other switching transistors. Now, some devices available using outputs structures with internal impedance shown Figures Semiconductor devices offer back source termination impedance potential reduction external components. Information regarding Termination Devices with Emitter Follower (EF) OUTPUT Structure found AND8020.
Output Driver
Output Driver
Figure with CML, Current Mode Logic Output Structures
Figure with Emitter Follower Output, Output Structures
Semiconductor Components Industries, LLC, 2006
June, 2006 Rev.
Publication Order Number: AND8173/D
AND8173/D
SECTION UNLOADED DRIVER OUTPUT VOLTAGE LEVELS OPEN)
This coupled emitter differential pair output structure incorporates internal constant source bias, ICS, "tail current". unloaded open output voltages, VOPEN, result from internal current, ICS, steered through each collector resistor output transistors Figures output states, VoutOPEN HIGH VoutOPEN LOW, complementary. output side differential pair will present output voltage VoutOPEN ICS, drawn through complementary output side, VoutOPEN HIGH essentially current flow, IOFF, will drop essentially across thus remaining near VCC. Switching accomplished steering constant tail current from side other.
VoutOPEN HIGH (IOFF (eq. VoutOPEN (ICS (eq.
Where: Constant Current Source Bias Output Transistor Collector Resistor Unloaded (open) Outputs will present either VoutOPEN HIGH voltage level near VoutOPEN voltage level active complementary signal pair will produce characteristic parameters Table
Table DRIVER LEVELS (with Open, Unloaded Outputs)
Parameter VoutOPEN HIGH VoutOPEN VoutOPEN VoutOPEN (Note VoutOPEN DIFF Each line measured single-ended. Level 1600 mVpp mVpp Unit
Unloaded Output Driver
Unloaded Output Driver VoutOPEN HIGH VoutOPEN
VoutOPEN VoutOPEN HIGH
Figure Open Output Driver Currents Levels HIGH, LOW)
Figure Open Output Driver Currents Levels LOW, HIGH)
AND8173/D
SECTION DIRECT CONNECT (DC) LOAD TERMINATED LINE
When output connected current source (loaded), driver's internal constant tail current, ICS, draws from active side transistor through internal (collector resistor), also through receiver's (RT) termination current source. typical receiver termination (internal external termination resistor)
shown Figures Both output lines differential pair should have equal loads maintain balanced dynamic signal loading driver. complementary side draws essentially zero current, Ioff remains near VCC.
Receiver
Loaded Output Driver
VoutLOADED HIGH
VoutLOADED
Figure Output (with Direct Connect Load Termination line VCC), Currents Levels HIGH, LOW)
Receiver
Loaded Output Driver VoutLOADED
VoutLOADED HIGH
Figure Output (with Direct Connect Load Termination line VCC), Currents Levels LOW, HIGH)
AND8173/D
driver parallel receiver (RT) VCC, presenting R(EQ) active side's constant tail current, will drop total about below VoutLOADED LOW. complementary output side, VoutLOADED HIGH, essentially current flow, IOFF, remains near VCC.
VoutLOADED HIGH (IOFF R(EQ)) (eq. VoutLOADED (ICS R(EQ)) (eq.
With differential Output lines loaded each terminated (RT) driver, voltage levels present either VoutLOADED HIGH level VoutLOADED receiver. active complementary signal pair produces characteristic parameters Table
Table DRIVER LEVELS (with Direct Connect Load Termination VCC)
Parameter VoutLOADED HIGH VoutLOADED VoutLOADED VoutLOADED (Note VoutLOADED DIFF Each line measured single-ended. Level mVpp mVpp Unit
Where: Constant Source Bias IOFF Zero Current Side Output Transistor Collector Resistor
AND8173/D
SECTION Coupled (AC) LOAD TERMINATED LINE Vterm
driver receiver using cap, coupled (AC) differential interconnect receiver side termination (RT) requires receiver side rebiasing, Vterm, signal lines shown Figure coupling cap, value load impedance constitute network affecting signal edges. coupling (AC) restricts frequency response require coding maintain sufficient crossing density. This coupled pair Figure will produce characteristic signal levels Table
Table DRIVER LEVELS (with Coupled Termination line VCC)
Parameter VoutAC LOADED HIGH VoutAC LOADED VoutAC LOADED VoutAC LOADED (Note VoutAC LOADED DIFF Each line measured single-ended. Receiver Vterm Receiver Level Vterm Vterm Vterm Unit mVpp mVpp
Driver
VoutACLOADED HIGH Vterm +200 VoutACLOADED LOW= Vterm -200
Figure Output with Coupling (AC) Load Termination Vterm Vterm SUPPLY
Vterm bias supply associated with receiver Figure needs accommodate receiver common mode range bypassed enhance rejection common mode noise. Typically, Vterm bias supply connected directly from receiver pins whether internal external driver. When internal, connect fixed value (RT) resistors singulated combined. external, termination resistor (RT) value changed accommodate specific transmission line impedance. external reference supply, Vterm, generated resistor divider network spanning from supplies, with appropriate bypass capacitance, CBP, shown Figure Typically bypass capacitor value range from 0.01 0.001 Resistors should generate appropriate common mode voltage receiver. Current through should least receiver typical input current both lines.
External Vterm Vterm
Driver
Receiver
Figure Typical Vterm Supply Divider Network
AND8173/D
Alternatively, receiver without internal (RT) resistors terminated biased using Thevenin parallel equivalent network. Both impedance matching rebias simultaneously accomplished solution resistor resistor shown Figure each complementary lines. AND8020, Section Thevenin Equivalent Parallel Termination equations generating values LVPECL receivers offer wide range accepted common mode value solutions inputs operating differential interconnect. Selecting common mode value would satisfy standard receiver. Table gives values typical pullup resistor R1'), pulldown resistor R2'), resulting Vrebias voltage when using common mode voltage impedance matching transmission media with
External Vterm
Driver
Vrebias
Receiver
Vrebias
Figure Thevenin Parallel Termination Scheme
Table Typical REBIAS IMPEDANCE MATCHING RESISTOR NETWORK VALUES
Resistor (R1') (R2') Vrebias |VCC |VCC |VCC 96.15 104.16 Unit
AND8173/D
SECTION INTERFACE INTERCONNECTS Driver Direct Connect (DC) LVPECL
Semiconductor Logic Devices with OUTPUT Structures easily interconnects directly (DC)
typical LVPECL receiver input similar power supplies. direct (DC) interface interconnect shown Figure
LVPECL Receiver
Driver
Vterm (Internal External)
VoutLOADED HIGH Vterm VoutLOADED
Figure Output with Direct (DC) Interconnect Termination Vterm
receiver have either internal external (RT) termination resistors, these resistors singulated combined pinout. external, termination resistors (RT) value changed accommodate transmission line impedance. Vterm supply (Figure connects (RT) termination resistors determines receiver bias level. proper Vterm bias must selected receiver comply with common mode specifications, such VIHCMR VCMR. Most devices will tolerate Vterm while others spec signal HIGH level, VIHmax (consult device data sheet) requiring appropriately lower
Vterm supply. lower Vterm supply affects receiver VoutHIGH VoutLOW levels. typical Semiconductor Device with OUTPUT Structure, directly (DC) driving internally terminated LVPECL input with various Vterm values, produces characteristic swing amplitude, VoutPP (each line measured single ended), common mode voltage, VoutCM, presented Table Both driver LVPECL receiver were supplied Note insensitivity output swing changes Vterm supply ranges from typical termination voltage Emitter Follower structures.
Table DRIVER LEVELS (WITH DIRECT CONNECT TERMINATION LINE Vterm)
Vterm Each line measured single-ended VoutCM 2.95 2.75 VoutHIGH 3.25 3.10 2.85 VoutLOW 2.95 2.85 2.55 VoutPP (Note 0.300 0.300 0.295 Unit
AND8173/D
Driver Coupled (AC) Various Supplied ECL: PECL, LVPECL, LVNECL, NECL
Semiconductor Devices with OUTPUT Structures easily interconnect with coupling
(AC) type receiver inputs operating with different supply modes such shown Figures Vterm supply used bias receiver input lines. also Vterm Supply, Figure Table
Vterm
Driver
PECL Receiver
VHIGH +200 VLOW -200
Figure PECL (VCC Vterm
Driver
Vterm
LVPECL Receiver
VHIGH +200 VLOW -200
Figure LVPECL (VCC Vterm
AND8173/D
Driver Vterm NECL LVNECL Receiver
-5.0 -3.3 VHIGH +200 VLOW -200
Figure NECL (Vterm -5.0 -3.3
AND8173/D
Driver Coupled (AC) LVDS
Driver interconnect LVDS (LVDS, BLVDS, M-LVDS, GLVDS, LVDM) compliant receiver requires coupled (AC) interface. Typically, (RT) line impedance matching termination Vterm used shown Figure will produce VHIGH about 1.33 VLOW with amplitude mVpp (each line measured single-ended). Vterm reference.
Resistor (R1') (R2') Vrebias |VCC VEE|
(RT) line impedance matching termination resistors external, termination resistor scheme modified using Thevenin parallel scheme shown Figure Thevenin parallel impedance matching resistor network values rebias voltage LVDS coupled receiver with given Table
Table LVDS IMPEDANCE MATCHING RESISTOR NETWORK VALUES REBIAS VOLTAGE
|VCC VEE| |VCC VEE| Unit
Driver
LVDS Receiver
Vterm VHIGH X1.33 VLOW X1.00
Figure LVDS (Vterm
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AND8173/D

Paul Shockman Contents SECTION 1.UNLOADED VOLTAGE LEVELS OPEN) SECTION

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