INTRODUCTION APPLICATION When comes communicating over serial bus
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AND8148/D Using MC74HC589A True SPI-Bus Peripheral
INTRODUCTION APPLICATION
When comes communicating over serial bus, there three main methods, (Serial Peripheral Interface), Microwire I2C. choice always easy make, often designer must whichever hardware available micro-controller peripherals. Eck1 claims that that three common interfaces, easiest write code for, fastest protocol. SPI-bus invented 1980s simple inexpensive communicate with peripherals, with minimum code absolute simplicity receive function. SPI-bus synchronous, with "master" device responsible sending clock signal. most expansive form consists wires, (Serial Clock), MISO (Master Slave Out), MOSI (Master Slave In), (Slave Select). MC74HC589A MISO (slave) device only. will interfere with other master devices system, however there other masters, system reduces MISO line, line n-number lines. lines either single line controlling single device multiple lines multiple devices. Latch Clock NLSF589 operation. addition, needs provide logic control action register, either Parallel Load Serial Shift, this action explicit requirement SPI, however part will function properly, without setting this requires high transition move data that been stored shift register, into output latch. Although device active Enable pin, necessary this pin, hard wired low.
diagram below shows MC74HC589 used detect closures remote location. only MISO port MCU. closures applied pins A-H. There determine that either been opened closed, designer must "polling" technique. designer initializes data, then goes shift register, reads data, looks change from prior state. designer must return port, update information regular basis e.g. every 30ms. "HC589" parallel inputs, along with various pins SPI. diagram shows switches with pull resistors parallel port (A-H), designer just needs supply logic level port. De-bounce explicitly required hardware. software engineer might want return port poll again, perhaps 10ms later, closure records same data. actual software algorithm will left designer. further aspect design requires rise fall times clock signals observed. supply voltage rise time must assure clock recognized change state properly. Some designers eliminate noise using filtering data clock lines. recommendation hysteresis gate(s) lines that rise fall time met. circuit shown operating only requirement that both shift register function same voltage, unless designer explicitly handles differences with logic level translators. diagram shows (Pin asserted with logic level low, latch clock (Pin being asserted with rising edge applied this pin. designer trying save wires, single gate inverter MC74HC1G14 create rising edge from output enable logic level. more"589s" cascaded more bits data. this done, reader should approach this carefully reading Semiconductor Application Note: AND8144/D observing timing issues.
Eck, Serial Interface Embedded Design, Circuit Cellar Online- Jan., 2000
Semiconductor Components Industries, LLC, 2006
May, 2006 Rev.
Publication Order Number: AND8148/D
AND8148/D
through
MC74HC589A
Wire
Data Clock
MISO
GPIO
Latch Clock
Figure Application Diagram
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AND8148/D
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