INTRODUCTION most modern circuits, lower input current harmonics impro

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AND8147/D Innovative Approach Achieving Single Stage Step-Down Conversion Distributive Systems
INTRODUCTION most modern circuits, lower input current harmonics improve input power factor, designers have historically used boost topology. boost topology operate Continuous Conduction Mode (CCM), Discontinuous Conduction Mode (DCM), Critical Conduction Mode. Most applications using boost topology designed operate over universal input voltage range (85-265 Vac), provide regulated (typically Vdc). most applications, load operate from high voltage bus, DC-DC converter used provide isolation between source load, provide voltage output. advantages this system configuration Total Harmonic Distortion (THD), power factor close unity, excellent voltage regulation, fast transient response isolated output. major disadvantage boost topology that power stages required which lowers systems efficiency, increases component count, cost, increases size power supply. Semiconductor's NCP1651 (www.onsemi.com) offers unique alternative Power Factor Correction designs, where NCP1651 been designed control circuit operating flyback topology. There several major advantages using flyback topology. First, user create voltage isolated secondary output, with single power stage, still achieve input current distortion, power factor close unity. second advantage, compared boost topology with DC-DC converter, lower component count which reduces size cost power supply. Traditionally, flyback approach been ignored applications because perceived limitations such high peak currents high switch voltage ratings. This paper will demonstrate novel control approach incorporated NCP1651 design, coupled with advances discrete semiconductor technology that have made flyback approach very feasible range applications.
Controller Analysis
NCP1651 operate either Continuous Discontinuous mode operation. following analysis will help highlight advantages Continuous versus Discontinuous mode operation. table below defines conditions from which comparison will made between modes operation.
Table
85-265 Vrms (analyzed Vrms input) Efficiency Freq Transformer turns ratio
Continuous Mode (CCM)
force inductor current continuous over majority input voltage range (85-265 Vac) primary inductance, needs least Figure shows typical current through primary winding flyback transformer. During switch period, this current flows primary during switch off-time, flows secondary.
Iavg
TIME
Figure
Therefore, peak current calculated follows:
Iavg (1.414
(eq.
Semiconductor Components Industries, LLC, 2004
February, 2004 Rev.
Publication Order Number: AND8147/D
AND8147/D
where:
1.414 Iavg
(eq. (mA)
1.414 (eq.
selected operating condition:
6.15
(eq.
1.414 1.414 6.15 3.35 (eq.
analysis converter shows that peak current operating 3.35
Discontinuous Mode (DCM)
FREQUENCY (MHz)
discontinuous mode operation, inductor current falls zero prior switching period shown Figure
Iavg
Figure Continuous Conduction Mode
Referring Figure switching frequency, harmonic (200 kHz)
TIME
Figure
ensure DCM, needs reduced approximately
1.414 1.414 5.18 6.23
(eq.
FREQUENCY (MHz)
results show that peak current flyback converter operating Continuous Conduction Mode about half peak current flyback converter operating Discontinuous Conduction Mode. lower peak current result operating lowers conduction losses flyback MOSFET.
Current Harmonics Analysis
Figure Discontinuous Conduction Mode
Refer Figure second harmonic (200 kHz)
Results
second result running higher input current distortion, Electromagnetic Interference (EMI), lower Power Factor, comparison CCM. While higher peak current filtered produce same performance result, will require larger input filter. simple Fast Fourier Transform (FFT) (ORCAD) Spice provide comparison between harmonic current levels DCM. harmonic current levels will affect size input filter which some applications required meet levels IEC1000-3-2. SPICE model, front filtering added result analysis could compared directly.
From result analysis apparent that flyback converter operating half peak current, tenth fundamental (100 kHz) harmonic current compared flyback converter operating DCM. results lower conduction losses MOSFET secondary rectifying diode, smaller input filter. negative side operation, flyback transformer will larger because required higher primary inductance, leakage inductance will higher affecting efficiency because leakage inductance energy that must absorbed during controller time.
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AND8147/D
Some advantages operating include lower switching losses because current falls zero prior next switching cycle, smaller transformer, general smaller transformer should result lower leakage inductance less energy absorbed snubber.
Transformer Turn Ratio
flyback transformer turns ratio affects several operating parameters, secondary side peak current MOSFET drain source voltage (VDS) during controller time, refer Figure application schematic. peak secondary current prim Where transformer turns ratio, application Using analysis versus DCM, peak secondary current 3.34 13.4 6.23 24.9 It's clear from analysis that higher turns ratio, there higher corresponding secondary side peak current resulting higher conduction losses output rectifier. second effect turns ratio MOSFET VDS. MOSFET during time 1.414 Vspike where: Vrms output voltage forward voltage drop across output diode Vspike voltage spike transformer leakage inductance turns ratio this equation determines output voltage reflected back primary, Vf)n. second effect turns ratio transformer leakage inductance, which effects Vspike. leakage inductance related coupling between primary secondary transformer. turns ratio increase, there more turns transformer, unless designer careful their core geometry selection winding technique, result will higher leakage inductance. minimize leakage inductance, core with wide winding window should used; this will reduce number primary secondary layers. addition, interleaving primary secondary winding will increase coupling. example will help illustrate point. application transformer required primary turns (two layers) secondary turns single layer). manufacturer transformer wound primary turns, then turn secondary, then remaining primary turns. result measured leakage inductance
second transformer wound with entire primary turns (two layers), then turn secondary, measured leakage inductance increased reason increased leakage inductance poor coupling between primary secondary. Once leakage inductance reduced, verify that voltage spike turn (Vspike) will exceed your MOSFET VDS. MOSFET application rating provide safety margin least under worst case conditions: Vspike: Vspike Vmargin 1.414 1.414 0.7) application snubber circuit designed limit MOSFET Vpk. Refer Figure waveform. energy stored transformer leakage inductance Ipk_
Figure
above analysis examples illustrate effects transformer turns ratio secondary side peak currents MOSFET turn off. Careful attention should taken when trading turns ratio, primary inductance duty cycle.
Output Voltage Ripple
second consideration when using flyback topology that output voltage ripple contains secondary transformer) components, traditional high frequency ripple associated with flyback converter, rectified line frequency ripple (100 Hz). high frequency ripple calculated
DVcap2 Vesr2
(eq.
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AND8147/D
DVcap Ioavg
1.50 (eq. 1.00 RIPPLE 0.50 0.00
Iped Ioavg DVesr DVesr 13.38 0.015 0.20
(eq.
where: transformer turns ratio peak current (secondary) (13.38 Apk) Iped pedestal secondary current (10.5 Apk) output capacitance (3000 total) output capacitor equivalent series resistance (0.015_) Toff (3.92
13.38 10.5 3.92 3000 0.0156
(eq.
-0.50 -1.00 -1.50
DEGREES
Figure Output Ripple Envelope
Hold-Up Time
Solving high frequency ripple component output
0.01562 0.202 0.20
(eq.
secondary output voltage used distributed bus, designer elect size output capacitor hold-up times, versus ripple. output capacitors calculated
Vnom2
(eq.
frequency portion ripple:
Iavg Iavg 0.637 2.95 0.637
(eq.
where: Pout maximum output power required hold-up time selected cycle line 16.67 Vnom nominal output Vmin
16.67 3000
(eq.
output voltage ripple divided into increments over cycle (180°) sinusoidal ripple voltage with respect phase angle
0.637 fline
(eq.
above calculations output voltage ripple hold-up time, coincidence that same value output capacitance selected both cases.
NCP1651 Features
calculate total output voltage ripple: Vripple total
DVripple total DVcap2 DVesr2 0.637 fline
(eq.
Figure output voltage ripple function phase angle plotted. results show that long capacitor(s) with used, that output voltage ripple will dominated frequency ripple (100 Hz).
NCP1651 internally provides necessary features that typically seen controller, plus some features normally found. example NCP1651 high voltage start-up circuit, which allows designer connect NCP1651 directly high voltage bus, eliminating bulky expensive start-up circuitry. After power applied circuit, high voltage biased current source provide current start-up power. high voltage start-up circuit enabled current drawn from rectified line charge cap. When voltage reaches turn point UVLO circuit (10.8 nominally), start-up circuit disabled, circuit enabled. With NCP1651 enabled bias current increases from
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AND8147/D
standby level operational level. divide-by-eight counter preset count that start-up chip will operational first cycle. second cycle counter advanced chip will allowed start this time. Refer Figure
10.8
STARTUP ENABLE
OUTPUT ENABLE ENABLE OUTPUT CURRENT FB/SD
SHUTDOWN START-UP CURRENT LIMIT SHUTDOWN START-UP SEQUENCE
Figure
addition providing initial charge capacitor, start circuit also serves timer start-up, overcurrent, shutdown modes operation. nature this circuit, this chip must biased using start-up circuit auxiliary winding power transformer. Attempting operate this chip fixed voltage supply will allow chip start. shutdown mode, cycle held count state until shutdown signal removed. This allows repeatable, fast restart. Figure timing diagram. unit will remain operational long voltage remains above UVLO under voltage trip point. voltage reduced under voltage trip point, operation unit will disabled, start-up circuit will again enabled, will charge capacitor turn voltage level. this point start-up circuit will turn unit will remain shutdown mode. This will continue next seven cycles. eighth cycle, NPC1651 will again become operational. voltage remains above undervoltage trip point unit will continue operate, unit will begin another divide-by-eight cycle.
purpose divide-by-eight counter reduce power dissipation chip under overload conditions allow recycle indefinitely without overheating chip. critical that output voltage reaches level that allows auxiliary voltage remain above UVLO turn-off level before discharged level. bias voltage generated inductor winding fails exceed shutdown voltage before capacitor reduces UVLO under voltage turn-off level, unit will shut down into divide-by-eight cycle, will never start. this occurs, capacitor value should increased. CONCLUSION will ultimately designer perform trade-off study determine which topology, Boost versus flyback, Continuous versus Discontinuous Mode operation will meet system performance requirements. recent introduction NCP1651 allows system designer additional option yielding less expensive, smaller solution.
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1N4006
1N4006
1N4006
1N4006 1500 1500 MUR1620CT 0.001 AZ23CK18
BAS19LT1
0.68
1N4006
MUR160 40.4 0.12 MC3303 Vref FB/SD ACin ACref Start-up
Input
Output
NCP1651
AND8147/D
Figure Application Schematic
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Ramp Lavg littr 11.2 0.001 0.001
0.022
0.022
0.01 TL431
AND8147/D
Notes
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AND8147/D
Semiconductor registered trademarks Semiconductor Components Industries, (SCILLC). SCILLC reserves right make changes without further notice products herein. SCILLC makes warranty, representation guarantee regarding suitability products particular purpose, does SCILLC assume liability arising application product circuit, specifically disclaims liability, including without limitation special, consequential incidental damages. "Typical" parameters which provided SCILLC data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. SCILLC does convey license under patent rights rights others. SCILLC products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure SCILLC product could create situation where personal injury death occur. Should Buyer purchase SCILLC products such unintended unauthorized application, Buyer shall indemnify hold SCILLC officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that SCILLC negligent regarding design manufacture part. SCILLC Equal Opportunity/Affirmative Action Employer. This literature subject applicable copyright laws resale manner.
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AND8147/D

INTRODUCTION most modern circuits, lower input current harmonics impro

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