There number very popular shift registers available solve Input Output

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There number very popular shift registers available solve Input Output

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AND8144/D CMOS Shift Registers Solve Issues Automotive Applications
There number very popular shift registers available solve Input Output problems very economically. automotive industry, particular, often needs send data from switches micro-controller that several meters away. Sending many parallel terribly inefficient. Using dedicated micro-controller still expensive solution. available industry-standard shift registers make very economical solution this problem. This article will point pitfalls using these devices properly. choice standard family generally first decision. families most widely used automotive uses, Metal Gate CMOS Family also known "4000" family High Speed Logic "HC" family. Semiconductor offers many part types these families, also some newer, faster lines. These applications usually demand more bits information, representing position mechanical switch, speed usually consequence. Since high speed serial might cause RFI1, clock rate sufficient even preferable high speed data transmission. However, many designers attempting keep minimum unwittingly introduce delays system that wreak havoc timing cause unexpected results. beauty shift register simplicity, there critical parameters that must taken into account. shift registers have "set-up hold" time. assumed that board running from nominal, with on-board regulator. MC74HC165ADR2 selected shift register. This device rated automotive temperatures, inexpensive available small packages. This device quite flexible, with bits parallel inputs, Q-Bar outputs, clock inhibit, ability string several registers together, create string parallel inputs desired. Since
Radio Frequency Interference MISO Master Slave
microcontroller providing clock signal, there need clock recovery. This design compatible MISO2 mode. system designer choose port simply pins microcontroller, while "bit-banging". Since polling shift register, simple circuit will suffice parallel inputs. data transition, that necessary come back poll this data again, before taking action. polling rate should sufficient de-bounce. clock rate, only takes read bits data. capacitors need have parallel resistors bleed charge after switch opened. This combination filtering polling very lost cost implementation de-bounce. reasons RFI, maximum data rate will 250kHz. This well below rating part, even 125°C. device set-up hold time specification that requires that data present valid proper logic level state) Fig. shows "HC165" expand bits into wire serial bus. must "poll" shift register desired rate, every polling consists setting High, holding High, "clocking" pulses. After each clock pulse data will present later. that necessary read this data software designer send clock pulse, wait sufficient time clock pulse arrive shift register transferred output, this case then read data. does this times reads bits. highly recommended that designer Schottky diodes resistor form time constant, limit noise lines. This very straight-forward. only critical point wait long enough, make sure data read valid. preferred solution recognize data, valid after receiving same data twice, sequence.
Semiconductor Components Industries, LLC, 2004
January, 2004 Rev.
Publication Order Number: AND8144/D
AND8144/D
HC165
+5.0
Figure
Cascading Devices "HC165" pins that make convenient cascade, however, designer careful, this circuit result data that incorrect, producing strange results data. designer careful, inadvertently reading wrong data. What's worse, this show under normal conditions, missed production environment, result units failing Minnesota Arizona. applications, logic level high (VIH) specified logic level (VIL) specified
Clock Pulse
actual transition somewhere between these voltages, actual trigger point specified. designer must make assumptions about this point. "165" device supports maximum rise time clock signals. rise time [400 nsecs, slew rate ns/volt. every device switched exactly Vcc, slow rise time would matter. only safe assumption however, that trip point clock between Volts, this puts nsecs ambiguity when clock strobes data, this ambiguity must taken into account.
"Read Window"
Figure
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AND8144/D
Even though edge rate meets specification, problem arises when more devices present. part "clock" wrong data serial mode. Data read sending series clock pulses equal number bits shift registers etc.). Figure shows typical shape waveform used. With slow edge rate likely create RFI. When designer connects more circuits that have different threshold points, problem occurs. that known certain logic level below logic level above "3.5". device actual threshold second device threshold 2.9, this entirely within specification this part. Should higher threshold device second device lower threshold device first, strange problems occur. With first device having lower threshold will "clock" data earlier than second device. trying read data, problems with first bits however when clock occurs, supposed taking previous register. data could easily incorrect, this represents signal lower your window, Minnesota, temperatures this real problem.
HC14
+5.0
HC165 +5.0
HC165
Figure
Improving Circuit clocking actions were take place simultaneously, data that second register sees that which there after previous clock. problem occurs first shift register "clocks" data significantly earlier than second. more than registers, same problem occurs from unit etc. excellent solution shown Figure This improvement involves adding Schmitt Trigger Input create well defined known edge clock. output rise time guaranteed faster than input signal. With strong, well defined signal feeding more
clocks, ambiguity clock signal trip point, reduced factor Since Schmitt Trigger individual devices each package, will more devices create some added delay. This will assure that design functions properly. goal make sure that data presented first device data that desired. making sure that receives clock pulse earlier than sure that data correct ready loaded. Figure shows Schottky diodes, Schmitt Trigger devices delay circuit being used.
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AND8144/D
Summary biggest factor solving problem making sure that both (all) registers clock their data appropriate time. necessary have fast rising edge rate clock reduce ambiguity switch points multiple devices. Since this action causes RFI, previously noted, solution buffer circuit board near shift registers. recommended circuit adds MC74HC14 package with hysteresis inverters. Output rise time will worst case. ambiguity owing different thresholds will only Since there more inverters package design further improved using some otherwise unused gates. gates cascaded series between shift registers, this will least another delay between circuits, assuring even further that there will false clocking. further improvement would package clamp diodes input, help eliminate large noise pulses ESD. These Schottky diodes fast have threshold, protect HC14 from damage keep noise minimum. design calls devices instead then instead using inverters data designer uses one, that would needed generate opposite going pulse. extra inverters would available adding delay. small value resistor could easily added form small time constant, with input capacitance. example resistor would approximately delay, when coupled (assumed) input gate. Although this accurate, right direction helps assure correct timing. Recommended Input Circuit
BAT51 74HC14
Figure
Conclussions using cost shift registers, micro-controller have expanded over wire bus. Timing these circuits important, essential that relationship between clocks data appropriate. circuit will improved greatly adding package Hex-Schmitt gates re-establish clock edge, with fast rise time. adding more gates between shift registers, sure that first device second device reading data appropriately. Lastly, highly recommended package Schottky diodes inputs long leads, prevent possible issues with large noise spikes. Schmitt devices take care timing small noise spikes.
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AND8144/D

There number very popular shift registers available solve Input Output

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