NSBMC290 Burst Mode Memory Controller User Application Note TABLE

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NSBMC290 Burst Mode Memory Controller User Application Note TABLE

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NSBMC290 Burst Mode Memory Controller
NSBMC290 Burst Mode Memory Controller User Application Note
TABLE CONTENTS DISTINCTIVE FEATURES Impact System Design Am29000 Access Protocol Support Memory Interface Support Buffer Strategies LOCAL CHANNEL PROTOCOL SUPPORT Simple Access Pipelined Access Burst Access Establishing Burst Mode Access Burst Suspension Burst Pause Terminating Burst Access MEMORY REQUIREMENTS Memory Refresh Memory Performance Requirements Pre-charge Time Access Time from Pre-charge Time Access Time from Write Cycle Restrictions SYSTEM INTERCONNECT Signal Description Local Channel Interface Memory Interface Buffer Control Signals Control Signal Interpretation Control Signal Interpretation Control Signal Interpretation Control Signal Interpretation Buffer Interconnect Strategies Nibble Wide Memories with ``245'' Style Buffers Wide Memories with ``245'' Style Buffers Enhanced Performance using Nibble Wide Devices Single Cycle Burst Write with Wide Devices Using Wide Devices with Am29C983 Expanding Memory Size Mode Mode Mode Mode
National Semiconductor Application Note July 1993
SOFTWARE DESIGN General Considerations Dynamic separation Instruction Data spaces Software Configuration NSBMC290 APPENDIX PROGRAM SAMPLE CONFIGURATION
APPENDIX NSBMC290 Am29000 INTERCONNECT (PGA) APPENDIX (PGA) APPENDIX (PGA) APPENDIX LIST SORTED SIGNAL NAME LIST SORTED NUMBER QUAD FLATPAK PIN-OUT
APPENDIX RECOMMENDED SYSTEM CLOCK GENERATOR DISTINCTIVE FEATURES NSBMC290 memory controller designed specifically Am29000 based systems NSBMC290 functionally equivalent V29BMC specific nature such systems preclude NSBMC290 from being general purpose device However within constraints targeted applications imposes architectural restrictions Every effort been made preserve application flexibility while still achieving principal design objective support Local Channel Protocol Impact System Design supporting both Local Channel fast page mode memory protocols NSBMC290 enables system designer incorporate very large memory sub-systems into high speed processing systems fact that little performance penalty incurred feature many application areas such intelligent peripheral controllers high speed communication controllers test instrumentation high performance work-stations large memory code data storage only desirable very necessary Given cost dynamic RAMs total system cost maintained levels approaching those currently popular systems that offer performance rates lower factor five more Cost performance ratios this magnitude possible lower density static memory substituted alternate implementations using power space consumptive discrete devices used Am29000 Access Protocol Support claim support Am29000 local channel protocol based assertions first that NSBMC290 implements full channel protocol described ``Am29000 Streamlined Instruction Processor Users Manual'' access methods supported
User Application Note AN-882
TRI-STATE registered trademark National Semiconductor Corporation NSBMC290 functionally equivalent V29BMC V29BMCis trademark Corporation C1995 National Semiconductor Corporation 11802 RRD-B30M75 Printed
Secondly interconnect Local Channel interface direct Local Channel naming convention been used designating pins related this interface order connect NSBMC290 Am29000 simply connects like named signal pins together example manner which these signals routed shown Appendix Memory Interface Support Support dynamic fast page mode protocols less complete than that Am29000 Local Channel protocol outputs memory array have been designed with high current drive order avoid necessity external drivers addition care been taken during design minimize problems associated with ground bounce Simultaneously Switching Outputs Buffer Strategies organization Instruction Data busses very much function system target performance cost designers lower cost systems elect retain instruction data separation willing accept lowered performance levels exchange Similarly memory speed (and cost) traded against system clock rate architecture NSBMC290 allows system designer exercise these options order achieve desired cost performance ratio LOCAL CHANNEL PROTOCOL SUPPORT three memory peripheral access methods specified Am29000 local channel protocol Simple Pipelined Burst
these access methods defined orthogonal manner both instruction data accesses This section focuses which NSBMC290 implements these access methods individually combination with each other Simple Access Simple Access method similar that characteristic conventional processor memory interface with synchronous hand shake baseline access type represents starting point other access methods simple access begins when request strobe (IREQ DREQ) asserted while address presents value within range which NSBMC290 been configured additionally required that option field (OPT2 contain value range from DREQT1 data access IREQT instruction access these conditions selection NSBMC290 occurs memory access begins
Figure diagrams sequence events After NSBMC290 been selected address transferred address lines appropriate bank that bank asserted Memory bank selection based state address line (A2) processor address interleave factor memory bank memory selected when referred Bank other Bank
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FIGURE Simple Access with Four Clock Cycle
access request immediately follows cycle which been active additional wait states will inserted guarantee de-assertion minimum clocks This ensures that pre-charge time violated After strobing memory column address NSBMC290 longer requires processor address signal asserted indicate that address available elsewhere Simple Cycle completes when NSBMC290 returns ready strobe processor (IRDY instruction access DRDY data access)
overall cycle time programmable configuration This determines number clock cycles which asserted timing Figure reflects sequence events that occur when configuration asserted cycles Figure shows same access cycle when clock cycle selected (bit timing remains same Figure except that D)RDY returned cycle earlier
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FIGURE Simple Access with Three Clock Cycle Pipelined Access NSBMC290 asserts cycle after primary access been initiated Another access begin immediately following assertion When primary access completes DRDY asserted) pipelined access becomes primary access pipeline process start again pipelined access same memory block memory bank alternate first followed vice versa) accesses overlap shown Figure
Figure shows pipelined access that begins with simple access memory Bank After asserted first time access memory Bank starts (before access Bank completes) timing diagram drawn with assumption that configuration three cycle access four cycle mode selected assertion delayed cycle pipelined access were address memory Bank pre-charge time cycles would inserted between accesses
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FIGURE Pipelined Access Alternate Memory Bank Burst Access burst access method Am29000 local channel protocol most important methods specified near theoretical performance achieved also most difficult implement NSBMC290 fully supports slave device specification this access method both instruction data accesses During execution burst access state machine NSBMC290 cycles through following phases Established processor NSBMC290 have successfully initiated burst access initial primary access been completed burst start validated Active During this phase data instruction transactions occur every clock cycle long IBREQ DBREQ remains asserted Suspended Burst access remains established instruction data transfers occur This phase processor initiated concluded either re-assertion IBREQ DBREQ signal assertion DREQ This suspended phase that initiated NSBMC290 entered only during clock write cycles order extend data hold times Burst access remains established NSBMC290 will preempt active suspended burst only long burst delays memory refresh access longer than refresh period required burst access cycles complete access requested This operation initiated processor
Paused
Preempted
Terminated
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FIGURE Establishing Burst Access Establishing Burst Mode Access NSBMC290 selected simple access D)BREQ signal asserted burst access establishment begins Figure device however limited simple access startup Burst establishment also initiated from pipeline access progress processor asserts D)BREQ complete conditions that must before time address address range configuration address block size request signal with accompanying burst request (IREQ IBREQ DREO DBREQ) field value data access (indicating word length access) request type (DREQ data access IREQT Instruction access) Immediately following memory bank containing initial address asserted Following addresses released column addresses asserted strobe this bank begins while opposite bank strobed request acknowledged NSBMC290 during D)BACK signal asserted prior this time establishment phase complete processor address available other (overlapping) transactions Both instruction data reads operate identical fashion during active phase burst access During burst reads data from memory valid until some time (memory access delay) after strobe been asserted signal delayed reflect this requirement Write operations (which only occur during data accesses) require different cycle timing DRDY During establishment phase burst data writes DRDY asserted earlier since data written memory) valid when strobe asserted using configuration bits adjust both cycle time burst write speed this type cycle modified several ways These detailed Section
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FIGURE Burst Mode Suspension Burst Suspension When processor de-asserts burst request signal (IBREQ DBREQ) during active burst access then NSBMC290 enters suspended state During this period memory control signals address maintain values held previous suspension ready signal deasserted (IRDY DRDY) suspended burst access reactivated processor re-asserts burst request (Figure Designers using processors that predate Revision ``C'' should note errata this subject implement suggested change that forces suspension become termination
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FIGURE Burst Suspended then Terminated Master
Burst Pause When cycle burst data write selected configuration NSBMC290 uses this state extend data hold period slower memories This type transaction implemented deasserting DRDY clock cycle long DRDY remains deasserted Am29000 considers transaction incomplete extends cycle period This signal sampled processor rising edge SYSCLK asserted deasserted NSBMC290 meet required setup time processor Terminating Burst Access processor terminates active burst asserting request This occur from either active suspended phases Figure shows suspended burst access that terminated when REQest asserted When termination occurs NSBMC290 immediately deasserts burst acknowledge (IBACK DBACK) MEMORY REQUIREMENTS This section provides calculations required determine DRAM speed requirements given memory configuration based NSBMC290 controller access speed required system DRAM function processor clock speed processor data setup hold times buffer delays NSBMC290 delays operating mode Memory Refresh only refresh cycle performed rate determined internal refresh counter When counter decrements terminal count value NSBMC290 will start refresh memory cycle soon idle period available refresh counter however does pause refresh memory cycle completion operates continuously independently guarantee overall device refresh rate refresh address generator always maintains full 11-bit refresh address outstanding refresh request priority over initiation access pending refresh delayed more than refresh period because long burst access NSBMC290 will preempt burst access deasserting acknowledge signal DBACK) This forces idle period because arbitration priority refresh cycle will complete refresh address automatically incremented between refresh cycles refresh period derived from system clock value programmed into configuration bits (Programmed Value row) (System Clock Frequency valid range programmed value from value used refresh cycle execution will disabled Memory Performance Requirements frequency performance system influence selection DRAM device NSBMC290 only sup-
ports page mode devices However since these most prevalent types devices market this constraint Particular attention must paid page mode behavior memory devices Most manufacturers offer both ``page mode'' ``high speed fast) page mode'' memories characteristics fast page mode devices generally those required reliable operation speeds above following sections present critical performance requirements memory devices function system operating frequency Pre-Charge Time minimum SYSCLK cycles provided between successive cycles Therefore required precharge time given 2(tSYS) tRHL tRLH Where tSYS tRHL tRLH DRAM Pre-charge Time SYSCLK Cycle Time High Delay
High Delay Because tRHL tRLH times this requirement reduces 2(tSYS) Access Time from possible control required access time DRAM memory using NSBMC290 Configuration register (Bit basic access time calculated tRAC tSYS tRHL tBUF tRAC DRAM Access Time tSYS SYSCLK Cycle Time tRHL High Delay tBUF Buffer Delay Am29000 Data Instruction Time When configuration additional SYSCLK cycle inserted into cycle tRAC increased additional tSYS period Pre-Charge Time pre-charge time during page mode access factors that determines page mode cycle time maximum permissible value given (tSYS) tCHL tCHL DRAM Pre-charge Time tSYS SYSCLK Cycle Time tCHL High Delay tCLH High Delay Because tCHL tCLH times this requirement reduces (TSYS) Where Where
Access Time from simple pipelined access time from clock cycle less then access time Thus required access time given tCAC tSYS tCHL tBUF tCAC DRAM Page Mode Access Time tSYS SYSCLK Cycle Time tCHL High Delay tBUF Buffer Delay Am29000 Data Instruction Time However burst mode operation access time decreased tCAC tSYS tCHL tBUF Where Where tCHL taken from burst mode timing parameter
Memory Interface memory block controlled NSBMC290 organized banks bits each Parity directly supported controller parity implemented parity error signal should drive D)ERR processor only during access associated memory block error detected memory interface outputs support high current drivers that will drive loads bank Given nominal input load device trace capacitance memory devices bank (byte parity included) easily supported These outputs however must externally matched input impedance DRAM memory array passive serial parallel terminating network that required Buffer Control Signals transfer Instructions Data from memory subsystem Local Channel occurs through buffers controlled NSBMC290 signals provided this purpose four operate multiple modes remaining (DBLEA have fixed interpretation These signals provide high true transparent latch enable controls during data transfers from Am29000 memory They designed operate with 74F373 style transparent latches provide additional data hold time during write operations high SYSCLK speeds with slow memories lower speeds functions performed remaining four signals change according programmed mode signal names they appear logic symbol reflect functions performed operational mode Table shows configurable control signals their assigned names various operating modes TABLE Mode Dependent Buffer Control Signals Mode (Default) DBTxA DBTxB IBTxA IBTxB
Signals prefixed
Write Cycle Restrictions During burst write cycle data hold time DRAM must considered Typically DRAM requires nonzero data hold time following assertion strobe early write cycle alternatives exist meeting hold time specification Configure NSBMC290 cycle write registers latches data into DRAM method chosen will depend desired cost performance ratio given application These methods further described Section Subsections thru SYSTEM INTERCONNECT This section describes connection NSBMC290 both host Am29000 processor DRAM memory devices describes some possible buffer strategies interconnecting Am29000 data instruction buses memory array inputs outputs Signal Description NSBMC290 signals subdivided into distinct categories processor local channel interface memory interface signals complete listing these signals device pin-outs presented NSBMC290 data sheet well Appendices this document What follows brief functional description major signal groups Local Channel Interface signals this group assigned same names their counterparts Am29000 They designed connected directly Am29000 multiple NSBMC290 system fully supported outputs reply signals DBACK DRDY PEN) have been designed that they simply wire ``OR''ed together connected directly processor interface outputs TRI-STATE open collector require only nominal pull-up approximately
Note Devices such Am29027 Arithmetic Accelerator drive these signals from non-TRI-STATE output they used circuit will necessary first wire ``OR''ed signal from NSBMC290s with signal from this device (using 74F08 example) connect output Am29000
Mode DBCeA DBCeB IBTxA IBTxB
Mode DBTx BankB IBTx IBTx
Mode DBCe BankB IBTx IBTx
active
Modes primarily designed with wide memories Since these memories have output enables separate buffers each bank required Modes designed take advantage output enables nibble wide memories Modes used with buffers which have chip enable direction control direction controls connected memory write enables chip enables connected appropriate chip enable signal IBTx(A DBCe(A write enable controls apply only data transfers since definition write operations occur from instruction When devices with select direction controls used care should taken connect ports that true write enables signals MWe(A data transfer direction from processor into memories 74F245's connect port memories)
``Am29000 Streamlined Instruction Procesor Memory Design Handbook''
modes NSBMC290 generates signal called BANKB high level this signal indicates that BANK must enabled starting next rising edge SYSCLK Conversely level indicates that BANK must enabled starting next rising edge SYSCLK order memory chip enables each bank operate with correct timing bank select signal BANKB delay from SYSCLK must kept minimum Figure shows this signal synchronized achieve proper control
Control Signal Interpretation
Mode
When configured this mode NSBMC290 asserts separate data chip enable controls each bank during both read write operations signals MWe(A asserted only during write operations determine direction data transfers This configuration mode appropriate direct control 74F245 style devices that have single enable direction control Control Signal Interpretation Mode This configuration supports nibble wide memories Am29861 style buffers wide memories with Am29C983 four port buffers NSBMC290 generates single transmit enable Instruction reads also single enable data accesses transmit enables asserted read operations either bank memory bank write enables MWe(A asserted write operations either bank used Mode BANKB signal used select which bank next accessed read operations Control Signal Interpretation Mode this mode selected single chip enable generated data access both banks asserted both read write operations either bank BANKB signal used select which bank read Both memory bank write enables asserted write operations either bank Buffer Interconnect Strategies size cost memory system design function types DRAM chosen desired system performance sections following expand some possible configurations illustrate them with appropriate diagrams Nibble Wide Memories with '245 Style Buffers nibble wide DRAM devices used conjunction with 74F245 octal buffers possible design small cost system 256k 4-bit Mbit) devices used memory size results Because NSBMC290 accommodates devices 4-Bit) size system memory size easily expanded
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FIGURE NSBMC290 Memory System Using DRAM Devices 74F245 Buffers Control Signal Interpretation Mode This mode designed used with wide memories buffers which have separate output enables each direction Am29861) transmit enable controls each bank DBtx(A asserted read operations from memory while memory bank write enables MWeA asserted write operations buffer signals that enable processor memory transfers must connected memory bank write enables while those that permit memory processor transfers connected appropriate transmit enables DBTx(A
Figure shows connection control signals data instruction buffers Buffer mode required NSBMC290 startup order guarantee sufficient data hold time during data burst writes memory SYSCLK cycles required NSBMC290 should initialized with configuration buffer mode output enables DRAM driven signals derived from BANKB signal write enable strobes from NSBMC290 used disable output enable during write cycles
Wide Memories with '245 Style Buffers Output enables typically available with wide DRAMs thus necessary individually buffer each memory bank illustrated Figure NSBMC290 must configured buffer mode with
cycle burst write This configuration most simple inexpensive when using single DRAM devices disadvantage this Strategy that large number buffers required Printed circuit routing probIerns require additional signal layers larger area
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FIGURE NSBMC290 Memory System Using DRAM Devices 74F245 Buffers Enhanced Performance Using Nibble Wide Devices single cycle data burst writes desired necessary latch data from processor This accomplished substituting 74F646 registered buffers data path replace 74F245s used Figure Figure 74F646 buffers connected that transparent (unregistered) path from memory array processor clocked (registered) path from processor memory array this ``245'' style response occurs during read cycles ``374'' style response occurs during write cycles NSBMC290 should configured buffer mode configuration register bits clock registered path complement SYSCLK Am29000 asserts data following rising edge SYSCLK This data then latched falling edge SYSCLK Simultaneously asserted bank addressed that cycle Figure illustrates write cycle timing achieved using 74F646 buffers data hold time calculated tSYS tCHL Where Data Hold Time DRAM tSYS SYSCLK Cycle Time tCHL High Delay
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FIGURE Burst Write Cycle Timing Using 74F646 Register Data from Processor
This method achieving single cycle burst write will work higher clock speeds Am29000 SYSCLK data valid delay begins approaching half SYSCLK period this event setup time 74F646 violated order avoid problems memory data should demultiplexed transparent latches (such 74F543) should used replace registered latches DBLE(A signals used control buffer latch enables This method will guarantee correct operation DBLE(A signals asserted until after falling edge SYSCLK Setup time violations thus avoided transparent latches requires that data buses memory banks separated Consequently this buffer method best suited with wide memories although nibble devices will work well
Single Cycle Burst Write with Wide Devices Since wide DRAMs lack fast output enable control found nibble wide DRAMs data outputs banks must separated buffer control signals from NSBMC290 require that write operations memory overlapped during burst access that while write cycle being completed bank memory data other bank being latched written transparent latch used hold data from previous cycle while that from current cycle being saved other bank 74F543 buffer contains sets latches that allow bi-directional latched transparent data flow During read operations transparent mode used during write operations data latched Figure illustrates required interconnect ``mode circuit Because latch controls inverted necessary invert control signals from NSBMC290
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FIGURE NSBMC290 Memory System with Inproved Burst Write Performance Using Nibble Wide DRAM Devices 74F646 Buffers
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FIGURE NSBMC290 Memory System Using DRAM Devices 74F543 Buffers Single Cycle Burst Read Write Operation
Using Wide Devices with Am29C983 Am29C983 port exchange buffer several distinct advantages memory system design principle advantage that only four packages required This will significantly reduce congestion lower board space requirement Another advantage Am29C983 9-bit data path size additional used transmit byte parity systems where parity desired Finally they also provide transparent latch capabilities that enable single cycle operation without violation memory setup hold times view these devices offer most efficient method obtaining high memory density device count full operational speed Figure Am29C983s configured operate non-latching buffers read operations transparent latches during data writes latch enable signals indicate when port output data latched while write enable signals determine when these outputs enabled BANKB signal synchronized SYSCLK selects between ports Expanding Memory Size When using nibble wide memories desirable second block memory NSBMC290 Using
gabit (256k devices base memory size required then second NSBMC290 should used that split Instruction data architecture implemented With NSBMC290s place further memory expansion accomplished Figure using buffer configuration ``mode Figure output enables four banks DRAM controlled with device (Listing Address line latched used select memory blocks result NSBMC290 should initialized larger block size With 256k memories block size should selected instead result block memory will redundantly mapped twice address space Note that write enables tied together each block compared NSBMC290 which separate write enables However NSBMC290 write enables logically identical outputs generated only purpose distributing load capacitance possible drive more than block wide devices NSBMC290 since load capacitance would prohibitive (only devices bank allowed)
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FIGURE Memory System using wide DRAMs Am29C983 buffers Configuration mode single cycle write
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FIGURE Memory System with Single Cycle Burst Write Performance Using Blocks Nibble Wide DRAM Devices SOFTWARE DESIGN ease with which NSBMC290 integrated into system design been illustrated foregoing sections memory sub-systems described support Am29000 with between memory (depending storage devices selected) managed single NSBMC290 examples shown 256k nibble wide devices General Considerations Since NSBMC290 manages both instruction data accesses memory block minimally required However interleaving instruction data accesses single memory block result increased number instruction burst restarts compared designs that separate instruction data memory blocks performance degradation that results severe maximum performance absolutely required more NSBMC290s effective solution minimaI systems type shown performance degradation access type interleave virtually eliminated careful software design Software design relates behavior systems using RISC type processors with near cycle instruction performance rates governed slightly different parameters from those operative CISC designs where everything equally slow There major architectural constructs that should taken advantage designing software Am29000 first large internal register file local global management structure second branch target cache These features relate respectively program data organization subroutine usage
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FIGURE Logic Equations Device Used when NSBMC290 Controls Blocks DRAM Devices Resulting Memory System
performance optimized single external data accesses should eliminated where possible replaced large scale register loads stores (``spills fills'') order this call tree analysis subroutine flow tracing should performed with view maximizing data locality reference While optimizing compiler long maximizing local variable placement array access loop constructs responsibility global external data placement province programmer supporting burst pipelined access data memory NSBMC290 promotes locality reference augmented register ``spill fill'' means enhancing program performance fact that branch target cache stores first four instructions address jump target that NSBMC290 requires five cycles restart burst access allows programmer issue repetitive subroutine call returns implement loops with single cycle penalty repetitive subroutine invocation real performance related issue data organization instruction burst restart passing arguments through registers taking advantage global local register support register file manager throughput maintained near theoretical rates Dynamic separation Instruction Data spaces Systems that employ multiple NSBMC290s enjoy benefit being able perform instruction data partitioning dynamically through translation look-aside buffer long
page allocation algorithm avoids assigning active code segment same memory block simultaneously active data segment performance affected This rule conjunction with standard best least recently used algorithms makes task page table management simple fast Software Configuration NSBMC290 Configuration NSBMC290 occurs first 32-bit instruction data read from address space other than system after RESET example presented assumes that RESET connected SYSTEM RESET This configuration mandatory external logic used separately control RESET NSBMC290 configuration bits zero following reset values placed fields comprising bits thru completely determined hardware implementation address assignment software option important remember that start address block boundary that integer multiple block size example NSBMC290s used which supports memory block other block block will reside boundary block boundary linear addressing required block assigned start block 800000(Hex) Alternately translation look aside buffer programmed linearize organization these address spaces
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APPENDIX
SAMPLE CONFIGURATUION PROGRAM
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APPENDIX NSBMC290 Am29000 INTERCONNECT (PGA) Relationshp between signal pins NSBMC290 Am29000 Diagram shows possible Printed Circuit Board routing strategy
Fine line design rules (two signals between pins) assumed multiple NSBMC290s require only that connection extended intermediate logic required
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APPENDIX
LIST SORTED SIGNAL NAME (PGA)
signals marked Reserved should connected through individual resistors maintain compatibility with future releases NSBMC290 Number Signal Name Number Signal Name AA10 AB10 BINV CASA0 CASA1 CASA2 CASA3 CASB0 CASB1 CASB2 CASB3 DBACK DBLEA DBLEB DBREQ DBTXA DBTXB DRDY DREQ DREQT0 DREQTI IBACK IBREQ IBTXA IBTXB IRDY IREQ IREQT Number Signal Name MWEA MWEB OPT0 OPT1 OPT2 RASA RASB Reserved Reserved Reserved Reserved RESET RSTOUT SYSCLK
APPENDIX
PINS LIST SORTED NUMBER (PGA)
signals marked Reserved should connected through individual resistors maintain compatibility with future releases NSBMC290 Number Signal Name CASB2 CASB0 RASB Reserved CASB3 CASB1 MWEB MWEA AB10 Reserved Number Signal Name Reserved CASA3 CASA2 CASA1 CASA0 RESET RASA AA10 SYSCLK OPT0 Number Signal Name DREQT0 DBREQ Reserved DBACK RSTOUT OPT1 DREQT1 DREQ IREO IRDY DRDY DBLEA IBTXA IBTXB IREQT OPT2 BINV IBREO IBACK DBTXA DBTXB DBLEB
APPENDIX
QUAD FLATPAK PIN-OUT
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User Application Note
APPENDIX
RECOMMENDED SYSTEM CLOCK GENERATOR
high loading factor sysclk input Am29000 following clock generator circuit should used minimize skew distortion
NSBMC290 Burst Mode Memory Controller
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LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION used herein Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user critical component component life support device system whose failure perform reasonably expected cause failure life support device system affect safety effectiveness
AN-882
National Semiconductor Corporation 2900 Semiconductor Drive 58090 Santa Clara 95052-8090 1(800) 272-9959 (910) 339-9240
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National does assume responsibility circuitry described circuit patent licenses implied National reserves right time without notice change said circuitry specifications

NSBMC290 Burst Mode Memory Controller User Application Note TABLE

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