DP83956EB-AT LERIC (LitE Repeater Interface Controller) PC-AT Adapter
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DP83956EB-AT LERIC (LitE Repeater Interface Controller) PC-AT Adapter
DP83956EB-AT LERIC (LitE Repeater Interface Controller) PC-AT Adapter
INTRODUCTION This LERIC-NIC Evaluation Board provides PC-AT compatible computers with Twisted Pair conductivity board uses DP8390 (NIC) perform Ethernet protocol operations operations dual (local remote) capabilities along with kBytes buffer allow entire Network Interface Adapter appear standard Port system module's local channel buffers packets between local memory kBytes buffer RAM) network while module's remote channel passes data between local memory system memory Port This Port architecture which isolates from network traffic proves simplest method interface DP8390 system DP83956 (LERIC) used interface twisted pair Ethernet provides IEEE (Chapter compliant repeater functions twisted pair ports LERIC on-chip Manchester data decoding Manchester encoder Elasticity buffer preamble regeneration also integrated 10BASE-T transceivers LERIC's internal registers accessed using same port architecture This board provides required attributes compliance with Novell's Management Interface (HMI) basic control capability BOARD OVERVIEW LERIC-NIC board allows direct connection network using RJ-45 phone jacks There ports card addition boards cascaded together PC-AT thus providing Twisted Pair ports block diagram shown Figure illustrates architecture LERIC-NIC Evaluation Board LERIC-NIC Board seen PC-AT system appears only port With this architecture LERIC-NIC board local access board memory system never intrude further than ports packet data operation Hardware Features
National Semiconductor Application Note Marc Clevenger Imad Ayoub Balasvbramanian November 1992
BOARD ARCHITECTURE Board LERIC-NIC Board requires 32-byte space allow decoding data buffers reset port LERIC registers first bytes (300h 30Fh) used address LERIC bits wide) registers bits wide) next bytes (310h 317h) used address data buffers which bits wide Finally reset port (also software selectable) addressed 318h 31Fh TABLE PC-AT Address 300h 310h 318h Part Addressed LERIC Select Data Buffers Reset
Although description above positioned addresses also placed following address spaces These alternate address spaces selected jumpers (JP1 JP0) shown Table TABLE Optional Address Spaces Address Space 300h 31Fh 320h 33Fh 340h 35Fh 360h 37Fh
Utilizes DP83956 LitE Repeater Interface Controller
(LERIC)
10BASE-T connections card node connection utilizing Cascadability boards kByte on-board Packet Buffer Simple Port Interface PC-AT Interfaces Twisted Pair (10BASE-T) Boot EPROM Socket detailed schematics this design shown this document
TRI-STATE registered trademark National Semiconductor Corporation LERICand Inter-LERICare trademarks National Semiconductor Corporation PC-AT registered trademarks International Business Machines Corp Ethernet registered trademark Xerox Corporation registered trademark used under license from Advanced Micro Devices Novell registered trademark Novell C1995 National Semiconductor Corporation
Data Address Paths following paragraph better understood looking block diagram shown Figure Twenty address lines from onto LERIC-NIC Board only four them actually LERIC These four addresses along with (low-asserted read) (low-asserted write) (NIC chip select signal) allow read write LERIC NIC's registers system wants read from write LERIC registers data bits bits LERIC) must pass through appropriate buffer packet data will pass through ports (the 374's) Each unidirectional only drive bits therefore necessary have four 374's which drive data from ports board memory which drive data from ports Even PROM which only addressed sends bits data through 374's When PROM does this 374's will enabled only lower bits will have valid data also accessed However addressed bits drives bits data
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RRD-B30M115 Printed
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FIGURE LERIC-NIC PC-AT System Interface PALs receive address lines among many other signals such With these signals PALs decodes such selecting LERIC-NIC Board LERIC chip chip PROM EPROM socket provided that user EPROM system This EPROM would normally contain program driver enable PC-AT booted through network chips necessary interface EPROM system 27128 (EPROM) 16L8 (PAL) 74ALS244 (buffer) Also must placed proper selection described jumper section decodes SA14-SA19 along with SMRDC (system memory read) order generate EPROMEN signal This signal issued when wants execute EPROM buffer Global Register Description additional 3-bit write only register provided board allow accesses LERIC This register also accessed using port architecture address location space been allocated This register mapped four address location This done using jumpers shown Table only write this register TABLE Optional Address Spaces Global Register Address Space 200h 220h 240h 260h
three bits this register shown Table Bits used specify board number Since there four boards cascaded together unique board address necessary distinguish between them used select LERIC when accesses being made power-up this defaults selects order access LERIC this zero TABLE Global Register Bits LERIC Board Board
LERIC-NIC INTERFACE LERIC-NIC interface makes Inter-LERICBus which consists following signals ACKO ACKI ACTN ANYXN COLN Besides data (IRD) clock (IRC) this provides other signals necessary cascading LERIC another treated another LERIC when connected InterLERIC Inter-LERIC also eliminates need encoder decoder chip which usually connected Since Inter-LERIC bidirectional some logical operations necessary convert signals compatible with some TRISTATE buffers used implement this function Figure shows interface between LERIC this implementation placed arbitration chain input pins connected directly LERIC pins respectively input derived combining COLN ANYXN signals from LERIC input comes from inverted signal LERIC When wants transmit drives ACKI input LERIC with inverted signal inverted signal also used enable TRI-STATE buffer which connects output signals signals Inter-LERIC used drive ACTN signals during transmission
together ACKI ACKO signals daisy chained between boards ACKO signal will drive ACKI input board which next arbitration chain Jumper (see schematic) used ACKI inverted signal from which puts arbitration chain boards used slave mode also ACKI high putting that board chain Otherwise with removed ACKI signal will driven ACKO output board higher arbitration chain Since these signals held TRISTATE open collector they pulled resistors resistor value selected these pull-ups When four boards cascaded smallest pull-up value Inter-LERIC signal will approximately This elevates need remove some these pull-up resistors when additional boards cascaded BOARD OPERATION following pages describe slave accesses LERIC-NIC local remote operation Global Register Operations Accesses board register operations LERIC which done control operation NIC's channels read write LERIC registers Since LERIC share same space registers (300h 30Fh) additional operation required Before register read write performs write global register order select LERIC bits selecting four possible boards usage this depends software used normal network access) driver used card looks like pure adapter software board normally would with selected When driver needs access LERIC would first write Global Register LERIC operations then back enable access This minimizes changes portion driver begin global register write (see Section Global Register description) drives address lines LERIC-NIC board address lines With these address lines decodes depending settings jumpers then drives strobe which used latch data into Global Register rising edge This ends cycle global register write LERIC Register Accesses Before LERIC register access must write global register order select LERIC appropriate LERIC-NIC board After register access must perform another write global register select LERIC Register Read begin register read drives four address lines (SA0 SA3) LERIC address lines With these address lines line decodes (the LERIC registers) signal enabled Once LERIC receives this then sends assertion BUFEN BUFEN signal used assert IOCHRDY signal false LERIC then drives data from internal registers buffer buffer then enabled LERICEN signal data driven onto 3-bit counter used indicate when LERIC
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COLN ANYXN
FIGURE LERIC-NIC Interface Inter-LERIC Interface LERIC-NIC board master board also used without board with LERIC only NIC) slave board desirable when more boards used same master three slave boards cascaded using Inter-LERIC interface form larger logical repeater that meets IEEE's specification single repeater) There 14-pin headers board cascading Inter-LERIC signals Both headers contain signals ACTN ANYXN COLN input header also contains ACKI signal output header contains ACKO These signals enable multiple LERICs cascad-
driven data This gives LERIC enough time output data This required since LERIC does have other signal which indicates that data available This indicated signal COUNT going high (after about which causes assert IOCHRDY true result driven high thereby de-asserting rising edge data which latched into system addresses removed same time causing LERIC chip select become de-asserted ending register read cycle LERIC Register Write begin register write drives four address lines (SA0 SA3) LERIC SA4-SA9 address lines With these address lines line decodes 300-30F (the LERIC registers) signal enabled Once LERIC receives this then sends assertion BUFEN BUFEN signal used assert IOCHRDY (used insert wait states) signal false then drives data onto where goes into buffer buffer then enabled LERICEN signal data driven LERIC 3-bit counter used indicate when LERIC latched data This indicated signal COUNT going high which causes assert IOCHRDY true result driven high thereby de-asserting addresses removed same time causing LERIC chip select become de-asserted ending register write cycle Register Accesses following discussion assumes jumper setting address space 300h-31Fh Register Read begin register read drives four address lines (SA0 SA3) SA4-SA9 address lines With these address lines decodes (the registers) thereby enabling chip select also drives line which sees (slave read) Since local master when attempts read write controller line used assert IOCHRDY signal false wait state drives data from internal registers buffer When ready slave move complete read cycle asserts true which enables buffer data driven onto Driving true also causes assert IOCHRDY true result driven high thereby de-asserting rising edge data which latched into system addresses removed same time causing chip select become de-asserted ending register read cycle Register Write begin register write drives SA0-SA3 address lines SA4-SA9 address lines With these address lines decodes (the registers) thereby enabling chip select then drives strobe which sees (slave write) Once receives this sends back assertion acknowledge that slave mode ready perform write assertion will generate IOCHRDY true enable buffer buffer then drives data from system drives high thereby de-asserting latching data
addresses also taken away chip select then goes high (de-asserted) This ends cycle register write Local Memory There only items mapped into local memory space These items shown Table buffer address PROM buffer used temporary storage transmit receive packets transmit packets remote puts data from ports into local moves data from receive packets local carries data from remote moves data from ports TABLE Local Memory 7FFFh 4000h 3FFFh PROM 0000h address PROM (74S288 contains physical address evaluation board Each PROM holds unique physical address which installed during manufacture Besides this address PROM also contains checksum This checksum calculated exclusive ORing address bytes with each other provided order check addresses initialization evaluation board software commands transfer PROM data Port where read then verifies checksum loads NIC's physical address registers Table shows contents PROM TABLE PROM Contents PROM Location Location Contents Ethernet Address (most significant byte) Ethernet Address Ethernet Address Ethernet Address Ethernet Address Ethernet Address Ethernet Address through Reserved
Remote Packet Data Transfers Remote transfers operations performed board These operations occur when programmed transfer packet data between PC-AT card's on-board These transfers take place through Port interfacing
Remote Read program remote read must take five slave accesses must write Remote Start Address bytes) Remote Byte Count bytes) Then issues Remote Read command Once received above data drives BREQ waits BACK immediately receives BACK because tied BREQ line BREQ tied BACK because there other devices contending local After receiving BACK drives address from which data required read This address flows into 373's latched ADS0 From here address flows waits until receives from then drives data into ports ports then latch data rising edge strobe from then sent system know that there data waiting ports reads ports before loaded 374's then port request (PRQ) from will driven This unasserted signal causes AT's ready line indicating that load data After data ports system must then read data ports This begins with driving address which decoded (inside data Ports (310-317) then drives RACK indicating that ready accept data This RACK signal then reads data from ports onto system deasserts which finishes cycle Remote Write Like remote read remote write cycle also begins with five slave accesses internal registers must write Remote Start Address bytes) Remote Bytes Count bytes) issue Remote write command then issues responds sending indicating that ready write ports also drives address which corresponds Ports generates WACK address decode data buffers along with This WACK signal latches data into ports issues BREQ immediately receives BACK since lines tied together upon receiving BACK drives address lines 373's These address lines latched ADS0 then driven then sends which drives data from ports into already specified address onboard then deasserted cycle ends Network Transfers from Buffer Transfers from network controlled NIC's local channel which transfers packet data from NIC's internal FIFO from card's buffer Data Reception data received from network deserialized loaded into FIFO inside then issues BREQ immediately receives BACK since lines tied together After receiving BACK drives address lines 373's 373's latched ADS0 address allowed flow Then drives along with data from FIFO data flows into address given earlier strobe then de-asserted ending cycle
Data Transmision begin transmit cycle issues BREQ waits BACK Since BREQ BACK lines tied together BACK received immediately Upon reception this signal drives address 373's which latch address with ADS0 strobe address then flows on-board memory driven causes drive data given address into then latches data into FIFO rising edge high assertion signifies ending this cycle From FIFO data serialized transmitted network TWISTED PAIR INTERFACE interface network through LERIC twisted pair ports shown Figure drive transmitted signal through meters Unshielded Twisted Pair (UTP) cable LERIC requires external drivers optimized resistor network shown provides proper pre-emphasis transmit signals 100X termination receive pair Standard Filter Transformer Choke modules (such Valor FL1012) used provide required filtering isolation BOARD CONFIGURATION LERIC initialized during power-on reset rising edge reset signal from PC-AT data pins loaded into configuration registers This reset tied directly MLOAD LERIC (Refer LERIC datasheet description MLOAD LERIC-NIC board there pull-up resistors pins which will load into configuration registers during power pattern configures LERIC twisted pair ports full mode enables polarity switching twisted pair ports selects consecutive collision counts port before partition sets update operation maximum mode LERIC possesses control logic interface pins which used provide status information concerning activity attached network segments current status repeater functions LERIC-NIC board LED's provided (one each port updating ``any'' port status) `259 addressable latch used latch data address information contained pins LERIC (refer LERIC datasheet description each pin) toggle switch also provided allow display either status link integrity reception activity port basis status collisions jabber ``any'' port This switch selects which LERIC data data input `259 latch on-board crystal oscillator provides clock inputs LERIC oscillator's output which directly LERIC Since also requires clock flip-flop (74ALS74) used divide down This input clock also used input 74LS93 counter Since there ``Ready'' signal from LERIC indicating completion data latching register read write operation this counter used generate wait state before OCHRDY signal asserted back
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FIGURE Twisted Pair Interface Jumper Options default jumper block configurations shown Figure there possible connections Four these select interrupt line available interrupt lines include INT3 INT4 INT5 INT9 last possible connections used select base address board However connected then these last connections also select address EPROM possible selections jumpers which should (closed) shown Table factory configuration uses INT3 line interrupts position used optional address space global register default position these jumpers (see Table III) TABLE Base EPROM Addresses Base 300h 31Fh 320h 33Fh 340h 35Fh 360h 37Fh EPROM C800h CC00h D000h D400h
used board address when multiple boards cascaded together These jumpers normally default position used take care IOCHRDY timing issues some clone default this jumper (refer description more details IOCHRDY timing inconsistency) used arbitration when cascading several boards default position assumes that arbitration chain ACKI generated from When cascading several boards boards lower chain would have removed
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FIGURE Jumper Blocks
EQUATIONS (U1) this output signals NIO16 NIOEN NNICB SELREG NIO16 only asserted trying access local buffers board 16-bit slot NIO16 used determine should perform 16-bit operations NIO16 false then will only perform 8-bit operations Since necessary assert NIO16 soon possible this been selected ``D'' NIO16 signal must TRI-STATE when asserted Therefore enable signal (NIOEN) which equal decode Ports
(310 31F) NAEN high (NAEN high signifies that system does have control bus) enable signal (NIOEN) loops back into bring NIO16 TRI-STATE NIO16 signal zero that whenever enabled will asserted NNICB signal consists simple address decodes along with NAEN will asserted when wants access LERIC-NIC board addresses decode four address slots which were earlier mentioned board configuration section SELREG signal similar NNICB decodes four addresses which were mentioned board architecture section SELREG asserted when wants access Global Register
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(U2)
this there seven outputs which include NRESET NIOCHR NIOCHW NIOCHC NRACK NWACK IOCHRDY signal used wait state Normally card drives IOCHRDY (not ready) only after address read write signals have been asserted some PC-AT compatible (those using Chips Technologies VLSI chipsets) during 16-bit operation controller actually samples IOCHRDY signal before read write signal asserted NIOCHC used drive IOCHRDY (not ready) based only address decode thus allowing IOCHRDY asserted earlier proper state when sampled controller shown Figure NIOCHR NIOCHW NIOCHC externally wire-ORed together generate IOCHRDY signal NIOCHR along with NIOCHR (enable NIOCHR) slave read remote read cycles NIOCHW NIOCHW (enable NIOCHW) slave write remote write cycles These signals together generate ``normal'' IOCHRDY signal more details IOCHRDY refer application note PC-AT Interface Design Considerations DP83902EB-AT NIOCHC cause problems PC's that
Chips Technologies VLSI chipsets D-flip flop used generate CLONEN implement timing modification variable CLONEN tied jumper that used switch IOCHRDY signal characteristics ``normal'' modified timing system operates under ``normal'' timing characteristics should removed asserted when needs access registers decoded address range along with NICSEL from NICSEL high access registers access LERIC registers next signals NRACK NWACK used acknowledge successful transfers between data buffers NRACK occurs with address decode NIOR NWACK occurs with address decode NIOW last signal NRESET which used reset both LERIC configuration registers NRESET asserted system with RSTDRV through software after system booted Once NRESET been asserted held until received from This will guarantee that NRESET pulse width required
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FIGURE
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(U16)
third does decode enable optional EPROM This decode consists address decode C8000h CC000h D0000h D4000h depending shown board configuration section must also jumpered selection EPROM NAEN asserted signal should indicate that does have control NSMRDC signal should asserted since doing system memory read
A013 signal used 8-bit mode operation When board placed into 8-bit slot EN16 signal used detect existence second PC-AT connector EN16 then board 16-bit slot this condition (from NIC) enabled A013 which goes board placed into 8-bit slot then EN16 pulled high resistor this causes LERIC-NIC's signal enabled This allows used 8-bit
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(U30)
this there seven outputs which include TXENABLE NLRD NLWR NLERICEN GRDATA first three outputs generate interface signals between LERIC just inverted NIRE signal which notifies that there activity network asserted there receive transmit collision coming from LERIC TXENABLE tied ACKI putting LERIC's arbitration chain TXENABLE also used enable buffer that controls flow coming from
NLRD NLWR generate read write strobes LERIC based address decode LERICHIT LERICHIT Global Register decode from NLERICEN signal used enable TRI-STATE buffers receivers that access LERIC registers will only asserted after NLRD NLWR true LERIC driven BUFEN signifying that inter-LERIC available register read write last output GRDATA used latch Global Register bits into data bits from AT-BUS will valid after asserted along with SELREG which address decode Global Register coming from
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(U29)
This includes outputs NCSROM INTO LERICHIT NICSEL registered outputs only used internally LERICHIT signal comes from decode Global Register indicates that needs access LERIC
GRDATA used clock registered outputs consisting NICSEL These three bits store contents Global Register just sent through buffered buffered signal which comes INTO NCSROM very simple signal consists only AD14 NMRD AD14 comes from selects either PROM (when low) on-board (when high)
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LERIC PC-AT Evaluation Board
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LERIC PC-AT Evaluation Board (Continued)
Pins Assigned Pins
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LERIC PC-AT Evaluation Board (Continued)
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LERIC PC-AT Evaluation Board (Continued)
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Note resistors unless otherwise indicated
LERIC PC-AT Evaluation Board (Continued)
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LERIC PC-AT Evaluation Board (Continued)
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Note Resistor Nomenclature follows 301X 806X
BILL MATERIALS Capacitors Miscellaneous 5mmGreenLED SS-668806-NF jumper jumper jumpers6x2 TOGGLESWITCH FL1012 102160-2 746194-2 Resistors SIP8x300 SlP8x10k IC's PAL16L8 GAL16V8 GAL16V8 PAL20L8D 74ALS245 74ALS374 6264RAM 74ALS373 74S288 74LS93 27128 74ALS244 74LS04 74ALS243 74ALS1035 DP8390 74ALS74 74ACT244 74LS259 DP83956
(6PORT POSITION RJ45 FROM STEWART)
(jumper block) (VALOR) HEADER RECEPTACLES
DPST
01%) PLCC Type (SOCKETED) PLCC Type (SOCKETED) PLCC Type (SOCKETED) PLCC Type (SOCKETED)
STATIC SOCKETED EPROM (SOCKET ONLY) Crystal Oscillator
(SOCKETED PLCC)
LERIC
Note Everything surface mount except devices that were marked with devices with through hole
DP83956EB-AT LERIC (LitE Repeater Interface Controller) PC-AT Adapter
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