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Measuring a Loudspeaker Impedance Profile Using the AD5933

by Sean Brennan

AN-843 APPLICATION NOTE
One Technology Way · P.O. Box 9106 · Norwood, MA 02062-9106, U.S.A. · Tel: 781.329.4700 · Fax: 781.461.3113 · www.analog.com
Measuring a Loudspeaker Impedance Profile Using the AD5933
by Sean Brennan
INTRODUCTION
This application note describes the circuit architecture and details required to measure the impedance profile of a commercial loudspeaker using the AD5933 impedance-to-digital converter. By evaluating the acoustic properties of loudspeakers through an impedance measurement from 1960 to 1970, two Australian pioneers, N. Thiele and R. Small, defined the Thiele-Small parameters. Thiele and Small analyzed the electro-mechanical behavior of a speaker voice coil, magnet, and cone interacting with the cone suspension and the air in and outside sealed enclosures. These findings have been used by manufacturers and hobbyists to the present day as a standard to design high fidelity speaker cabinets, crossover networks 1 , and to test the final driver networks themselves. Measuring the impedance of a commercial loudspeaker typically involves using various tools ranging from
simple lab equipment (for example, signal generators, oscilloscopes, and digital voltmeters) to PC sound cards and expensive audio network analyzers. A fundamental problem exists: the impedance test equipment remains separate from the audio system driving the loudspeaker. The aim of this document is to describe a circuit architecture using the AD5933 that allows the system designer to measure the impedance profile of the loudspeaker and integrate this circuitry into the audio signal chain. This has many benefits for example upon system power up, the circuitry provides the ability to measure the impedance profile and thus the acoustic properties of the loudspeaker, enabling direct comparison to a factory calibrated profile stored nearby. Any changes in the impedance profile are detected and so further diagnostics are carried out, preventing premature damage.
For more information, see Chapter 8 (Page 101), "Speaker Crossovers, " by Hank Zumbahlen, in the Systems Application Guide. Published by Analog Devices, Inc., 1993, ISBN 0-916550-13-3.
OSCILLATOR
DDS CORE (27 BITS)
DAC ROUT VOUT
SCL SDA
I2 C INTERFACE
TEMPERATURE SENSOR Z()
AD5933
REAL REGISTER IMAGINARY REGISTER RFB 1024-POINT DFT
VIN ADC (12 BITS) GAIN LPF VDD / 2
Figure 1. AD5933
AN-843 TABLE OF CONTENTS
Introduction ........................................... 1 Revision History ........................................ 2 Operation and Calibration ............................... 3 Loudspeaker Impedance Model and Profile ................. 3 Circuit Details .......................................... 4 Howland Current Source................................. 5 Modified Howland Current Source ........................ 5 AD5933 DFT Details.................................... 6 Clock Divider Circuitry................................7 Loudspeaker Impedance Measurement ......................8 System Calibration ....................................8 Loudspeaker Impedance and Phase Calculation ...........8 System Clock Settings..................................9 Results ............................................... 11 Conclusion ......................................... 11
REVISION HISTORY
6 / 06-Revision 0: Initial Version
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OPERATION AND CALIBRATION
As shown in Figure 1, the AD5933 is a high precision, impedance converter system that combines an on-board frequency generator with a 12-bit, 1 MSPS, analog-to-digital converter (ADC). The frequency generator allows an external complex impedance to be excited with a known frequency. The response signal from the impedance is sampled by the on-board ADC, and a discrete Fourier transform (DFT) is processed by an on-board DSP engine. The DFT algorithm returns a real (R) and imaginary (I) data-word at each output frequency. The magnitude of the impedance and relative phase of the impedance at each frequency point along the sweep are easily calculated using the following two equations: ·
LOUDSPEAKER IMPEDANCE MODEL AND PROFILE
To understand the subsequent measurement, a simplified electrical model of a loudspeaker is shown in Figure 2.
Rdc LIN L rms C
Therefore, in order to obtain the Thiele-Small parameters, the resulting impedance peak and crossover frequencies need to be accurately determined.
LINEAR REGION 55 50 45 40 RESONANCE VOICECOIL INDUCTANCE
IMPEDANCE
Figure 2. Loudspeaker Impedance Model
35 30 25 20 15 10 5 100 FREQUENCY (Hz) 1k
The circuit in Figure 2 has a dc resistance placed in series with a lossy parallel resonant circuit made up of L, rms, and C, which model the dynamic impedance of the speaker. In summary:
Figure 3. Typical Loudspeaker Impedance Profile
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CLOCK DIVIDING CIRCUIT MCLK AVDD DVDD
CIRCUIT DETAILS
Figure 4 shows the circuit block diagram used to measure the impedance profile of a commercial loudspeaker. The circuit consists of three major blocks. One major block is a modified Howland current source and gain stage connected to the output of the AD5933 with a commercial loudspeaker connected in the feedback loop of the external gain stage. Another block is a clock-dividing circuit, which scales down the master clock / crystal frequency supplied to the AD5933, enabling the impedance profile to be analyzed across the bandwidth of interest (10 Hz to 20 kHz).Clock scaling is required by the AD5933 in order to analyze frequencies below 10 kHz. The third block is the AD5933 impedance-to-digital converter. The following sections explain the circuit details of the Howland current source and clock-dividing circuitry. For more information, the AD5933 data sheet can be downloaded from www.analog.com.
LOUD SPEAKER 10k 150pF 3.3V 10µF, 0.1µF DAC ROUT VOUT 20k U1A 100 10k 20k 10µF, 0.1µF 3.3V RFB 1024-POINT DFT 30 0.1µF U1B RCALIBRATION
OSCILLATOR
DDS CORE (27 BITS)
SCL SDA
I2C INTERFACE
TEMPERATURE SENSOR
AD5933
REAL REGISTER IMAGINARY REGISTER
10µF, 0.1µF 10k 10k 10µF
VIN ADC (12 BITS) GAIN LPF VDD / 2
Figure 4. Loudspeaker Impedance Measurement Circuit
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HOWLAND CURRENT SOURCE
Figure 5 shows a modified Howland constant current source. The output current through the load is independent of the impedance of the load and only depends on the input voltage VIN.
R2 C1 VCC
MODIFIED HOWLAND CURRENT SOURCE
LOUD SPEAKER 10k 150pF 3.3V 10µF, 0.1µF 20k U1A 100 RCALIBRATION
20k 10µF, 0.1µF 3.3V
10k 3.3V 10µF, 0.1µF 10k 10k
1.65V
Figure 5. Typical Howland Current Source
0.1µF
Using the equations for the gain of an op amp at the negative and the positive input terminals, the voltage VA can be written as
Simplifying Equation 3 yields
Rearranging the equation it can be shown that
If R2 is much greater than Rx, the current IB can be assumed to flow through the load in accordance with the current divider rule. In practice, Rx is 1 to 100 and R2 is in the order of 10 k to 100 k. The capacitor C1 provides a single dominate pole in the feedback circuit to prevent oscillations. Without a load, the positive feedback equals the negative feedback when power is first applied to the circuit (Vdd). Capacitor C2 ensures that the positive feedback is always less than the negative feedback when power is applied first to the circuit.
AN-843
where: X(f) is the power in the signal at the Frequency Point f. x(n) is the ADC output. cos(n) and sin(n) are the sampled test vectors provided by the DDS core at the f frequency. The multiplication is accumulated over 1024 samples for each frequency point. The result is stored in two, 16-bit registers representing the real and imaginary components of the result. The data is stored in twos complement format.
Leakage Considerations
If the input signal to the receive side does not have an exact integral number of cycles over the N-point sample interval, there is not a smooth transition from the end of one period to the start of the next. Because the on-board ADC is sampling the receive signal for a finite time, the AD5933 is in effect multiplying the input sequence by a rectangular window. The continuous Fourier transform of a rectangular function is the classic sinc function (sin (x) / x). If the input signal to the receive side of the AD5933 contains spectral components at exactly integer multiples of the fundamental analysis frequency, then these side lobes are zero at bin frequencies and do not show up in the DFT output. If however, the input signal contains components that do not fall exactly on these bin frequencies, then the sinc functions side lobes contain energy at the bin frequencies. It is the high frequency components inherent in the discontinuities of nonperiodic sampling that causes these side lobes to exist. Therefore, an obvious problem exists. The DFT performed by the AD5933 only produces a correct result when the ADC output sequence x (n) contains energy precisely at the analysis frequencies that are integral multiples of the fundamental frequency. If the input signal has a component at some intermediate frequency between these frequency bins, this input signal shows up to some degree in all of the N output frequency bins of the DFT. In a conventional DFT, this can have the undesirable effect of masking out weaker signals that are present close to stronger ones in the input signal. This is called spectral leakage. The method employed by the AD5933 for reducing the effects of spectral leakage is the application of a windowing on the ADC output data. Windowing has the effect of reducing the energy contained in the side lobes of the sinc function. When the receive side input signal does not contain an integer number of cycles within the sample interval, the ADC output has spectral leakage as previously described.
AD5933 DFT DETAILS
The AD5933 method of determining the impedance (see the AD5933 datasheet for impedance calculation details) involves the use of the DFT. The DFT offers many benefits to the user: · Excellent dc rejection · Error averaging · Phase information The conventional DFT method assumes a sequence of periodic data samples x(n) which allows the user to determine the spectral content of the corresponding continuous signal. Internally, these samples come from the on-board 12-bit ADC of the receive side. The method employed by the AD5933 differs from the conventional DFT in that only a single frequency bin is transformed, rather than a fundamental and harmonics-it is, in fact, a single-point DFT as explained in the following section.
Single-Point DFT With the conventional DFT, a sequence of input samples x(n) are correlated with samples from a phasor. The frequency of this phasor is at integer multiples of a fundamental frequency given by Fs / N 1 . The correlation is performed for each frequency multiple if the resulting correlation of the phasor (consisting of both a sine and a cosine at that multiple frequency) is nonzero, there is energy in the input signal at that particular frequency bin. If no energy is found in a bin, there can be no energy at that test frequency. The single-point DFT implemented by the AD5933 ensures by design that the analysis frequency provided by the on-board DDS core is always the same. Therefore, the AD5933 is only analyzing energy at one particular frequency that is determined by the sweep parameters preprogrammed by the user. The single-point DFT calculated at each frequency point is given by Equation 7.
(x(n)(cos(n) - j sin(n)))
FS is the A / D sampling frequency.
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CLOCK DIVIDER CIRCUITRY
MCLK / 4 MCLK / 8 MCLK / 16
Scaling the sampling frequency increases the span of the sample window, creating coherent sampling required for accurate results. The following section details a clock dividing circuit used to scale the system clock at the MCK pin, enabling the AD5933 to analyze excitation frequencies below 10 kHz.
3.3V 3.3V R1 CLR D Q 74HC74 Q PR 3.3V 3.3V D Q 74HC74 Q PR 3.3V CLR
3.3V CLR D Q 74HC74 Q PR 3.3V 3.3V D Q 74HC74 Q PR 3.3V CLR
3.3V CLR Q D 74HC74 Q PR 3.3V 3.3V D Q 74HC74 Q PR 3.3V CLR
3.3V CLR Q D 74HC74 Q PR 3.3V 3.3V D Q 74HC74 Q PR 3.3V CLR D 3.3V CLR Q
12MHz / OSCILLATOR 74HC00
3.3V D Q 74HC74 Q PR 3.3V CLR
74HC74 Q PR
MCLK / 32
MCLK / 64
MCLK / 128
MCLK / 256
MCLK / 512
MCLK / 1024
Figure 7. Master Clock Dividing Circuitry
AN-843 LOUDSPEAKER IMPEDANCE MEASUREMENT
LOUDSPEAKER IMPEDANCE AND PHASE CALCULATION
Once the calibration process is finished, the loudspeaker replaces the calibration resistor. After the user issues a start frequency sweep command to the control register, the AD5933 automatically sequences through the user-defined frequency sweep. The frequency sweep is calculated by contents of the three registers (start frequency, frequency step, and number of increments register). Finally, the loudspeaker impedance at each frequency point is calculated, by the microprocessor communicating to the AD5933, by multiplying the gain factor by the magnitude of the complex code returned at each frequency by the AD5933.
SYSTEM CALIBRATION
However, prior to a valid impedance measurement, the AD5933 system must undergo a calibration process. The calibration process simply requires that a known precision metal film resistor be substituted for the impedance to be measured and a scaling factor (gain factor) is calculated for subsequent measurements. The gain factor calculation is given by the following formula:
Gain Factor Calibration Resistor
where R and I are the contents of the real and imaginary register (94 h to 97 h) at a chosen calibration point. The phase of the loudspeaker is calculated at each sweep point by subtracting the speaker phase from the calibration phase
where R and I are the contents of the real and imaginary register (94 h to 97 h) at a chosen calibration point.
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SYSTEM CLOCK SETTINGS
As explained in the section AD5933 DFT Details, the frequency of the clock applied to MCLK must be divided in order for the AD5933 to analyze excitation frequencies lower than 10 kHz accurately. Table 1 outlines the programmed sweep range and the corresponding clock frequencies applied to the MCLK pin of the AD5933 used in the test to cover the 20 kHz to 10 Hz bandwidth. The circuit shown in Figure 7 was used to provide the AD5933 clock frequencies for each subrange by binary division of a 12 MHz crystal oscillator As the start frequency is reduced by a factor of 2, the corresponding master clock frequency is halved. Table 2 outlines the programmed sweep parameters (start frequency, frequency increment, and number of increments) used in the test to cover the 20 kHz to 10 Hz bandwidth. As shown in Figure 3, the peak impedance typically occurs between 20 Hz to 40 Hz and so it is necessary to have a small frequency increment in this region of the loudspeaker impedance profile to capture the sudden change in impedance at resonance. As frequency increases from the resonant point, it is not necessary to measure such small changes in frequency for the remainder of the impedance profile. Increasing the step size reduces the required test time and increases the span of impedance profile measured for a fixed number of increments. The frequency step size was set to 1 / 10th of the start frequency in every sweep. Therefore, as the start frequency for the sweep increased, the frequency step size increased proportionally. The AD5933 number of settling time cycle register was set at 15 output cycles throughout the experiment, and the number of increments was set to 99 point.
Table 1. AD5933 MCLK Values vs. Sweep Range
AD5933 Sweep Range 20 kHz to 10 kHz 10 kHz to 5 kHz 5 kHz to 2.5 kHz 2. 5 kHz to 1.25 kHz 1.25 kHz to 625 Hz 625 Hz to 312.5 Hz 312.5 Hz to 156.25 Hz 156.25 Hz to 78.125 Hz 78.125 Hz to 39.125 Hz 39.125 Hz to 19.53 Hz 19.53 Hz to 9.76 Hz Clock Frequency Applied to MCLK pin 12 MHz 6 MHz 3 MHz 1.5 MHz 750 kHz 375 kHz 187.5 kHz 93.75 kHz 46.875 kHz 23.437 kHz 11.71 kHz
The AD5933 frequency sweep is determined by the contents of the start frequency, frequency increment, and number of increments register programmed by the user via the I2C interface. See the AD5933 data sheet for more details on performing a frequency sweep.
Table 3 outlines the AD5933 sweep parameters for the four sweeps required to span a frequency of 20 kHz to 1.25 Hz.
Table 2. AD5933 Programmed Sweep Register Values
1 2 3 4 5 6 7 8 9 10 11 AD5933 Sweep Range 20 kHz to 10 kHz 10 kHz to 5 kHz 5 kHz to 2.5 kHz 2.5 kHz to 1.25 kHz 1.25 kHz to 625 Hz 625 Hz to 312.5 Hz 312.5 Hz to 156.25 Hz 156.25 Hz to 78.125 Hz 78.125 Hz to 39.12 Hz 39.125 Hz to 9.53 Hz 19.53 Hz to 9.76 Hz Programmed Start Frequency 10 kHz 5 kHz 2.5 kHz 1.25 kHz 625 Hz 312.5 Hz 156.25 Hz 78.125 Hz 39.125 Hz 19.53 Hz 9.76 Hz Programmed Frequency Increment 100 Hz 50 Hz 25 Hz 12.5 Hz 62.5 Hz 31.5 Hz 15.625 Hz 7.8125 Hz 3. 9125 Hz 1.953 Hz 0.0976 Hz Programmed No. of Increments 99 99 99 99 99 99 99 99 99 99 99
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As outlined in the AD5933 data sheet, the start frequency is a 24-bit word that is programmed to the on-board RAM at Address 82h, Address 83h, and Address 84h (see the AD5933 data sheet register map). The required code loaded to the start frequency register is the result of Equation 11, based on the master clock frequency and the required start frequency output from the DDS:
Start Frequency Code
For example, if the user requires the sweep to have a resolution of 100 Hz and has a 12 MHz clock signal connected to MCLK, the code that needs to be programmed is given by
00117 hexidecimal
Frequency
(15) The user programs 00 hex to Register 85 h, 11 hex to Register 86 h, and 79 hex to Register 87 h. The third parameter used to define the frequency sweep is the number of increments register. This is a 9-bit word that represents the number of frequency points in the sweep. The number is programmed to the on-board RAM at Address 88 h and Address 89 h (see the AD5933 data sheet register map). The maximum number of points that can be programmed is 511. For example, if the sweep needs 99 points, the user programs 00 hex to Register 88 h and 63 hex to Register 89 h. Table 3 shows the required sweep codes and the various clock frequencies on which the codes are based. Because the master clock and the start frequency / frequency increment values scale equally by 2 in the binary division algorithm implemented, the start frequency code, the frequency increment code, and the number of increment codes are equal for each sweep. This means that the user only has to write to these three registers once for the entire test. However, to ensure an equal division by 2 each time, the user must ensure that the circuit in Figure 7 produces a clean clock signal at each output, that the reference clock is stable, and that jitter is minimized.
(12) For example, looking at the first row of Table 3, if the user requires the sweep to begin at 10 kHz and has a 12 MHz clock signal connected to MCLK, the code that needs to be programmed is given by
Start Frequency Code
06D3A0 hexidecimal
(13) The user programs 06 hex to Register 82 h, D3 hex to Register 83 h, and A0 hex to Register 84 h. Similarly, the frequency increment register is a 24-bit word that is programmed to the on-board RAM at Address 85 h, Address 86 h, and Address 87 h (see the AD5933 data sheet register map). The required code loaded to the frequency increment register is the result of the formula shown in the Equation below, based on the master clock frequency and the required increment frequency output from the DDS.
Increment
Table 3. AD5933 Required Sweep Codes for Frequency Range 20 kHz to 1.25 kHz
Programmed Start Frequency / Required Start Frequency Code 10 kHz 06D3A0 hex 5 kHz 2.5 kHz 1.25 kHz 06D3A0 hex 06D3A0 hex 06D3A0 hex Programmed Frequency Increment / Required Frequency Increment Code 100 Hz 001179 hex 50 Hz 25 Hz 12.5 Hz 001179 hex 001179 hex 001179 hex Programmed No. of Increments / Required No. of Increments Code 99 0063 hex 99 99 99 0063 hex 0063 hex 0063 hex Clock Frequency Applied to MCLK 12 MHz 6 MHz 3 MHz 1.5 MHz
AN-843 RESULTS
The system in Figure 4 was calibrated with a precision value 27.4 resistor and a gain factor was calculated at each frequency point in the sweep using the sweep codes and clock frequencies as outlined in Table 3. The values were stored in memory in a nearby microcontroller. The calibration resistor was replaced by a commercial 5 1 / 4 inch commercial loudspeaker and the sweep was repeated. The impedance was calculated at each frequency point by multiplying the gain factor by the corresponding code at each frequency, as shown in Equation 8 and Equation 9. The final impedance profile as measured by the AD5933 is shown in Figure 8.
The same experiment was measurement was repeated using the same loudspeaker but this time using a commercial USBbased loudspeaker impedance test unit that required a similar calibration process at each frequency with a 27.4 resistor, prior to making the final impedance measurement. The results of the measurement are shown in Figure 9.
50 40 30 20 50 40 30 20 10 0 -10 -20 -30 -40 10 100 1k FREQUENCY (Hz) 10k
IMPEDANCE ()
10 0 -10 -20 -30 -40 -50 10 100 1k FREQUENC Y (Hz) 10k
PHASE (Degrees)
-50 20k
Figure 9. Loudspeaker Impedance and Phase Results as Measured by the AD5933 vs. a Commercial Loudspeaker Impedance Test Unit
CONCLUSION
The AD5933 provides a highly accurate and low cost solution to loudspeaker impedance measurement compared to expensive commercial devices. Along with the AD5933, only a few external components are required to incorporate the simple test circuitry into the audio chain at the expense of minimum board space. The impedance profile can be evaluated upon system power-up with minimal effort, providing a simple means of characterizing the loudspeaker acoustics and examining the effects of the loudspeaker enclosure so that aging and damage changes can be identified.
Figure 8. Loudspeaker Impedance and Phase Results as Measured by the AD5933
PHASE (Degrees)
IMPEDANCE ()
AN-843 NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.