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AN-8015 FMS6501 Evaluation Board Application Note FMS6501 evaluat
Top Searches for this datasheetAN-8015 FMS6501 Evaluation Board Application Note AN-8015 FMS6501 Evaluation Board Application Note FMS6501 evaluation board full functional 12x9 cross point matrix evaluating performance FMS6501. demo board operates from standard supply voltages +3.3V ±5%. This device driven DC-coupled output AC-coupled input signal inputs programmed clamp bias mode. Device outputs either coupled also programmed gain 12dB. addition unused outputs disabled reduce power dissipation. FMS6501 provides inputs that routed outputs. Each input routed more output only input routed output. Programming FMS6501 controlled inputs manual register data settings Applications Cable Satellite boxes HDTV sets switches Security/surveillance Personal Video Recorders (PVR) Video distribution Automotive (in-cabin entertainment) complete description FMS6501 please refer FMS6501 data sheet. Evaluation Board Block Diagram OUT1 OUT2 OUT3 OUT4 FMS6501 OUT5 OUT6 OUT7 OUT8 Address IN10 Data OUT9 IN11 IN12 5.3V Connector AN-8015 Rev. www.fairchildsemi.com ©2006 Fairchild Semiconductor Corporation AN-8015 FMS6501 Evaluation Board Application Note Evaluation Contents FMS6501 Evaluation contains following items: AN-8015 FMS6501 Evaluation Board Application Note latest revision FMS6501 data sheet, which also obtained from http://www.fairchildsemi.com. Fully functional FMS6501 eval board VIPDEMOcontrol software Female power connector Connect monitor Out2. Connect monitor Out3. Turn power supplies. Check that address select jumper place. This sets device address Execute VIPDEMOcontrol software clicking demo icon. test setup configuration diagram below. Click "Show Config" button verify that Bus_Addr 0x06. Program Bias, bias bias mode. Program out1, Out2 Out3. Program Out1 6dB, Out2 Out3 6dB. Program "ON" Out1 enable, Out2, enable Out3 enable. Verify monitor setup receive signals. Verify test pattern that produced from signal generator same pattern monitor. Example 100% color bars. Testing complete Board Setup Test following test equipment necessary fully test FMS6501 evaluation board. Installed VIPDEMOcontrol software program control FMS6501. (follow directions Power supplies ±5%, 250mA +3.3v ±5%, 250mA high resolution monitor (YC, GBR, Component) HDTV monitor (480I, 480P, 720I, 720P, 1080I) NTSC video signal source capable generating necessary outputs. (GBR, Composite) PS/HD video signal source capable generating necessary outputs. (480I, 480P 720I, 720P, 1080I) video measurement (VM700) video measurement (VM5000) Assorted video cables turn power supply until connections completed. power supply 5.0V supply +3.3V. Connect power supplies input voltage terminals demonstration board. Connect GOUT signal source input connector. Connect BOUT signal source input connector. Connect ROUT signal source input connector. Connect monitor Out1. Figure VIPDEMOTest Setup Configuration www.fairchildsemi.com AN-8015 Rev. 3.3V 10uF 3.3V +3.3V 22uF ZM4730 4.7uF .1uF AN-8015 FMS6501 Evaluation Board Application Note AN-8015 Rev. Across outputs coupled outputs only 0.1u 220u OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 IN10 IN11 IN12 IN10 IN11 IN12 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 ADDR OUT7 OUT8 OUT9 FMS6501 Addr Select Figure FMS6501 Schematic Diagaram 22uF ZM4735 10uF 4.7uF .1uF www.fairchildsemi.com AN-8015 FMS6501 Evaluation Board Application Note 3.3V 74HC166 74HC166 www.fairchildsemi.com reset clock parallel load Load Momentary Reset Acknowledge load serial Address 3.3V ACE1502 RESET/ 3.3V 3.3V Figure Input/Manual Register Data Control Schematic Diagaram serial 3.3V Data 3.3V 3.3V U3,4,5 .001 .47u 3.3V AN-8015 Rev. AN-8015 FMS6501 Evaluation Board Application Note Configuration OUT1 OUT2 OUT3 Assignments IN10 IN11 IN12 ADDR OUT9 OUT8 OUT7 GNDO VCCO OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 Type Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input, channel Input, channel Input, channel Input, channel Input, channel Input, channel FMS6501 SSOP OUT4 OUT5 OUT6 VCCO GNDO OUT7 OUT8 OUT9 Positive power supply Must tied Input, channel Input, channel Input, channel Input, channel Input, channel Input, channel Selects address. 0x06 (0000 0110), 0x86 (1000 0110) Serial clock port Serial data port IN10 IN11 IN12 ADDR Output Output, channel Output Output, channel Output Output, channel Input Input Must tied Positive power supply output drivers Output Output, channel Output Output, channel Output Output, channel Output Output, channel Output Output, channel Output Output, channel AN-8015 Rev. www.fairchildsemi.com AN-8015 FMS6501 Evaluation Board Application Note Bill Materials Item Quantity C20, C7-C9, C17-C26 CC18, C19, C37, C33, C34, C35, FB1, FB2, RP2, R17, R18, R20, R1-R29 R30-R38 Reference Part 0.1µF 0.001µF 0.01µF 0.47µF 22µF 0.1µF 4.7µF 10µF ZM4735 ZM4730 Inductor Jumper (stuff option) DIP-8 Load Reset FMS6501 ACE1502 74HC166 www.fairchildsemi.com AN-8015 Rev. AN-8015 FMS6501 Evaluation Board Application Note Applications Information Input Clamp/Bias Circuitry FMS6501 accommodate either coupled inputs. Internal clamping bias circuitry provided support coupled inputs. These selectable through CLMP bits compatible interface. coupled inputs, device should programmed 'bias' input configuration. this configuration, input internally biased 625mV through 100k resistor. Distortion optimized with output levels between 250mV above ground 500mV below power supply. These constraints along with desired channel gain need considered when configuring input signal levels input coupling. With coupled inputs, FMS6501 uses simple clamp rather than full DC-restore circuit. video signals with without sync, (Y,CV,GBR) lowest voltage output pins will clamped approximately 300mV above ground when gain setting selected. symmetric coupled input signals used, (chroma, bias circuit mentioned above used center them within input common range. average value output will approximately 1.27V with gain setting. This value will change, depending upon selected gain setting. Video source must AC-coupled 0.1uF FMS6501 Input Bias Lowest voltage 625mV Figure Bias Mode Input Circuit Output Configuration FMS6501 outputs either coupled. Resistive output loads representing dual doubly terminated video load. High impedance, capacitive loads 20pF also driven without loss signal integrity. standard video loads matching resistor should placed series allow doubly terminated load. coupled outputs should connected follows: Gain Setting Clamp Voltage 300mV 330mV 370mV 420mV Bias Voltage 1.27V 1.43V 1.60V 1.80V FMS6501 Output Amplifier following diagram shows clamp mode input circuit internally controlled voltage input coupled inputs: Figure DC-Coupled Load Connection AC-coupled loads should configured shown Figure 0.1uF Video source must AC-coupled FMS6501 Input Clamp Lowest voltage 125mV FMS6501 Output Amplifier 220uF Figure Clamp Mode Input Circuit following diagram shows bias mode input circuit internally controlled voltage input coupled inputs. Figure AC-Coupled Load Connection AN-8015 Rev. www.fairchildsemi.com AN-8015 FMS6501 Evaluation Board Application Note Thermal Considerations multiple impedance loads coupled, increased power thermal issues will need addressed. this case, multi-layer board with large ground plane help dissipate heat recommended. 2-layer board used under these conditions, extended ground plane directly under device recommended. This plane should extend least 0.5" beyond device. Other board layout issues covered "Layout Considerations" section. Thermal issues significantly reduced with coupled outputs, alleviating need special layout requirements. Each FMS6501 outputs independently disabled placed high impedance state with ENABLE bit. This function used mute video signals, parallel multiple FMS6501 outputs, save power. When output amplifier disabled, high impedance output presents load ground. output amplifier will typically enter recover from power down state less than 300ns after being programmed. When output channel connected input, input that particular channels amplifier forced approximately 150mV. output amplifier still active, unless specifically disabled interface. Voltage output levels will depend programmed gain that channel. Applications FMS6501 Video Switch Matrix increased demand consumer multimedia systems created large challenge system designers provide costeffective solutions capitalize growth potential graphics display technologies. These applications will require cost effective video switching filtering solutions deploy highquality display technologies rapidly effectively target audience. Areas specific interest include HDTV, Media Centers, Automotive Infotainment (includes navigation, cabin entertainment, back camera). cases, advantages integrated video switch matrix provides high quality video switching specific application well video input clamps chip impedance output cable drivers with selectable gain. Generally largest application video switch front HDTV. This used take multiple inputs route them their appropriate signal paths (main picture picture picture PiP). These normally routed into ADCs that followed decoders. There many different technologies HDTV including: LCD,Plasma, that have similar analog switching circuitry. VIPDEMOControl Software FMS6501 configured compatible digital interface. order facilitate ease demonstration, Fairchild Semiconductor developed VIPDEMOGUI based control software write FMS6501 register map. This software included when ordering FMS6501DEMO kit. Also included Parallel port adapter interface cable connect demo board. Besides using full FMS6501 interface, VIPDEMOcan also used control single register read writes I2C. Layout Considerations General layout supply bypassing play major roles high frequency performance thermal characteristics. FMS6501DEMO 4-layer board with full power ground plane. optimum results your system board, follow steps below basis high frequency layout: Include 10µF 0.1µF bypass capacitors Place 10µF capacitor within 0.75 inches power Place 0.1µF capacitor within inches power Connect external ground pins tightly possible, preferably with large ground plane under package Layout channel connections reduce mutual trace inductance Minimize trace lengths reduce series inductances. routing across board, place device such that longer traces inputs rather than outputs using multiple, impedance coupled outputs, special layout techniques employed help dissipate heat. multi-layer board used, large ground plane directly under device will help reduce package case temperature. dual layer boards, extended plane used. Worse case additional power loading estimated (Vcc2/4Rload) output channel. This assumes constant output voltage Vcc/2. with dual video load, 25/(4*75) 83mW, channel. AN-8015 Rev. www.fairchildsemi.com AN-8015 FMS6501 Evaluation Board Application Note Manual Programming FMS6501 Individual Register Data Settings FMS6501 demo board populated with circuitry that will allow device programmed manual input register data settings. "EXT" jumpers will need moved "MAN" position accomplish this task. Register maps described detail FMS6501 datasheet. There registers that programmed control input output connections, output gain, output enable input common mode level settings. example would connect Out8, gain output enabled bias mode set. first register that needs programmed address 0x08. address data switches labeled logic low, logic high, MSB. settings data switches would settings data switches would Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 settings address would Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Press load button next data address. settings data switches would Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 settings address would Bit7 settings address would Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Press load button device programmed. Next press load button this will load address data into FMS6501. device bias mode, load following addresses data. AN-8015 Rev. www.fairchildsemi.com AN-8015 FMS6501 Evaluation Board Application Note DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES RIGHT MAKE CHANGES WITHOUT FURTHER NOTICE PRODUCTS HEREIN IMPROVE RELIABILITY, FUNCTION DESIGN. FAIRCHILD DOES ASSUME LIABILITY ARISING APPLICATION PRODUCT CIRCUIT DESCRIBED HEREIN; NEITHER DOES CONVEY LICENSE UNDER PATENT RIGHTS, RIGHTS OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: critical component component life Life support devices systems devices support device system whose failure perform systems which, intended surgical implant into reasonably expected cause failure life body, support sustain life, whose support device system, affect safety failure perform when properly used accordance with instructions provided labeling, effectiveness. reasonably expected result significant injury user. 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