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DP83902EB-AT PC-AT Compatible DP83902 ST-NIC Ethernet Evaluation Board

National Semiconductor Application Note 752 May 1993

DP83902EB-AT PC-AT Compatible DP83902 ST-NIC Ethernet Evaluation Board
National Semiconductor Application Note 752 May 1993
HARDWARE FEATURES Half-size IBM PC-AT I O Card Form Factor Y Utilizes DP83902 Serial Network Interface Controller for Twisted Pair (ST-NIC) Y 16 Kbyte on-board Packet Buffer Y Simple I O port interface to IBM PC-AT Y Interfaces to Thick Ethernet Thin Ethernet and Twisted Pair Y Boot EPROM Socket The detailed schematics for this design are shown at the end of this document
NETWORK INTERFACE OPTIONS The evaluation board supports three physical layer options Thick Ethernet Thin Ethernet and Twisted Pair The block diagram for these interfaces can be seen in Figure 1 When using Thick Ethernet a drop cable is connected to an external transceiver which is in turn connected to a standard Ethernet network eliminating the need for an internal transceiver This configuration may be obtained by connecting the pins on JB3 while leaving JB2 open and connecting JB9 (AUTP) to VCC
FIGURE 1 Physical Layer Adapter Interface Block Diagram
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TRI-STATE is a registered trademark of National Semiconductor Corporation ST-NIC is a trademark of National Semiconductor Corporation IBM and PC-AT are registered trademarks of International Business Machine Corporation PAL is a registered trademark of and used under license from Advanced MicroDevices Inc C1995 National Semiconductor Corporation TL F 11158 RRD-B30M115 Printed in U S A
When using Thin Ethernet a transceiver (the CTI) is available on-board to allow the evaluation board to directly connect to the network This transceiver (the CTI) forms the link between the differential ECL signals of the SNI module and the non-differential ECL signal of the thin-wire coaxial cable A DC-DC Convertor is provided on the board to supply the CTI with b9V isolated voltage source The Thin Ethernet solution is made by connecting the pins on JB2 leaving JB3 open and JB9 (AUTP) should be connected to VCC When using the Twisted Pair JB9 (AUTP) needs to be connected to ground The ST-NIC allows direct connection to the network using the RJ-45 phone jack The remaining circuitry includes pre-emphasis resistors a filter a transformer filter and a common mode choke The transformer filter decouples the DC component and eliminates any possible voltage spikes
The diagram in Figure 2 illustrates the layout of the board It shows the various jumpers ICs LEDs and the connectors for the three physical layer options The transmit pre-emphasis resistors R27 - R30 provide equalization to the twisted pair transmit outputs This boosts the higher harmonics of the signal in order to compensate for losses in these harmonics over the twisted pair cable R19 and R20 are 50X each and when combined form the required 100X termination on the receive side BUS INTERFACE The block diagram Figure 3 illustrates the architecture of the ST-NIC Evaluation Board The ST-NIC Board as seen by the system appears only to be an I O port With this architecture the ST-NIC board has its own local bus to access the board memory The system never has to intrude further than the I O ports for any packet data operation This I O architecture isolates the system bus and the local bus thereby preventing interference by the system when the STNIC is doing real-time accesses such as transmitting and receiving packets
FIGURE 2 Layout of ST-NIC Evaluation Board
BOARD ARCHITECTURE I O Map of ST-NIC Board The ST-NIC Board requires a 32-byte I O space to allow for decoding the data buffers the reset port and the ST-NIC registers The first 16 bytes (300h-30Fh) are used to address the ST-NIC registers (8 bits wide) and the next 8 bytes (310h - 317h) are used to address the data buffers which are 16 bits wide Finally the reset port (also software selectable) may be addressed by 318h-31Fh TABLE I I O MAP in PC-AT
Address 300h-30Fh 310h-317h 318h-31Fh
Part Addressed ST-NIC Chip Select Data Buffers Reset
RAM 4000h 3FFFh PROM 0000h
Although in the description above the I O map is positioned at the addresses 300-31F it may also be placed in the following address spaces 320-33F 340-35F 360 - 37F
This factory configuration is shown in Figure 4 along with the factory configurations for JB1 JB5 JB6 JB7 JB8 and JB9 The square pin indicates pin 1 of the jumpers
FIGURE 4 Factory Configuration for JB1 JB4 JB5 JB6 JB7 JB8 and JB9
APPENDIX A The following tables show all of the various jumper settings The shaded boxes are the Factory Configuration default settings JB1 High Low JB5 High Low JB6 High Low JB7 High Low JB8 High Low JP1 On On Off Off JP0 On Off On Off Link Enabled Link Disabled EPROM Address Base Address Tx a and Txb are same in idle state Tx a is positive with respect to Txb in idle state Normal Operation ENDEC Module Testing Internal Function Testing Normal Operation EPROM Address C800h CC00h D000h D400h JB9 Low High High INT9 On Off Off Off JB2 X On Off INT3 Off On Off Off JB3 X Off On INT4 Off Off On Off Physical Layer Selected Twisted Pair Thin Ethernet Thick Ethernet INT5 Off Off Off On Interrupt Selection Interrupt 9 Interrupt 3 Interrupt 4 Interrupt 5
Base Address 300h-31Fh 320h-33Fh 340h-35Fh 300h-37Fh
enable signal (NIOEN) loops back into the PAL to bring NIO16 out of TRI-STATE The NIO16 signal is set to zero so that whenever it is enabled it will be asserted The STNICB signal consists of simple address decodes along with NAEN The addresses decode to one of four address slots which were mentioned earlier in the board configuration section The NCSROM is a very simple signal as it consists only of AD14 and NMRD AD14 comes from the ST-NIC and selects either the PROM (when low) or the onboard RAM (when high)
TL F 11158-6
TABLE IV R - S Flip Flop Truth Table S (NIOW) 0 1 0 0 0 1 Q (NRESET) 0 1 1 0 0 1 Q (NSOUT) 1 0 0 1 1 0
In this PAL there are eight outputs NRESET NSOUT NRDYEN NIOCHRDY NCS NRACK NWACK and INTO The first two outptus (NRESET and NSOUT) are part of an R - S flip flop as shown below
FIGURE 5 RS Flip-Flop NRESET is given by the NOR of the high asserted R-input pin and the NSOUT signal NSOUT is given by the NOR of the high asserted S-input pin and the NRESET signal The NOR gates are enabled by the low assertion of NRSTDRV When the system first boots up it will disable the NOR gates by asserting the RSTDRV signal But due to the pullup and pull-down resistors the output kNRESET NSOUTl will be set to k0 1l Once RSTDRV becomes deasserted the output will remain at k0 1l The only way to get out of reset is to assert the S-pin high which is done by an NIOW and an address decode to 318-31F After the system has booted up the ST-NIC may be reset through software This would be done by setting the R-pin high with an NIOR and an address decode to 318-31F To escape from reset we once again set the S-pin high with an NIOW and address decode of 318-31F The above description of logic is also shown in Truth Table VII
The third PAL only does a decode to enable the optional EPROM This decode consists of an address decode to C800h CC00h D000h or D400h depending on JP1 and JP0 as shown in the board configuration section JP2 must PAL 3
also be jumpered for selection of the EPROM NAEN a low asserted signal should be high to indicate that the DMA does not have control of the bus and the NSMRDC signal should be asserted high since the CPU is doing a system memory read
Note ETHERNET ID PROM ADDRESS ASSIGNMENT Registration Authority for ISO IEC 8802-3 c o The Institute of Electrical and Electronics Engineers 445 Hoes Lane P O Box 1331 Piscataway NJ 08055-1331 (908) 562-3812 MAGNETICS (TRANSFORMER FILTER CHOKE DC-DC CONVERTOR ETC ) See Section 5 of databook Ethernet Magnetics Vendors SPARK GAP SUPPLIERS 0 75 pFkV Spark Gap Mallory Part ASR75A (317) 856-3731 Mepco Centralab Part S758X44000NAZAA Available from Philips Components Discrete Product Division (602) 820-2225
10K 4 7K 39 2 1M 270 1 5K 1K TBD 420 430 4 7K TBD 4 7K
PAL PAL
8K x 8 STATIC RAM PROM ST-NIC CTI
100 ns
EPROM (not supplied on board) Crystal Oscillator
MAGNETICS U14 T1 T2 PM7102 VALOR DC-DC Convertor PE64103 Pulse Engineering RX and TX Filter Transformer
Pulse Engineering PE65431
MISCELLANEOUS DS1 GREEN 5mm LOW CURRENT LED DS2 AMBER 5mm LOW CURRENT LED DS3 RED 5mm LOW CURRENT LED DS4 YELLOW 5mm LOW CURRENT LED DS5 GREEN 5mm LOW CURRENT LED JB1 1x3 SHUNT BLOCK WITH 1 JB2 2x6 SHUNT BLOCK WITH 1 JB3 2x6 SHUNT BLOCK WITH 1 JB4 2x6 SHUNT BLOCK WITH 1 JB5 - JB9 1x3 SHUNT BLOCK WITH 1
CURRENT4IF43 5m CURRENT4IF e 3 5 mA CURRENT4IF e 2 0 mA CURRENT4IF e 2 0 mA CURRENT4IF e 3 5 mA SPACING BETWEEN PINS SPACING BETWEEN PINS SPACING BETWEEN PINS SPACING BETWEEN PINS SPACING BETWEEN PINS
SOCKETS MECHANICAL S1 - S3 20 PIN 0 3 DUAL IN-LINE FOR U1 U2 U16 (PAL) S4 28 PIN DUAL IN-LINE SOCKET FOR U18 (EPROM) S5 84 PIN PLCC SOCKET FOR U13 (ST-NIC) AMP SOCKET S8 BRACKET FOR MOUNTING IN PC-AT SLOT G44 Basic Blank J3 RJ-45 CONNECTOR AMP 520252-4 J4 BNC CONNECTOR RT A Low Pro Amp 227161-7 J5 15 PIN D CONNECTOR Female AMP 747247-4 (or 747845-4) MAXCON SUB D Slide Lock MDA 51220-1 BOARD ATTACHMENT COMPONENTS 1) Screw Bind Head Slotted 4-40 x 2) Washer Lock Ext 4 Zinc Steel 3) Washer Flat 4 Zinc-CRS
Steel
(90277A106)
(91114A005) (90126A005)
TL F 11158 - 11
DP83902EB-AT PC-AT Ethernet Evaluation Board
APPENDIX D Bus Interface NIC Section
W unless otherwise indicated
Note EN16 is actually a ground signal on the AT Bus J2 Connector This signal is used to determine whether 8- or 16-bit mode should be used
DP83902EB-AT ST-NIC Ethernet Evaluation Board Schematic (Bus Interface NIC Section) 14
TL F 11158 - 10
DP83902EB-AT ST-NIC Ethernet Evaluation Board Schematic (Continued) (Bus Interface NIC Section)
DP83902EB-AT PC-AT Compatible DP83902 ST-NIC Ethernet Evaluation Board
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