DP83902EB-AT PC-AT Compatible DP83902 ST-NIC Ethernet Evaluation Board
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DP83902EB-AT PC-AT Compatible DP83902 ST-NIC Ethernet Evaluation Board
DP83902EB-AT PC-AT Compatible DP83902 ST-NIC Ethernet Evaluation Board
OVERVIEW National Semiconductor ST-NIC Evaluation Board design provides AT's Compatibles with Thick Ethernet Thin Ethernet Twisted Pair connections This parts count Evaluation Board compatible with requires only size slot insertion board uses DP83902 (ST-NIC) interface twisted pair Ethernet ST-NIC also Port which allows interface thick wire Ethernet thin wire Ethernet addition DP8392 Coaxial Transceiver Interface (CTI) dual (local remote) capabilities ST-NIC along with Kbytes buffer allow entire Network Interface Adapter appear standard Port system module's local channel buffers packets between local memory Kbytes buffer RAM) network while module's remote channel passes data between local memory system Port This Port architecture which isolates from network traffic proves simplest method interface DP83902 system
National Semiconductor Application Note 1993
HARDWARE FEATURES Half-size PC-AT Card Form Factor Utilizes DP83902 Serial Network Interface Controller Twisted Pair (ST-NIC) Kbyte on-board Packet Buffer Simple port interface PC-AT Interfaces Thick Ethernet Thin Ethernet Twisted Pair Boot EPROM Socket detailed schematics this design shown this document
NETWORK INTERFACE OPTIONS evaluation board supports three physical layer options Thick Ethernet Thin Ethernet Twisted Pair block diagram these interfaces seen Figure When using Thick Ethernet drop cable connected external transceiver which turn connected standard Ethernet network eliminating need internal transceiver This configuration obtained connecting pins while leaving open connecting (AUTP)
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FIGURE Physical Layer Adapter Interface Block Diagram
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TRI-STATE registered trademark National Semiconductor Corporation ST-NICis trademark National Semiconductor Corporation PC-AT registered trademarks International Business Machine Corporation registered trademark used under license from Advanced MicroDevices C1995 National Semiconductor Corporation 11158 RRD-B30M115 Printed
When using Thin Ethernet transceiver (the CTI) available on-board allow evaluation board directly connect network This transceiver (the CTI) forms link between differential signals module non-differential signal thin-wire coaxial cable DC-DC Convertor provided board supply with isolated voltage source Thin Ethernet solution made connecting pins leaving open (AUTP) should connected When using Twisted Pair (AUTP) needs connected ground ST-NIC allows direct connection network using RJ-45 phone jack remaining circuitry includes pre-emphasis resistors filter transformer filter common mode choke transformer filter decouples component eliminates possible voltage spikes
diagram Figure illustrates layout board shows various jumpers LEDs connectors three physical layer options transmit pre-emphasis resistors provide equalization twisted pair transmit outputs This boosts higher harmonics signal order compensate losses these harmonics over twisted pair cable each when combined form required 100X termination receive side INTERFACE block diagram Figure illustrates architecture ST-NIC Evaluation Board ST-NIC Board seen system appears only port With this architecture ST-NIC board local access board memory system never intrude further than ports packet data operation This architecture isolates system local thereby preventing interference system when STNIC doing real-time accesses such transmitting receiving packets
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FIGURE Layout ST-NIC Evaluation Board
BOARD ARCHITECTURE ST-NIC Board ST-NIC Board requires 32-byte space allow decoding data buffers reset port ST-NIC registers first bytes (300h-30Fh) used address ST-NIC registers bits wide) next bytes (310h 317h) used address data buffers which bits wide Finally reset port (also software selectable) addressed 318h-31Fh TABLE PC-AT
These alternate address spaces selected jumper pins (refer Figure Appendix DP83902's Local Memory There only items mapped into local memory space These items being buffer address PROM buffer used temporary storage transmit receive packets TABLE ST-NIC's Local Memory 7FFFh
Address 300h-30Fh 310h-317h 318h-31Fh
Part Addressed ST-NIC Chip Select Data Buffers Reset
4000h 3FFFh PROM 0000h
Although description above positioned addresses 300-31F also placed following address spaces 320-33F 340-35F
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FIGURE Block Diagram ST-NIC Evaluation Board's System Interface
transmit packets remote puts data from ports into local moves data from ST-NIC receive packets local carries data from ST-NIC remote moves data from ports address PROM (74S288 contains physical address evaluation board Each PROM holds unique physical address which installed during manufacture PROM also contains some identification bytes that checked driver software initialization evaluation board software commands ST-NIC transfer PROM data Port where read then loads ST-NIC's physical address registers following chart shows contents PROM TABLE PROM Contents PROM Location Location Contents Ethernet Address (Most Significant Byte) Ethernet Address Ethernet Address Ethernet Address Ethernet Address Ethernet Address Ethernet Address thru Reserved
EPROM SOCKET EPROM socket provided that user EPROM system This EPROM would normally contain program driver enable PC-AT booted through network chips necessary interface EPROM system 27128 (EPROM) 16L8 (PAL) 74ALS244 (buffer) Also must placed proper selection described jumper section decodes SA14 SA19 along with SMRDC (system memory read) order generate EPROMEN signal This signal issued when wants execute program stored EPROM enables EPROM buffer EVALUATION BOARD OPERATION following pages will describe slave accesses ST-NIC local remote operation Register Operations Accesses board register operations DP83902 which done ST-NIC control operation ST-NIC's channels REGISTER READ begin register read drives four address lines (SA0 SA3) ST-NIC address lines These address lines decoded order generate chip select ST-NIC also drives NIOR line which ST-NIC sees NSRD (slave read) Once ST-NIC receives this NSRD then sends high assertion NACK acknowledging that slave mode ready complete read NACK signal used assert IOCHRDY (used insert wait states) signal false ST-NIC then drives data from internal registers buffer buffer then enabled data driven onto When ST-NIC ready asserts NACK true asserts IOCHRDY true result NIOR driven high thereby deasserting NSRD rising edge NIOR data which latched into system addresses removed same time causing ST-NIC chip select become deasserted ending register read cycle REGISTER WRITE begin register write drives address lines ST-NIC address lines With these address lines decodes (the ST-NIC registers) thereby enabling chip select ST-NIC then drives NIOW strobe which ST-NIC sees NSWR (slave write) Once ST-NIC receives this NSWR sends back assertion NACK acknowledge that slave mode ready perform write When receives this signal puts data onto where goes into buffer buffer then drives data STNIC data latched into ST-NIC until rising edge NIOW system drives NIOW high thereby deasserting NSWR latching data addresses also taken away chip select then goes high (deasserted) This ends cycle register write
Data Address Paths following paragraph refer block diagram shown Figure Twenty address lines from onto ST-NIC Board only four them actually ST-NIC These four addresses along with NIOR (low-asserted read) NIOW (low-asserted write) (ST-NIC chip select signal) allow read write ST-NIC's registers system wants read from write ST-NIC registers data (only bits) must pass through buffer packet data will pass through ports (the 374's) Each unidirectional only drive bits therefore necessary have four 374's which drive data from ports board memory which drive data from ports Even PROM which only addressed ST-NIC sends bits data through 374's When PROM does this 374's will enabled only lower bits will read system also accessed STNIC However addressed bits drives bits data PALs receive address lines among many other signals such NIOR NIOW NACK With these signals PALs decodes such selecting ST-NIC Board ST-NIC chip PROM
Remote Transfers Remote transfers operations performed STNIC board These operations occur when ST-NIC programmed transfer packet data between PC-AT card's on-board These transfers take place through Port interface REMOTE READ program ST-NIC remote read must make five slave accesses ST-NIC must write Remote Start Address bytes) Remote Byte Count bytes) issue Remote Read Command addresses byte count require transfers because they both bits only bits written transfer Once ST-NIC received above data drives BREQ waits BACK ST-NIC immediately receives BACK because tied BREQ line (BREQ tied BACK because there other devices contending local After receiving BACK ST-NIC drives address from which data required read This address flows into 373's latched ADS0 From here address flows waits until receives from ST-NIC then drives data into ports ports then latch data rising edge strobe from ST-NIC then sent ST-NIC system know that there data waiting ports reads ports before ST-NIC loaded 374's then port request (PRQ) from ST-NIC will driven This unasserted signal causes AT's ready line indicating that ST-NIC load data After data ports system must then read data ports This begins with driving address which decoded (inside PAL) data Ports (310-31F) then drives RACK ST-NIC indicating that ready accept data This RACK signal then reads data from ports onto system deasserts NIOR which finishes cycle REMOTE WRITE Like remote read remote write cycle also begins with five slave accesses into internal registers must write Remote Start Address bytes) Remote Byte Count bytes) issue Remote Write Command ST-NIC then issues responds sending NIOW indicating that ready write ports also drives address which corresponds Ports This address goes into helps decode WACK This WACK signal latches data into ports ST-NIC issues BREQ immediately receives BACK since lines tied together (BREQ tied BACK because there other devices contending local ST-NIC upon receiving BACK drives address lines 373's These address lines latched ADS0 then driven ST-NIC sends NMWR which drives data from ports into already specified address onboard memory NMWR then deasserted cycle ends
Network Transfers Transfers from network controlled DP83902's local channel which transfers packet data from ST-NIC's internal FIFO from card buffer's RECEIVE data comes network deserialized stored FIFO inside ST-NIC ST-NIC then issues BREQ immediately receives BACK since lines tied together After receiving BACK ST-NIC drives address lines 373's 373's latched ADS0 address allowed flow Then ST-NIC drives NMWR along with data from FIFO data flows into under address given earlier NMWR strobe then deasserted ending cycle TRANSMIT begin transmit cycle ST-NIC issues BREQ waits BACK Since BREQ BACK lines tied together BACK signal received immediately Upon reception this signal ST-NIC drives address 373's which latch address with ADS0 strobe address then flows onboard memory NMRD driven ST-NIC causes drive data given address into ST-NIC ST-NIC then latches data into FIFO rising edge NMRD This high assertion NMRD signifies ending this cycle From FIFO data serialized transmitted onto network BOARD CONFIGURATION DP83902EB-AT ST-NIC board there nine jumper blocks seen diagram below following pages wiill explain configure these jumpers Physical Layer tied Ground then twisted pair interface will selected closed while open connected then Thin Ethernet option will selected finally closed while open high then Thick Ethernet option will selected Refer Appendix Jumper settings Interrupt Lines Board Addresses EPROM Addresses there possible connections Four these select interrupt line available interrupt lines include INT3 INT4 INT5 INT9 last possible connections used select base address board However connected then these last connections select address EPROM also possible selections jumpers shown Appendix factory configuration uses INT3 line interrupts position
This factory configuration shown Figure along with factory configurations square indicates jumpers
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FIGURE Factory Configuration
APPENDIX following tables show various jumper settings shaded boxes Factory Configuration default settings High High High High High Link Enabled Link Disabled EPROM Address Base Address same idle state positive with respect idle state Normal Operation ENDEC Module Testing Internal Function Testing Normal Operation EPROM Address C800h CC00h D000h D400h High High INT9 INT3 INT4 Physical Layer Selected Twisted Pair Thin Ethernet Thick Ethernet INT5 Interrupt Selection Interrupt Interrupt Interrupt Interrupt
Base Address 300h-31Fh 320h-33Fh 340h-35Fh 300h-37Fh
APPENDIX EQUATIONS (U1) this first output signals NIO16 NIOEN NSTNICB NCSROM (The before signals indicate that signal asserted Since necessary assert NIO16 soon possible this first been selected ``D'' NIO16 signal must TRI-STATE when asserted Therefore enable signal (NIOEN) which equal decode Ports (310-31F) NAEN high (NAEN high signifies that system does have control bus)
enable signal (NIOEN) loops back into bring NIO16 TRI-STATE NIO16 signal zero that whenever enabled will asserted STNICB signal consists simple address decodes along with NAEN addresses decode four address slots which were mentioned earlier board configuration section NCSROM very simple signal consists only AD14 NMRD AD14 comes from ST-NIC selects either PROM (when low) onboard (when high)
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(NIOR)
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TABLE Flip Flop Truth Table (NIOW) (NRESET) (NSOUT)
this there eight outputs NRESET NSOUT NRDYEN NIOCHRDY NRACK NWACK INTO first outptus (NRESET NSOUT) part flip flop shown below
FIGURE Flip-Flop NRESET given high asserted R-input NSOUT signal NSOUT given high asserted S-input NRESET signal gates enabled assertion NRSTDRV When system first boots will disable gates asserting RSTDRV signal pullup pull-down resistors output kNRESET NSOUTl will Once RSTDRV becomes deasserted output will remain only reset assert S-pin high which done NIOW address decode 318-31F After system booted ST-NIC reset through software This would done setting R-pin high with NIOR address decode 318-31F escape from reset once again S-pin high with NIOW address decode 318-31F above description logic also shown Truth Table
using NIOR NIOW which never asserted same time this insures that R-pin S-pin will never asserted same time next signals (NRDYEN NIOCHRDY) quite similar NIOEN NIO16 decode takes place enable signal (NRDYEN) This decode consists addresses without NACK addresses without NRDYEN signal asserted then NIOCHRDY will driven other times NIOCHRDY strobe will TRI-STATE This must also ``D'' decoded NSTNICB (from along with assertion either NIOR NIOW decode address range last signals NRACK NWACK NRACK occurs with address decode NIOR NWACK signal only differs from NRACK NIOR NIOW signal therefore consists address decode NIOW just sent through buffered buffered signal which comes INTO
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third only does decode enable optional EPROM This decode consists address decode C800h CC00h D000h D400h depending shown board configuration section must
also jumpered selection EPROM NAEN asserted signal should high indicate that does have control NSMRDC signal should asserted high since doing system memory read
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APPENDIX BILL MATERIALS DP83902EB-AT ST-NIC ETHERNET ADAPTER CAPACITORS RESISTORS IC's
Note ETHERNET PROM ADDRESS ASSIGNMENT Registration Authority 8802-3 Institute Electrical Electronics Engineers Hoes Lane 1331 Piscataway 08055-1331 (908) 562-3812 MAGNETICS (TRANSFORMER FILTER CHOKE DC-DC CONVERTOR Section databook Ethernet Magnetics Vendors SPARK SUPPLIERS pFkV Spark Mallory Part ASR75A (317) 856-3731 Mepco Centralab Part S758X44000NAZAA Available from Philips Components Discrete Product Division (602) 820-2225
Monolythic Tantalum Ceramic Disk Ceramic Disk Monolythic Spark Monolythic Tantalum Tantalum Monolythic Tantalum Monolythic Tantalum
16L8D 16L8B 74ALS245 74ALS374 HM6264 74AS373 74S288 DP83902 DP8392 74HC04N 27128 74ALS244
STATIC PROM ST-NIC
EPROM (not supplied board) Crystal Oscillator
MAGNETICS PM7102 VALOR DC-DC Convertor PE64103 Pulse Engineering Filter Transformer
Pulse Engineering PE65431
MISCELLANEOUS GREEN CURRENT AMBER CURRENT CURRENT YELLOW CURRENT GREEN CURRENT SHUNT BLOCK WITH SHUNT BLOCK WITH SHUNT BLOCK WITH SHUNT BLOCK WITH SHUNT BLOCK WITH
CURRENT4IF43 CURRENT4IF CURRENT4IF CURRENT4IF CURRENT4IF SPACING BETWEEN PINS SPACING BETWEEN PINS SPACING BETWEEN PINS SPACING BETWEEN PINS SPACING BETWEEN PINS
SOCKETS MECHANICAL DUAL IN-LINE (PAL) DUAL IN-LINE SOCKET (EPROM) PLCC SOCKET (ST-NIC) SOCKET BRACKET MOUNTING PC-AT SLOT Basic Blank RJ-45 CONNECTOR 520252-4 CONNECTOR 227161-7 CONNECTOR Female 747247-4 747845-4) MAXCON Slide Lock 51220-1 BOARD ATTACHMENT COMPONENTS Screw Bind Head Slotted 4-40 Washer Lock Zinc Steel Washer Flat Zinc-CRS
Steel
(90277A106)
(91114A005) (90126A005)
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Note resistors unless otherwise indicated Note Capacitors signals
DP83902EB-AT PC-AT Ethernet Evaluation Board
APPENDIX Interface Section
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Note resistors
unless otherwise indicated
Note EN16 actually ground signal Connector This signal used determine whether 16-bit mode should used
DP83902EB-AT ST-NIC Ethernet Evaluation Board Schematic (Bus Interface Section)
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DP83902EB-AT ST-NIC Ethernet Evaluation Board Schematic (Continued) (Bus Interface Section)
DP83902EB-AT PC-AT Compatible DP83902 ST-NIC Ethernet Evaluation Board
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