CMOS Converter Chips Easily Interface 8080A Microprocessor Systems

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CMOS Converter Chips Easily Interface 8080A Microprocessor Systems

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CMOS Converter Chips Easily Interface 8080A Microprocessor Systems
CMOS Converter Chips Easily Interface 8080A Microprocessor Systems
SUMMARY This paper describes techniques interfacing National Semiconductor's ADC3511 ADC3711 microprocessor compatible analog-to-digital converter chips 8080A microprocessor systems hardware interface software interrupt service routine will described single multiple converter data acquisition systems INTRODUCTION recent introduction monolithic digital voltmeter chips encouraged designers consider their analogto-digital converters data acquisition systems While high accuracy afforded cost attractive certain difficulties applying these devices digital systems were encountered Most these difficulties were chip's output structure being oriented towards driving 7-segment displays with internally generated digit scanning rates National Semiconductor recently introduced family monolithic CMOS converters these devices directed towards display applications (ADD3501 -digit ADD3701 -digit DPM) while other (ADC3511 -digit ADC3711 -digit have addressable outputs These last devices allow easy interface microprocessor calculator-oriented (COPS) systems
National Semiconductor Application Note March 1978
Single multiple channel monitoring physical variables achieved with high accuracy despite lack complexity overall cost CONVERSION converters this family operate from single supply convert inputs from converters pulse-width modulation technique which requires precision components exhibits offset drift high linearity rollover error additional advantage that voltage reference same polarity supply resolutions offered -digit types divide input into counts plus sign while -digit types provide counts plus sign which roughly equivalent resolution 12-bit plus sign binary converter -digit converters require conversion -digit types require converters handle negative inputs internally switching inputs forcing sign While this technique allows conversion positive negative inputs with only single supply supply must isolated from inputs Without isolated supply only positive voltages converted basic converter shown Figure actual conversion technique described Appendix
AN-200
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FIGURE Basic Converter
C1995 National Semiconductor Corporation
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RRD-B30M115 Printed
OUTPUT DESCRIPTION ADC3511 ADC3711 present output data form single 4-line output port plus separate sign output desired digit selected 2-bit address which latched high level Digit Latch Enable input (DLE) level allows flow thru operation Since output compatible with many standard instruments easily converted into binary processor this format should desired Overrange inputs indicated hexidecimal ``EEEE'' plus Overflow output conversion begun positive pulse high level Start Conversion (SC) input analog section converter continuously tracks analog input Start Conversion command controls only transfer data output latches consequently delay from pulse Conversion Complete (CC) signal vary from several milliseconds several hundred milliseconds interrupt driven systems delay problem since processor does execute delay instructions while waiting data However in-line program used where program waits data ready maximum delay between must programmed into wait routine This type therefore efficient interrupt output goes immediately after pulse conversion goes high remains high until conversion initiated Continuous conversion operation obtained tying input REFERENCE VOLTAGE 000V reference derived from LM336 recently announced monolithic reference which provides with drift cost This active reference adjusted minimum thermal drift about using third terminal device adjust output 490V Total reference current consumption LM336 requires only bias current resistor divider about reference circuit shown Figure reference used many values upper series resistor depends number converters used SINGLE CHANNEL CONVERTER complete port seen Figures Figure shows Dual Polarity converter Figure Positive Only Polarity converter Each port contains converter TRI-STATE driver gates control This port easily used single multi-channel systems multichannel systems converter used every channel allowing digital multiplexing outputs Data from converter single channel system easily processed using command start conversion commands read data after microprocessor been interrupted Conversion Complete seen Figure single channel port uses 6-bit comparator decode assigned peripheral address from lower address bits 8080A address When interrupt received present status processor stored stack memory series push commands interrupt serviced reading digit (MSD) into processor checking overflow overflow high converter input exceeded range error signal generated indicating that scaling must done attenuate input signal sign then checked determine polarity conversion sign ``1'' added digit Since this would normally (maximum converter range allows 0011) ``1'' this position used denote negative input voltage bits digit which include sign shifted into upper half first byte bits digit packed into lower half Similarly digits packed into second byte both bytes stored memory
Figure routine flow chart assembly language routine used implement this action
8-CHANNEL WITH SOFTWARE PRIORITY basic port easily expanded multiple channel systems 8-channel system seen Figure This system interrupts processor when Conversion Complete outputs goes high processor saves current status reads status word system status word then compared priority table Each level table corresponds priority level with high priority converters which first table more converters have same priority ready same time converter with highest number gets serviced first program determines which service routine position ``1's'' status word routine loads address pointer digit selected converter
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FIGURE Converter Reference Adjusted Voltage Output this Voltage Minimum Drift Occurs Reference Supply Converters
program then calls subroutine which goes through process checking overflow sign packs digits into bytes These bytes then stored table memory directly above converter addresses After
channel serviced original processor status restored interrupt enabled additional channels need service they immediately interrupt status word then read priority established
FIGURE Dual Polarity Requires that Inputs Isolated from Supply Input Range 999V
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FIGURE Positive Polarity Operating from Supply Input Range 999V
FIGURE Single Channel Interface with Peripheral Mapped
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FIGURE Flow Chart Single Channel Converter
LABEL ADIS
OPCODE PUSH PUSH PUSH
OPERAND
PLUS
PLUS
Routine Single Channel Interrupt Service Routine LABEL OPCODE OPERAND COMMENT interrupt service save current status input digit delay reset carry rotate thru carry overflow condition rotate sign thru carry ADMS positive input into input shift into position mask lower bits save input digit delay mask higher bits pack into save input digit
COMMENT delay rotate into upper bits mask lower bits save digit delay mask upper bits pack save load space save memory point next save memory start conversion restore previous status enable interrupts return main program
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FIGURE 8-Channel System with Maskable Priority Interrupt Using Memory Mapped
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FIGURE Flow Charts Routines
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FIGURE Flow Charts Routines (Continued) Routine 8-Channel Interrupt Service Routine with Software Priority LABEL OPCODE OPERAND OPERAND COMMENT XCGH interrupt from PCHL save stack INAD1 save stack CALL ADIN save stack ADWD pickup status DONE word INAD2 move word into PRTBL pickup priority CALL ADIN pointer place status word accum DONE mask with priority table FIND match jump Find point lower DONE priority TEST again RTBL pickup routine pointer reset carry rotate thru carry GTAD found PRTBL point next routine GTBIT again move first byte into point next byte move second byte into
LABEL
OPCODE PUSH PUSH PUSH PUSH
TEST
COMMENT exchange jump input routine pickup pointer call common input routine start conversion done pickup pointer call input routine start conversion done
FIND
GTBIT
restore restore restore restore enable interrupts return main program 0000C100 highest priority 0000011 next priority
GTAD
Routine 8-channel Interrupt Service Routine with Software Priority (Continued) LABEL OPCODE OPERAND COMMENT PRTBL 00010000 lowest priority RTBL 1000H routine 100CH routine LABEL OPCODE SHLD LHLD OPERAND COMMENT save point input delay rotate into upper bits mask lower bits save point input delay mask upper bits pack save store temp move accum generate lower address above memory mapped converter addresses include carry upper bits store then store retrieve return
ADIN PLUS PLUS 1060H routine Input plus SIGN delay reset carry rotate left thru carry jump overflow rotate left thru carry sign jump plus into minus
TEMP TEMP
mask lower order bits save point MSD-1 input MSD-1 delay mask higher bits pack MSD-1
ADJUSTMENT TESTING Adjustment testing single channel done monitoring memory space where interrupt routine stores data word microprocessor forced loop around section program with interrupts enabled input voltage converter changed this data word should also change converter updates precision voltage reference connected input incremental voltage steps applied data word should also change according voltage steps full-scale input voltage data word should maximum value check full-scale adjust adjusting goes high when input exactly 000V Multichannel systems more difficult check Start individually checking full-scale adjustments converters overflow 000V Check software priority routine forcing status bits status word high This corresponds converters being ready same time very unlikely worst-case condition microprocessor should respond outputting address digits port with highest priority along with memR strobes then with memW strobe start conversion next highest priority converter should then receive addresses memR strobes down line Once priority routine been debugged each data word monitored input converter adjusted Since common input routine used once channel operates other channels should also
Debugging most easily done single stepping through program these critical areas timing problems should encountered since port appears standard peripheral memory ADC3511 ADC3711 desired output merely addressed same memory location memory requirements interface depends course complexity system single channel converter requires approximately bytes program storage plus bytes data storage peripheral addresses multichannel system requires about bytes priority routine bytes program each converter routine common input routine requires about bytes program used converter routines form subroutine Memory mapped causes memory locations used input 8-channel system data space located directly above address space converters memory locations used store data converters CONCLUSION ADC3511 ADC3711 microprocessor compatible converters eliminate difficulties previously encountered applying chips microprocessor systems parts count cost channel make distributed remote conversion practical variety data acquisition applications
APPENDIX THEORY OPERATION schematic analog loop shown Figure output either VREF depending state flip-flop high level VOUT VREF level VOUT This voltage then applied pass filter comprised output this filter connected negative input comparator where compared analog input voltage output comparator connected input flip-flop Information then transferred from input outputs positive edge clock This loop forms oscillator whose duty cycle precisely related analog input voltage example will demonstrate this relationship Assume input voltage equal 500V output flipflop high then VOUT will equal 000V) will charge toward with time constant equal R1C1 some time will exceed 500V comparator output will switch next clock rising edge output flip-flop will switch ground causing VOUT switch this time will start discharging toward with time constant R1C1 When less than comparator output will switch high rising edge next clock output flip-flop will switch high process will repeat There exists output square wave pulse train with positive amplitude VREF negative amplitude
value this pulse train VOUT VREF VREF (duty cycle) tOFF
pass filter will pass value then VREF (duty cycle) Since closed loop system will always force equal then that VREF (duty cycle) (duty cycle) VREF duty cycle logically ANDed with input frequency resultant frequency equals (duty cycle) (fIN) Frequency accumulated counter time determined counter count contained counter then count (duty cycle) (fIN) (fIN) (fIN) VREF
ADC3511 2000 ADC3711 4000
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VREF (duty cycle) (duty cycle)
Count Counter
(duty cycle) VREF
FIGURE Analog Loop Schematic Pulse Modulation Converter
Electrical Characteristics
ADC3511CC ADC3711CC conv (ADC3511CC) conv (ADC3711CC) unless otherwise specified Parameter Non-Linearity Conditions (Note 0b2V Full-Scale 0b200 Full-Scale (Note
Units
Full-Scale Counts Counts
Organization Error Offset Error Rollover Error VINb Analog Input Current (Note
Note ``Absolute Maximum Ratings'' those values beyond which safety device cannot guaranteed Except ``Operating Range'' they meant imply that devices should operated these limits table ``Electrical Characteristics'' provides conditions actual device operation Note typicals given Note ADC3511CC full-scale 1999 counts therefore 025% full-scale counts full-scale count ADC3711CCL fullscale 3999 counts therefore 025% full-scale count full-scale counts Note full-scale 000V count ADC3511CC counts ADC3711CC
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FIGURE ADC3511 -Digit ADC3711
-Digit Block Diagram
CMOS Converter Chips Easily Interface 8080A Microprocessor Systems
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION used herein Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user
National Semiconductor Corporation 1111 West Bardin Road Arlington 76017 1(800) 272-9959 1(800) 737-7018
critical component component life support device system whose failure perform reasonably expected cause failure life support device system affect safety effectiveness
AN-200
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National does assume responsibility circuitry described circuit patent licenses implied National reserves right time without notice change said circuitry specifications

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