Application Note (Preliminary) Harris Mark Rootz Contents
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Design Tutorial, PSD813F1 80C31
Application Note (Preliminary)
Harris Mark Rootz
Contents
Introduction Design Example. Matching Functions PSD813F1 PSD8XX Functional Blocks PSDsoft Development Tools. PSDabel. Configuration. Fitter. Simulator Programmer. code Generation Design Flow. PSDsoft Program Flow. Tutorial Example. Managing Project PSDabel File 5.2.1 Compiling Tutor Design PSDsoft Configuration Fitter Fitting Address Translation. 5.4.1 Fitting Design. 5.4.2 Generating code. 5.4.3 Performing Address Translation. PSD8XX Chip Simulation 5.5.1 PSDsoft.run File. 5.5.2 Running Logic Simulator. 5.5.3 Running Analyzer 5.5.4 Working With Explorer Programming PSD8XX. 6.1.1 PSDpro. 6.1.2 JTAG FlashLink. PSD8XX Appendix AABEL Design FileTutor8xx.abl Appendix BStimulus FileTUTOR8XX.STL. Appendix CList PSD8XX Simulation Signals Appendix DDesign file EPM7064S Figure Appendix EDiscrete Solution (Figure Compared Integrated Solution (Figure Appendix FSystem Memory UART
Return Main Menu
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Introduction
This tutorial takes step-by-step through development cycle PSD8XX based design, from design entry programming device. first part this tutorial will show PSD813F1 used conjunction with handful other implement automatic gain control (AGC) design. tutorial also shows this design would implemented using discrete part solution, Appendix reveals various benefits using PSD8XX device versus discrete solution. members PSD813F family programmable system devices Flashbased peripherals embedded microcontrollers (MCUs) capable In-SystemProgramming (ISP). These PSDs easily connected variety 8-bit MCUs provide memory, logic, I/O. Embedded designs typically bound cost, size, power consumption. market products using embedded MCUs extremely competitive. Time-to-market quality features-per-dollar define success. Using PSD8XX device will reduce your cost, time-to-market, power consumption, board space, design complexity, chip count. read this document, will PSD813F1 will enhance your meet needs Flash memory, EEPROM, SRAM, configurable pins, programmable logic (both sequential combinatorial), decoded address space, address expansion, backup power, code integrity, code security, ISP. these features cost effective PSD813F1 device allows cost, minimal feature, ROMless device. addition giving step-by-step design entry information, this document highlights three areas: using concurrent memory JTAG, Micro-Cell technology, logic simulation capabilities PSDsilosIII. typical design with Flash memory consists MCU, main Flash memory, either boot PROM SRAM implement download main Flash memory over UART channel, some other communication link. systems that SRAM ISP, Flash programming algorithm must first downloaded SRAM then executes from SRAM during ISP. power interruption system glitches that occur will cripple system. Therefore, boot PROM necessity applications that demand high system reliability. However, boot PROM adds cost system difficult update once service. Flash PSDs address these concerns combines elements necessary enable easily download main Flash memory boot memory while in-system. method just described requires participation. Flash PSDs also offer another method, which uses JTAG interface, requiring participation. This means that completely blank that soldered place programmed insystem. WSI's JTAG FlashLink cable PSDsoft development software implement this powerful feature PSD8XX.
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Adding peripheral memory space involves great amount circuitry decode addresses lines, latch data, handle timing. This "overhead" circuitry required peripheral needed used since address, data, control signals already routed processed inside PSD. Micro-Cells take advantage this, allowing designer build logic peripherals inside efficient flexible manner. This tutorial will compare Micro-Cell design with equivalent functional design using Altera EPM7064S CPLD device emphasize efficiency PSD. PSD8XX Output Micro-Cells (OMCs) Input Micro-Cells (IMCs). Each Micro-Cell occupies memory location address space connected data bus. ability load flip-flops OMCs read them back useful such applications loadable counters, shift registers, other system logic. IMCs able latch external input, also read microcontroller. IMCs also useful implement handshake communication logic with outside source. designs simulated using PSDsilosIII simulation program. PSDsilosIII models devices using Verilog-HDL. Thus, designs simulated levels (from behavioral transistor level). PSDsilosIII also comes with Waveform Editor/Viewer Watch window (for stepping through simulations).
Design Example
Implemented this design example closed-loop Automatic Gain Control (AGC) function. analog receiver section Programmable Gain Amplifier (PGA) control signal level that output though envelope detection circuit. gain must adjusted real-time keep constant signal level envelope detection output. This output monitored Analog-to-Digital Converter (ADC). When function works properly, constant signal level output from receiver, which used other analog digital circuitry signal processing. block diagram below.
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DESIRED LEVEL 80C31 INTERRUPT BOOST TRIM
STATE MACHINE
AMPLIFIER GAIN CONTROL SETTING
CLOSED LOOP
CONVERTER
FILTER
MODULATED SIGNAL
BASE BAND SIGNAL ENVELOPE
RECEIVER
Block Diagram Automatic Gain Control circuit
could perform this real-time gain adjustment, would leave little execution time other tasks. highly desirable free offloading these repetitive tasks with hardware. will that moving some this function into state machine programmable logic shown block diagram above. this configuration, will load state machine with desired signal level, start state machine, wait interrupt from state machine when signal drifts from desired level. state machine this because reading outputs comparing measured value with desired value. state machine will provide additional signals with interrupt, `Trim' `Boost'. signal level from receiver high, interrupt will accompanied `Trim', will write appropriate value decrement gain. Likewise, signal level low, interrupt from state machine will accompanied `Boost'. Once this closed-loop process started, perform other tasks need only interrupted when gain correction required. This tutorial will show implement this function different ways: discrete solution (individual devices programmable logic, memory, etc.) integrated solution. addition function, other features implemented, such Real-Time-Clock (RTC), In-System Programmability (ISP), miscellaneous signals.
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Please refer Appendix information related system memory mapping, issues using UART, memory paging considerations. We'll look discrete solution first, which requires extra devices implement 80C31 application that 128K Flash memory, battery-backed SRAM, EEPROM, real-time clock (RTC), 8-bit analog-todigital converter (ADC), JTAG interface, EPM7064S CPLD, analog receiver circuit (including PGA). Following that, show Flash, EEPROM, SRAM, CPLD, battery backup circuit combined into PSD813F1 device. Let's look discrete solution shown Figure 80C31 MCUthis using external memory since internal program data storage sufficient. result, Port Port sacrificed address data. EPM7064SLC84-5 CPLDneeded address decoding, control logic, implementation paging/segmentation scheme Flash EEPROM, interfacing ADC. Refer Appendix complete design listing 29F010 Flash128K program memory. Notice that address lines A14-A16 driven CPLD support additional address space. A128C256 EEPROM32K boot memory. Allows concurrent programming Flash. Address lines A13-A14 driven CPLD support additional address space. DP8572A RTCprogrammable Real-Time Clock used time-stamp various data received MCU. LH51162K SRAM configured with battery backup protection. Generic 8-bit ADCConverts target signal envelope into digital value. This controlled CPLD. Receiver CircuitCollection components that make signal receiver circuit including: Pre-Amp, mixer, Local Oscillator (LO), PGA, Envelope Detector circuit. circuit takes signal through antenna input outputs signal envelope. 7414 Inverter with hysteresisU7B used provide stable reset signal (U1). part battery backup circuit SRAM.
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U10: Generic OPAMP comparatorPart battery backup circuit SRAM. When sags below battery voltage, circuit switches over battery, which then powers SRAM.
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P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 PSEN ALE/P PSEN/ PSEN/ EPM7064S FLASH_A14 FLASH_A15 FLASH_A16 FLASH_CS/ FLASH_OE/ FLASH_A14 FLASH_A15 FLASH_A16 FLASH_CS/ FLASH_OE/
EA/VP RESET INT0 INT1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 80C31
Pushbutton With Debounce Reset
7414 RTC_INTR/ AGC_INTR/ RESET/
EEPROM_A13 EEPROM_A14
I/O0 1/01 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
TRIM BOOST
EEPROM_OE/ EEPROM_CS/
EEPROM
I/OE1 I/OE2/GCLK2
AT28C256
128K FLASH
RTC_CS/
29F010 RESET/ Clock AGC_INT/ I/GCLR I/GClk1 ADC_OUT7 ADC_OUT6 ADC_OUT5 ADC_OUT4 CONV_START/ SRAM_CS/ SRAM_OE/ EEPROM_A13 EEPROM_A14 EEPROM_OE/ EEPROM_CS/ RTC_CS/
JTAG Connector
System Clock
RS232 PORT
Osc_In Osc_Out
CPLD
INTR
RTC_INTR/
DP8572A CONTROL0 CONTROL1 CONTROL2
32.768
HEADER
BOOST TRIM PGA_Din2 PGA_Din1 PGA_Din0
Control0 Control1 Control2
LH5116 I/O1 1/02 I/O3 I/O4 1/O5 1/O6 I/O7 I/O8
ADC_OUT4 ADC_OUT5 ADC_OUT6 ADC_OUT7
PGA_Din2 PGA_Din1 PGA_Din0
SRAM_Vcc
ConvStart
SRAM_CS/ SRAM_OE/
SRAM
ANTENNA
(Receiver)
CONV_START/
PreAmp
COMPARATOR
Filter
Vout
Envelope Detector
ENVELOPE_OUT
7414
LITHIUM BATTERY
Size Date:
Document Number Tutorial- -Before Integration Friday, July 1998 Sheet
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PRELIMINARY
Now, let's compare integrated design Figure discrete Figure memory (U3, U6), battery backup circuit (U9A, U10) Figure incorporated into PSD813F1 (U2) Figure Also, functions handled CPLD Figure taken care PSD's CPLD. pins individually configured match functions implemented original design. Using JTAG, entire PSD8XX device programmed. Also, JTAG pins multiplexed with other I/O. These JTAG features beyond capabilities EPM7064S.
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RTC_CS/
INTR
Osc_In Osc_Out
RTC_INT/
DP8572A
EA/VP RESET INT0 INT1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 80C31 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 PSEN ALE/P
32.768 CONTROL0 CONTROL1 CONTROL2 PGA_DIN0 PGA_DIN1 PGA_DIN2 ADC_OUT4 ADC_OUT5 ADC_OUT6 ADC_OUT7
Pushbutton With Debounce Reset
7414 7414
RESET AGC_INT/ RTC_INT/
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
PSEN/
PSEN/
ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 CNTL1 CNTL0 CNTL2
Control0 Control1 Control2
TRIM BOOST
74HC126 (TMS) (TCK) (VSTBY) (TSTAT) (TERR) (TDI) (TDO) TMS; AGC_INT/ TCK; START_CONV/ TSTAT; TRIM TERR/; BOOST JEN/ AGC_INT/ CONV_START/
System_Clock
ALE/ CLKIN RTC_CS/ RESET/
RESET PSD813F1
JEN/
RS232 PORT
Battery
PGA_Din0 PGA_Din1 PGA_Din2
PGA_CS/
ANTENNA
(Receiver)
Filter
Vout
Signal Envelope
TSTAT RST/ TERR/
PreAmp
Envelope Detector
JTAG Connector
HEADER
Size Date:
Document Number Tutorial After Integration Friday, July 1998 Sheet
ConvStart
ADC_OUT4 ADC_OUT5 ADC_OUT6 ADC_OUT7
JEN/
Audio Application
Figure
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Matching Functions PSD813F1
Table maps functional areas original design into PSD813F1. 80C31 running taviv (address valid instruction valid time) PSD813F1-15 (150ns part) selected meet 80C31 access time requirement. Table Discrete solution compared PSD813F1 Design Example with discrete components
128KB Flash 32KB EEPROM
Functional Area
Matching PSD813F1 Function
Memory
Same Same Same Automatically taken care internally DPLD, page register, register. DPLD (Decoding PLD) Port latched address mode (A7-A0)
Memory Paging/ Segmentation, Control PLD/Control/ Demux
SRAM Extra logic drive address lines, output enables, chip selects Flash EEPROM Decoder (EPM7064S) Address latch logic CPLD Various registers used hold data control information used external devices Latched data inputs outputs CPLD Combinatorial outputs CPLD Automatic switch battery backup
Output Micro-Cell each register
mode feature
same Built-in comparator automatically switches battery power when system voltage drops below battery voltage (Vstby) Utilizes standard JTAG non-standard extensions speed programming); JTAG port multiplexed with other I/O, memory logic within JTAG port.
Supervisory/ JTAG
Limited JTAG interface with multiplexing JTAG port available, JTAG memory available
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PSD8XX Functional Blocks
PSD8XX provides five system-level functional blocks, allows user define configure these blocks meet design specification. Interface Adapts address, data, control lines particular PSD. Choices include multiplexed non-multiplexed address/data particular control/handshake signals. PLDs (Decode memory registers, General logic) DPLD generates internal chip selects PSD8XX Flash memory, EEPROM, SRAM, Control registers Ports, Peripheral mode, MicroCells. CPLD implements general logical functions, such state machines, shift registers, counters, combinatorial logic. Both PLDs based Flash memory technology. Ports PSD8XX four ports: Ports These ports have several modes operation selected within PSDsoft during design entry firmware runtime. Modes that defined PSDsoft implemented with Non-Volatile Memory (NVM) configuration bits that cannot altered unless device reprogrammed. remaining available port operational modes determined writing control registers. Application Note more details. Memory PSD813F1 Kbytes Flash memory, Kbytes EEPROM, Kbytes battery backed SRAM. these memories operate concurrent fashion. That that while executing code from type memory, other memories written erased, read. These memory blocks placed system address space using PSDsoft development software. PSD8XX also offers some run-time features that used alter system memory fly, which good memory paging ISP.
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JTAG interface PSD813FX family includes JTAG channel In-System Programming. This function extension typical JTAG boundary-can function. implementation JTAG-ISC (In-System Configuration) specification that becoming industry standard. entire device configured programmed while soldered into end-product. completely blank before programming because JTAG interface needs assistance from MCU. enhanced standard four-wire IEEE 1149.1 JTAG interface making available additional handshake lines speed programming. JTAG interface additional handshake lines defined using PSDsoft. Also, some control over JTAG interface runtime.
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PSDsoft Development Tools
PSDsoft WSI's integrated system development software tool which runs Windows Windows environments. PSDsoft supports configuration functional blocks just described. Figure shows PSDsoft program flow configuring, defining, programming devices. PSDsoft consists following major modules: PSDabel Configuration Fitter Simulator Programmer Code Generator
utility featured PSDsoft V5.X. This utility automatically generates ANSI-C code functions that used with user's choice crosscompilers.
PSDabel
PSDabel Minc's ABEL (formerly DATA ABEL) engine core. PSDabel environment provides editor create/edit *.abl file which defines chip select logic, general purpose logic, configuration parameters. Template .abl files provided many combinations. *.abl file compiled synthesize logic create files passed PSDsoft fitting utility.
Configuration
This utility used specify interface type, special assignments, particular internal functions. output this module *.glc configuration file which also used PSDsoft Fitter.
Fitter
Fitter main functions: Fitter Address Translator. Fitter accepts input from PSDabel Configuration, synthesizes this user logic configuration, fits design silicon. Address Translator process allows user firmware from cross-compiler Intel SRecord format) into memory blocks within PSD. result, firmware merged with logic configuration definition PSD. output Address Translator *.obj file that downloaded programmer program device. This *.obj file also used program Flash using JTAG
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FlashLink cable. *.obj file includes chip configuration, fusemap, firmware.
Simulator
WSI's version SIMUCAD's SILOSIII simulation software provides functional chip level simulation devices. PSDsoft automatically creates files input simulator. These files convey particular design information simulator user convenience. result, user only create/edit stimulus file since signals nodes taken from *.abl file.
Programmer
Programmer interface MagicProIII®, PSDpro, PEP300, Flashlink programming devices. accepts *.obj file input, allows viewing editing *.obj file, programs device.
code Generation
This feature PSDsoft that automatically generates code functions headers controlling Flash devices. These functions headers ANSI-C compatible. generated files (*.c *.h) edited suit particular application, then compiled linked with rest code. Afterwards, linker output cross-compiler (usually Intel Motorola S-record format) merged with configuration device Address Translate utility PSDsoft. functions headers provided PSDsoft will cover operations such Flash memory program erase algorithms, EEPROM program algorithms, control definition, memory management, power management, others.
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Design Flow
This section describes design flow project; from entering design PSDabel programming device simulation. Figure (below) shows PSDsoft Design Flow utility, first window appear after PSDsoft been started. double clicking each box, associated process invoked. While this convenient method navigate through steps, this tutorial shows step through process using menus toolbars since experienced user more likely take this approach. Section takes step-by-step through tutorial design.
Figure
PSDsoft Design Flow
PSDsoft Program Flow
Here high level steps complete design. Create open project after entry into PSDsoft. creating project, specify project name, directory path, device family, part number, provide small description design desired.
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Select design template (project.abl file), modify this template your design. PSDabel edit, compile, optimize project.abl file. Perform ABEL simulation desired. You'll need necessary test vectors PSDabel file. successful PSDabel compile operation will generate optimized file (project.tt2) Fitter. Configure device using PSDsoft Configuration. This generates project.glc file Fitter. design using Fitter. Fitter inputs files from PSDabel PSDsoft Configuration generates file project.fob that passed Address Translator process. Fitter also generates fusemap files, project.afu project.pfu Simulator. After successful fit, possible skip step (simulation) desired since PSDsilosIII used before after firmware merged with configuration. Generate code desired. Edit this code suit your particular application compile link with your other application code. Your cross-compiler will output Intel Motorola S-record file containing firmware. Perform address translation. Address Translator combines firmware file project.fob file into project.obj file. This project.obj file includes firmware, fusemap, configuration bits. Verify design using Simulator. Chip level simulation based user's Verilog stimulus file (project.stl) fusemap files from Fitter. must create/edit project.stl file. Programmer download project.obj file MagicProIII®, PSDpro, FlashLink JTAG programmer program device. compatible third party programmer also used. Contact representative near list compatible programmers.
Tutorial Example
This section uses tutorial design example illustrate steps invoke software implement functions shown schematic Figure files required, which were generated tutorial design, found \PSDSOFT\TUTORIAL\TUTOR8XX directory.
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this point, wish start PSDsoft program, that follow along with tutorial example.
Managing Project
Each project have working directory where files generated PSDsoft reside. Once specify project name, PSDsoft passes working directory pertinent information other functional modules. following sections, windows displayed explain step-by-step operation PSDsoft. Start PSDsoft; main PSDsoft window displayed, file automatically opened. Note, exited PSDsoft without closing whatever project were working that project will automatically reopened, "Design Flow" window will also displayed, shown Figure
Pull down Project menu select Open Project. "Open Project" dialog appears.
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Click Browse button, which brings "Open" dialog box. \PSDSOFT\TUTORIAL\TUTOR8XX directory, select tutor8XX.ini file click Open button, which closes "Open" dialog box.
Click button, which closes "Open Project" dialog automatically opens tutor8XX.abl file, which listed Appendix
PSDabel File
detailed information PSDabel relates PSD8XX, please read comments file tutor8XX.abl Appendix Also, refer WSI's Application Note (PSD GPLD Primer-PSD6XX/7XX/8XX PSDsoft PSDabel-HDL Reference Manual. more information system memory this tutorial design, Appendix 5.2.1 Compiling Tutor Design compile tutor8XX.abl file, take following steps: Click Compile->Compile. click Compile button tool bar.
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PSDabel compiler generates error file (even errors present), writes file, both which opened their respective windows. compiler also generates output file, tutor8XX.tt2, which used PSDsoft fitting, optimized based reduction algorithm specified "Optimization Options" under Options menu. After compilation, display actual logic equations that will implemented PSD8XX pulling down VIEW menu select Compiled Equations; this opens tutor8XX.eq2 file.
select Simulation Results View menu, PSDabel will display simulation results based logic equations test vectors PSDabel file. Note: order simulation work properly, some equations need commented out. Check note ABEL file which lines comment out.
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want change simulation results displayed, select Options menu, which will bring "Options" dialog box. Select "Simulation Options" tab, choose desired format.
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PSDsoft Configuration
PSD8XX programmable interface able interface directly many microcontrollers. Other features functions configured well. Configuration utility allows specify these type items. This tutorial design based Intel 80C31 microcontroller, which 8-bit multiplexed with /RD, /WR, /PSEN control signals, active-high level address latch (ALE). perform configuration, take following steps: Pull down PSDsoft menu main PSDsoft window choose Configuration. dialog opens titled "The Global Configuration". Make sure "MCU Configuration" selected.
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global configuration shown above. Ensure 8-Bit selected under "Data Width", selected under "Address/Data Mode", High selected under "Address Latch/Strobe Setup", "Enable Chip-Select Input (/CSI)" checked, /WR, /RD, /PSEN selected under "Control Setting", Data Space selected under "Flash", Program Space checked under "EEPROM". This arrangement program data space allows boot from EEPROM program space download Flash memory data space needed. Afterwards, override this arrangement example, wanted move Flash memory program space. Click "Other Configuration" tab, ensure that Enable Standby Voltage Input (PC2) checked under "Standby Voltage", Edge selected under "Mode Loading Micro-Cell MCU", other boxes unchecked.
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Click "JTAG Configuration" ensure that none boxes checked because checking boxes would enable JTAG port operational 100% time. Since this tutorial multiplexing JTAG pins with other signal functions, desired that JTAG functions only operational when JEN/ signal active (see schematic Figure "User Code" left
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Click "Sector Protection" tab, ensure that none boxes checked. appropriate sector should only checked desired that selected sector write protected. These bits changed later through JTAG port device programmer.
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When finished with global configuration settings, click button, which saves configuration. PSD8XX interface configuration completed. ever wish view configuration file, first ensure Configuration Mode (see step this section). Next, pull down View menu select Configuration Report, then select File->Print.
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Fitter Fitting Address Translation
Fitter consists Fitter Address Translator. Fitter accepts input from PSDabel Configuration, synthesizes this user logic configuration, fits design PSD8XX silicon. Address Translator process allows user firmware from cross-compiler Intel S-Record format) into memory blocks within PSD. result, firmware merged with logic configuration definition PSD. output Address Translator tutor8XX.obj file. 5.4.1 Fitting Design input files Fitter tutor8XX.tt2PLA file generated PSDabel. tutor8XX.glcPSD8XX configuration file generated Configuration. five output files generated Fitter tutor8XX.fobPLD fusemap PSD8XX configuration file. tutor8XX.afuGenerated Simulator. tutor8XX.pfuGenerated Simulator. tutor8XX.feqFitter CPLD equation file. tutor8XX.frpFitter report file. Design Pull down PSDsoft menu PSDsoft window choose Fitter, click "Fitter" button tool bar.
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Click Options Menu, select "Fitter Options" specify four fitting options. tutorial, choose Keep Current under "Pin Assignment", ensure that "Enable Product Term Expansion" "Perform Register Synthesis" boxes checked, shown below.
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Table explains "Pin Assignment" options. Table Keep Current Assignment Fitter Options
Fitter should maintain assignments defined user. This default option Keep Previous re-fitting current project after modification: Fitter will maintain previous assignment intact. Maintain many current assignments possible. Ignore Fitter free make assignment ignores user's assignments. Click save Fitter options. Then, pull down Fitter menu choose Fitting, click "Fitter" button toolbar.
Fitter opens files viewing: file (PSDsoft.log) error file (tutor8XX.err). Check error file possible errors. there errors present (there shouldn't didn't modify tutor8XX.abl file), skip Step fitting successful, have view tutor8XX.eq2 file PSDabel which logic function causes fitting problem modify tutor8XX.abl file accordingly. view tutor8XX.eq2 file, Step under "Compiling Tutor Design". Recompile modified tutor8XX.abl file. Repeat Steps through until successful been found, re-enter Fitter program, proceed Step Examine Fitter Report File pulling down VIEW menu. report file shows results fitting process assignment PSD8XX. want certain fitting other than generated, return tutor8XX.abl file change desired signal assignments.
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5.4.2 Generating code PSDsoft will automatically generate code functions, headers controlling PSD8XX. This optional step; however, will save time implementing your low-level function drivers header files PSDsoft create these you. functions headers ANSI-C compatible. files that generated should edited suit particular application, then compiled linked with rest your application code using your cross-compiler linker. functions headers provided PSDsoft will cover operations such Flash memory program erase algorithms, EEPROM program algorithms, control definition, memory management, power management, others. Although code generation performed anytime after project opened, recommended that done after successful fitting session. Once successful achieved, functions configurations known code tailored accordingly you. This tutorial does provide source programming files implement tutorial function. tutorial meant illustrate flow device configuration, logic design, simulation, programming, system considerations. However, let's look would code generation utility your project.
While "Fitter" environment, pull down Tools menu PSDsoft window choose Generate Code, shown below. (Alternately, click Code button Design Flow graphic.)
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should following screen:
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Code Generation dialog property sheets. first sheet, `Functions/Headers' following sections: Device InfoPSD family part number current project. These values cannot changed unless this project closed different opened. HeaderSpecify folder that would like place header files (*.h) generated PSDsoft clicking Browse. button. Typically, folder your cross-compiler environment chosen. cannot change name headers file(s) this point since these header files referenced name within other header files functions that also generated PSDsoft. Once headers functions copied their designated folders, edit
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header file names anyway wish, long change their names respective `#include' statements. FunctionsSpecify folder which would like place function file (*.c) clicking Browse. button. Typically, folder your crosscompiler environment chosen. This file will contain functions that specify next section. Code SelectionSelect categories code functions that would like integrate into your application program. Under `PSD Category' major functional groups that supported with code device that used this project. Under Code Coverage' brief list individual functions that available within each category. select more than category, hold `Ctrl' while clicking left mouse button make selections. Only file generated even more than category selected (functions appended within same file).
DescriptionThis field will offer description functions within selected category. After defining folders selecting functions, click this example, three files will written your folder(s). They are:
psd813F1.cANSI-C source selected functions psd813F1.hANSI-C header file define particular registers map813F1.hANSI-C header file define locations system memory elements (Flash, EEPROM, registers, etc.).
file psd813F1.h contains define statements each individual function within file PSD813F1.c. Later, edit psd813F1.h simply remove comment delimiters (//) from define statement function that would like compiled with rest your source code.
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Select next property sheet, "Coded Examples" clicking dialog box. should screen like this:
This sheet contains several examples that basis building your code application. These complete projects (main, functions, headers) targeted toward particular MCU. copy these files some folder browse them ideas paste sections from examples into your cross-compiler environment. There three sections: ExampleSpecify folder that would like place example project files generated PSDsoft clicking Browse. button selecting folder.
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Example SelectionThere several areas which generate code. Each category implements high level system function such memory paging, UART downloads Flash memory, etc. DescriptionThe description window contains information about currently selected category.
Once code generated PSDsoft integrated into your application successfully compiled linked your cross-compiler, ready address translation. 5.4.3 Performing Address Translation Address Translator combines tutor8XX.fob file with firmware file(s) generated your choice cross-compilers. Address Translator will generate tutor8XX.obj file that downloaded programmer compatible with PSD8XX.
NOTE: addresses within generated tutor8XX.obj file special "direct" addresses that meaningful programming device. They "system" addresses that would that DPLD decodes. This what meant `Address Translate'. translation "system" addresses that compiler/linker know about "direct" addresses that device programmer knows about.
Pull down Fitter menu choose Address Translate. Translation" dialog appears.
"Address
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NOTE: will notice warning message from PSDsoft upon entering Address Translate window. This warning reminder ensure that take paging into account when entering start/stop addresses file names.
Address Translation dialog following sections: Memory Select NameName memory segment that will selected when associated equation true. Memory Select EquationsEach cell shows equation appropriate memory segment. These optimized equations from PSDabel. They displayed convenience cannot modified this window. File Address StartStarting system address from compiler/linker that will mapped memory segment. File Address StopEnding system address from compiler/linker that will mapped memory segment. File NameMCU firmware file that generated your Compiler/linker linker. Record TypeThe supported formats Intel Motorola S-Record. Mapping ModeTwo modes mapping supported, direct relative. more information, consult PSDsoft User Manual.
Notice that PSDsoft will attempt fill File Start File Stop Addresses based your PSDabel equations. However, paging used this tutorial), these file addresses must handled carefully since PSDsoft does know your cross-compiler linker handles paging. progress, this process should become clear. Type file names your linker output appropriate places. this example, five files used. (See Appendix information system memory these files relate). Four five files programmed into Flash memory different pages. remaining file programmed into boot area EEPROM. four Flash files page_0.hex, page_1.hex, page_2.hex, common.hex. file EEPROM boot.hex. Each these files contain Kbytes code. Enter File Start File Stop Addresses.
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Table shows what data should entered Address Translate Menu this design: Memory Select EES0 EES1 EES2 EES3 File Start Address 0000 4000 8000 C000 8000 C000 8000 C000 0000 2000 File Stop Address 3FFF 7FFF BFFF FFFF BFFF FFFF BFFF FFFF 1FFF 3FFF File Name common.hex common.hex page_0.hex page_0.hex page_1.hex page_1.hex page_2.hex page_2.hex boot.hex boot.hex
Table Address Translation Values this design, different file name used each several sections code Flash memory because they overlapped same address space (i.e. 0x8000 0xFFFF). This file scheme used because even though these sections code physically reside different memory pages, some linkers will place them overlapping absolute address space. method depends your linker. Alternatively, single file name across many memory chip selects your linker automatically appends extra address bits that represent your paging scheme. would then, example, enter 18bit addresses accompany single file name into Address Translate utility instead 16-bit addresses accompany several file names.
NOTE: Optionally, specify only EEPROM contents programmed device programmer. desired load system code into Flash memory while in-system, device programmer. this case, only information EES0 EES1 should entered Address Translate utility.
Ensure that Direct Mapping selected "Mapping Mode" this tutorial design. Select Intel Record "Record Type" box. Click perform address translation. errors indicated, then tutor8XX.obj will placed your project directory.
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your copy PSDsoft includes PSDsilosIII simulator, should simulate verify your design before programming PSD8XX. Refer next section simulate tutorial design.
PSD8XX Chip Simulation
PSDsilosIII simulator software, WSI's version SIMUCAD's SILOSIII, provides chip level simulation design verification using Verilog Hardware Description Language (Verilog-HDL). Appendix lists stimulus file (tutor8xx.stl) this tutorial. Many internal nodes PSD8XX available tracing. Descriptions signals that traced simulator listed Appendix PSDsoft generates input files required simulator. file that must created stimulus file (.stl). stimulus file, same names used PSDabel file, predefined ones Appendix 5.5.1 PSDsoft.run File files generated PSDsoft simulation process PSDsoft.run, listed Figure below. command batch file used PSDsilosIII. additional information PSDsilosIII commands (commands starting with refer PSDsilosIII on-line help. Figure PSDsoft.run File
!Reset !file .sav Tutor8xx !control .ext `timescale 1ns/0.1ns !lib d:\psdsoft\psd8.v `include "tutor8xx.top" `include "tutor8xx.stl" endmodule
Let's analyze PSDsoft.run file. "`timescale 1ns/0.1ns" compiler directive defining delay values module; unit measurement times delays, precision which delays rounded off. `include also compiler directive that allows entire contents Verilog source file included another file (PSDsoft.run this case). Tutor8xx.top generated PSDsoft based PSDabel file, allows signal names within PSDabel file. There also parameter definitions high impedance state signals through Z32) .top file. Notice "endmodule" statement last statement PSDsoft.run file. there because complements "module WSIdesign" statement .top file. There important thing note about included library files: these files look other files automatically generated PSDsoft from fusemap file,
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have *.?fu extension. They allow simulation logic (defined .abl file) stimulus file. 5.5.2 Running Logic Simulator Review stimulus file (tutor8xx.stl) listed Appendix Pull down PSDsoft menu main PSDsoft window select Simulator, click appropriate button tool bar. tutor8xx.stl file automatically opened PSDsoft, shown.
Click LogicSim invoke SilosIII simulator. following events happen automatically result clicking LogicSim button: PSDsilosIII simulator automatically starts simulator automatically loads project tutor8xx.spj, PSDsoft.run, window displaying tutor8xx.stl file.
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Click button, which automatically opens "Output" window viewing results simulation:
5.5.3 Running Analyzer that logic simulation complete, results displayed with PSDsilosIII Data Analyzer performing following steps: Pull down Window menu select Data Analyzer, press click appropriate button tool bar.
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SilosIII Data Analyzer window appears with simulation results displayed screen. Note: Your screen will look different. tutorial Data Analyzer Explorer under Help->Contents rearrange group signals.
5.5.4 Working With Explorer Explorer SilosIII used conjunction with Data Analyzer trace signals. open explorer, ensure that have simulated design following steps "Running Logic Simulator" section (5.5.2). Next click Window->Explorer menu selection Explorer button), explorer window will appear. Explorer shows viewable signals.
more information Explorer Data Analyzer, on-line help, PSDsilosIII User Manual.
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Programming PSD8XX
Programmer programming interface MagicPro III® programmer. enables downloading .obj file, displays Flash EEPROM locations, fusemap, configuration bits (ACR). also perform following operations from Functions menu: Blank Testcheck device blank. Uploadupload contents device that were programmed buffer. Programprogram device with .obj file. Verifyverify programmed device against .obj file buffer. Erasecompletely erase device.
have MagicProIII, PSDpro, FlashLink device programmer connected your take following steps program PSD8XX after design been compiled .obj file been generated: Pull down PSDsoft menu main PSDsoft window choose Programmer, click appropriate button tool bar. tutor8XX.obj file downloaded displayed screen automatically.
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Let's right program device. Assuming have MagicProIII programmer connected, following: Pull down Functions menu select Program click Program button tool that's available when Programmer invoked. "PSD Programmer Program Confirmation" dialog appears, which enables user program Flash, EEPROM PLD/ACR (PSD Configuration) regions device.
Select `All' shown above. Leave address range Click button. programming takes place, MagicProIII programmer checks each location after programmed make sure matches .obj file contents. particular location cannot programmed properly, error message will appear. this occurs, must start over program fully erased functional part.
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6.1.1 PSDpro have PSDpro installed your parallel ports, select configure going Options menu Programmer environment select Hardware Setup. Once "PSD Programmer Hardware Setup" dialog appears, under "Hardware Section:", select PSDpro shown below:
Next, will that Auto Select option becomes active. This means that PSDsoft will automatically detect which parallel port your PSDpro connected Just click PSDpro will detected configured connections good. same menu options capabilities that apply MagicProIII section above also apply PSDpro. 6.1.2 JTAG FlashLink have FlashLink cable installed your parallel ports, select configure follows: Options menu Programmer environment select Hardware Setup. Once "PSD Programmer Hardware Setup" dialog appears, under "Hardware Section:", select FlashLink shown below:
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Next, will that Auto Select option becomes active well Loop Test.
Auto Select means that PSDsoft will automatically detect which parallel port your FlashLink cable connected Just click FlashLink cable will detected. Optionally, return Hardware Setup menu Loop Test FlashLink cable. This hardware integrity test that requires loopback cable (provided) installed FlashLink cable (see FlashLink installation manual). Make sure that have connected FlashLink cable your target system. target system needs powered since FlashLink cable gets power from target.
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Under Programmer menu, select JTAG->JTAG Chain Setup. This opens "JTAG Chain Setup" dialog box.
this writing, JTAG Chain Setup been finalized. However, following top-level steps taken.
JTAG chain must defined. Both PSDs devices from other vendors (non-PSD devices) exist this chain. However, non-PSD devices will placed bypass mode while PSDs communicating JTAG channel. result, chain constructed which defines each part type, length instruction register, desired operation. PSDs execute operations shown Property highlighted JTAG Chain Setup screen above.
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*.obj filename programmed verified each member chain must defined. This does apply non-PSD devices since they only bypass mode. file name this entire chain setup should specified this setup used later needed. Once chain setup, operations defined, files specified, then selected execute operations through JTAG FlashLink interface onto target circuitry. Additionally, Serial Vector Format file, filename.svf, created party JTAG programming support.
This tutorial document will updated with latest JTAG FlashLink information becomes available. Please refer document titled JTAG Information PSD8XXF (Application Note information these areas: JTAG Spec Compliance Programming Support Program/Erase Flow Control SVF/BSDL file information Enhanced functions Multiplexed JTAG functions Dedicated JTAG functions JTAG connector JTAG Chaining
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PSD8XX
PSD8XX programmed In-system with without participation MCU. with MCU, Appendix UART download information considerations. without participation, section 5.6.3 FlashLink JTAG programming within PSDsoft environment Application Note JTAG Information PSD8XXF.
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Appendix AABEL Design FileTutor8xx.abl
module Tutor8XX title '8XX Tutorial Design File'; Designed Harris Mark Rootz Design date: 6-16-98 Description: This shows logic implementation sample design Tutorial. design highlights following functionality PSD8XX: Effective efficient Input Output Micro<>Cells pins while underlying Micro<->Cell being used other functionality. WSIPSD PROPERTY statement output demultiplexed address bits, define Input Micro<->Cells/Output Micro<->Cells. Multiplexing JTAG pins with other I/O. logically interface 80C31 MCU, RTC, circuit. Convention: used throughout file indicate active signals. Note that used with reserved signal names below. "************************** Interface signal declarations ************************** reserved signal names automatically assigned appropriate following inputs from pin; "CNTL0 Input:(pin 47)- write strobe pin; "CNTL1 Input:(pin 50)- read strobe psen pin; "CNTL2 Input:(pin 49)- program store enable pin; "PD0 Input:(pin 10)- address latch enable reset pin; "Input:(pin 48)- system reset a15.a0 pin; "Input:(pins 46.39,37.30)- demuxed address "************************** ************************** Port declaration
Port Control outputs mode outputs Control0.Control2 "Some generic control signals Assign latched/demultiplexed address Port pins pa0. WSIPSD PROPERTY 'Address_Out Aout[4:0]:Addr_Out[4:0]'; Port PGA_Din2.PGA_Din0
"Data bits used program "Implemented with mode Measured_Level3.Measured_Level0 istype 'reg'; "Upper bits converter (ADC) WSIPSD PROPERTY 'DataBus_IMC D[7:4]:Measured_Level[3:0] PortB'; Port Note that pins pc0, pc1, pc5-6 multiplexed output/JTAG signals. pc3, pc4, JTAG signals that multiplexed. Ensure that under "Global Configuration" with "JTAG Configuration" selected that none
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boxes enabling various JTAG signals certain pins checked because device will expect only valid JTAG signals these pins, multiplexing done under these circumstances. (pin used VSTBY (set global configuration) Intrn "Interrupt when gain needs changed/JTAG Start_Conv "Start Conversion signal ADC/JTAG Trim "The gain high needs decremented/JTAG TSTAT Boost "There enough gain-increment it/JTAG TERRn JCEn "JTAG chip enable signal used demultiplex Port output JTAG Port (pin assigned above signal from microcontroller. external chip selects that generated decoding address should placed Port when possible save many resources possible. RTCcsn "Real Time Clock (RTC) chip select/JTAG clkin pin; "Port (pin System clock Output Micro<->Cell assignments WSIPSD PROPERTY 'DataBus_OMC D[7:4]:Desired_Level[3:0] MCELLAB'; "************************** ************************** Internal node declarations
mxord3 node; "This signal needed save product terms meqd node; "True when measured signal equals desired signal level begin node istype 'reg'; "This signal takes state machine idle STATE1.STATE0 node istype 'reg'; "State machine bits Desired_Level3.Desired_Level0 node istype 'reg'; "The desired gain level fs7.fs0 node; "Main Flash memory segments ees3.ees0 node; "EEPROM memory segments Reserved node names node; "Select SRAM memory space csiop node; "Control register jtagsel node 102; "This JTAG enable product term. used enable "the JTAG port signals. pgr1.pgr0 node; "Internal Page Register bits following page register definitions example manipulate memory facilitate ISP. This scheme explained Appendix Application note swap node 117; This page register (pgr7) will used swapping memory segments after firmware download from 8031 UART port completed. When swap secondary occupies boot area ISP, swap primary occupies boot area.
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enable_data_half node active.
116; This page register (pgr6) will used manipulate EEPROM. this divide EEPROM into equal sections, boot general data. When this bit=0, boot section
When this data section active. DEFINITIONS
"************************** **************************
DLEVEL "Desired gain level MLEVEL "Measured gain level latched IMCs STATE_MACHINE [STATE1.STATE0]; .x.; "Don't care symbol .c.; "Clock symbol page [pgr1,pgr0]; address [a15.a0]; "De-muxed microcontroller address signals EQUATIONS "************************** ************************** DPLD equations Each
Generate active high chip selects main Flash segments. segment bytes PSD813FX devices. ((address ^h8000) (address ^hBFFF) (page !swap) ((address ^h0000) (address ^h3FFF) (page swap); (address ^h4000) (address ^h7FFF) (page (address ^h8000) (address ^hBFFF) (page (address ^hC000) (address ^hFFFF) (page (address ^h8000) (address ^hBFFF) (page (address ^hC000) (address ^hFFFF) (page (address ^h8000) (address ^hBFFF) (page (address ^hC000) (address ^hFFFF) (page
Generate active high chip selects EEPROM segments. Each segment bytes PSD813F1 devices. ees0 ((address ^h0000) (address ^h1FFF) (page !swap) ((address ^h8000) (address ^h9FFF) (page swap !enable_data_half); ees1 ((address ^h2000) (address ^h3FFF) (page !swap) ((address ^hA000) (address ^hBFFF) (page swap !enable_data_half); ees2 (address ^hC000) (address ^hDFFF) (page swap enable_data_half; ees3 (address ^hE000) (address ^hFFFF) (page swap enable_data_half; //Generate active high chip select SRAM bytes). (address ^h0100) (address ^h08FF) (page
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Generate active high chip select control registers. contiguous bytes must decoded PSD8XX devices. csiop (address ^h0900) (address ^h09FF) (page Enable JTAG port when JTAG Chip Enable (JCEn) Signal active jtagsel !JCEn; "************************** ************************** GPLD/ECSPLD
equations
IMPORTANT NOTE: Comment these next four equations ABEL simulation only. PSDsilosIII Simulator requires equations (and they functionally correct). problem that presets (loads) clears these registers, value registered through input. However, ABEL simulator does reconize "dot" extentions these would normally through equations). basic functionality still properly tested, actually implemented hardware slightly different. intend ABEL Simulator, comment following four lines that test vectors file will work properly. DLEVEL.ck DLEVEL begin.ck begin mxord3 Measured_Level3 !Desired_Level3; Trim gain when Measured signal level greater than desired signal level. Trim MLEVEL DLEVEL Trim (Measured_Level3 !Desired_Level3) ((Measured_Level2 !Desired_Level2) mxord3) ((Measured_Level1 !Desired_Level1) mxord3 (Measured_Level2 !Desired_Level2)) ((Measured_Level0 !Desired_Level0) mxord3 (Measured_Level2 !Desired_Level2) (Measured_Level1 !Desired_Level1)); Boost gain when Measured signal level less than desired one. meqd (MLEVEL DLEVEL); Boost !meqd !Trim; Generate chip select !RTCcsn ((address ^h0a00) (address ^h0aff)); Loading various registers MLEVEL.ld !clkin;
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State machine which controls conversion start ADC, interrupt MCU, strobing IMCs STATE_MACHINE.ck clkin; STATE_MACHINE.re !reset; state_diagram STATE_MACHINE; state Start_Conv Intrn (begin then else state Start_Conv goto state Start_Conv goto state !Intrn Trim Boost; "Interrupt when Measured equal Desired goto Test_Vectors Test state machine, trim, boost ([clkin, reset, begin, MLEVEL, DLEVEL] [Start_Conv, Intrn, STATE1, STATE0, Trim, ^h3, ^h4, ^h5, ^h5, ^h5, ^h4, ^h4,
signals Boost]) "system reset "system reset
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Appendix BStimulus FileTUTOR8XX.STL
.stl file consists four sections: Define Parameters: each PSD8XX control registers address (offset from CSIOP base address). parameters make stimulus file easier read. User-defined tasks: used define implement microcontroller cycles. each task, timing control signals address/data should follow that microcontroller, don't have exact, just scale. Simulator will simulate cycle every time read, write, psen task called. Signal Initialization: must specify initial logic level input signals before simulation. Note: output signals that want simulate should initialized high impedance state. Generate stimulus inputs: here stimulus inputs needed perform read/write cycles access Flash, EEPROM, SRAM ports. Inputs also generated exercise CPLD functions.
//Title: tutor8XX.stl //Function: Simulation file PSD8XX Tutorial //Designed Harris //Design Date: 6-23-98 //Description: This file intended used PSDsilosIII environment stimulus file PSD8XX Tutorial. idea this file show Verilog-HDL language works, rather format .stl file, applies this tutorial example. main parts this file are: Parameter declarations which make file more readable Read, write "PSEN/" cycle tasks 80C31 area where user wish file order test more functions actual stimulus design +++++++++++++++++++++ Parameters declarations address offsets CSIOP address space
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+++++++++++++++++++++ //Port parameter parameter parameter parameter //Port parameter parameter parameter parameter Port_A_Dir_Reg 'h0906, Port_A_Dout_Reg 'h0904, Port_A_IMC 'h090A, Port_A_En_Out 'h090C; Port_B_Dir_Reg 'h0907, Port_B_Dout_Reg 'h0905, Port_B_IMC 'h090B, Port_B_En_Out 'h090D; Port_A_Cntl_Reg ='h0902; Port_A_Din_Reg ='h0900; Port_A_Drive_Sel 'h0908;
Port_B_Cntl_Reg ='h0903; Port_B_Din_Reg ='h0901; Port_B_Drive_Sel 'h0909;
//Port parameter Port_C_Dir_Reg 'h0914, parameter Port_C_Dout_Reg 'h0912, parameter Port_C_IMC 'h0918, //Port parameter Port_D_Dir_Reg 'h0915, parameter Port_D_Dout_Reg 'h0913, parameter Port_D_En_Out 'h091B; //Port OMCs parameter Port_AB_OMC 'h0920, //Port OMCs parameter Port_BC_OMC 'h0921, //Other control registers parameter FLASH_Protect 'h09C0, parameter PMMR0_Reg 'h09B0, parameter PMMR2_Reg 'h09B4, parameter Page_Reg 'h09E0,
Port_C_En_Out ='h091A; Port_C_Din_Reg ='h0910; Port_C_Drive_Sel 'h0916; Port_D_Drive_Sel ='h0917; Port_D_Din_Reg ='h0911;
Port_AB_OMC_Mask 'h0922; Port_BC_OMC_Mask 'h0923; EEPROM_Protect 'h09C2; PMMR1_Reg ='h09B2; JTAG_En 'h09C4; VM_Reg ='h09E2;
+++++++++++++++++++++ Defining tasks simulate 80C31 cycles (read, write psen cycles). Note that cycles shortened simulation purposes, functionality remains same. +++++++++++++++++++++ //The "write task" implements 80C31 write cycle task write; input [15:0] addr_bus;
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input [7:0] data_in; begin 1;//Latch address lines adio addr_bus; //Read valid address defined .top file) 0;//Ale inactive adio[7:0] data_in; //Write operation 0;//Write pulse #100 1;//Write ends adio[7:0] //Z16 defined .top file endtask //The "read task" implements task read; input [15:0] addr_bus; begin .top) #100 1;//Latch address lines adio addr_bus; //Read valid address 0;//Ale inactive adio[7:0] //Float address 0;//Read pulse 1;//Read ends 80C31 read cycle timing
(adio
defined
endtask //The "psen task" implements 80C31 psen program fetch cycle task psen; input [15:0] addr_bus; begin #100 1;//Latch address lines adio addr_bus; //Set-up right address //Ale inactive adio[7:0] //Float address psen 0;//Read pulse psen 1;//Read ends
endtask +++++++++++++++++++++
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Define some busses here make program easier read. +++++++++++++++++++++ //adrout latched address output Port [4:0] adrout; Addr_Out4, Addr_Out3,Addr_Out2, Addr_Out1, Addr_Out0; assign {Addr_Out4, Addr_Out3, Addr_Out2, Addr_Out1, Addr_Out0} adrout; [3:0] measured_value; Measured_Level3, Measured_Level0; assign {Measured_Level3, Measured_Level0} measured_value; [3:0] desired_value; Desired_Level3, Desired_Level0; assign {Desired_Level3, Desired_Level0} desired_value; Measured_Level2, Measured_Level2, Measured_Level1, Measured_Level1,
Desired_Level2, Desired_Level2,
Desired_Level1, Desired_Level1,
[3:0] PGA_data; PGA_Din3, PGA_Din2, PGA_Din1, PGA_Din0; assign {PGA_Din3, PGA_Din2, PGA_Din1, PGA_Din0} PGA_data; [2:0] cntrl; Control2, Control1, Control0; assign {Control2, Control1, Control0} cntrl; +++++++++++++++++++++ Stimulus starting point Initialize first. Then proceed with rest simulation. +++++++++++++++++++++ initial begin //Initialize signals first reset adio ='h0000; psen adrout measured_value 'h0;
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desired_value 'h0; PGA_data cntrl Intrn Start_Conv Trim Boost JCEn #100 reset Take reset after 100ns //We ready some configuration //Port configuration //Configure Port pins output latched address, rest //of port will output control information mode. //Writing "1F" Port control register enables latched address output //pins pa0, rest port output I/O. psen(Port_A_Cntl_Reg); //Writing "FF" Port direction register sets Port pins outputs. write(Port_A_Dir_Reg,'hff); //Port configuration //Since there latched address output Port control register //defaults mode output, only direction register needs setup. //Only pins will outputting data, rest will receiving //input write(Port_B_Dir_Reg,'h0f); //All Port output (with exception Vstby input write(Port_C_Dir_Reg,'hfb); //There only output direction register //setup follows: write(Port_D_Dir_Reg,'h04); Port (RTCcs/),
//Set mask registers that only desired portion OMCs //written. Only desired value (MCELLAB[7:4]), begin (MCELLBC7) //written write(Port_AB_OMC_Mask, 'h0f);
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write(Port_BC_OMC_Mask, 'hdf); //The next four cycles write/read cycles verify latched //addresses show Port write('h0A00,'h5a); write('h0A20,'h69); read ('h0A00); read ('h0A20); Wait, then initialize gain output data pins pb0. write(Port_B_Dout_Reg,'h01); Assume small value output since gain measured_value 'h3; Load into desired value register write(Port_AB_OMC, 'h50); Take state machine idle state generate chip select. write(Port_BC_OMC, 'h20);
Since measured value less than desired one, gain would boosted after interrupt generated cycles after start state machine). should increment gain that time. #400 write(Port_B_Dout_Reg, 'h02); $finish; initial begin
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Generate system clock used state machine, etc. Note time scale psdsoft.run file. clkin forever #100 clkin ~clkin; //stimulus ends here
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Appendix CList PSD8XX Simulation Signals
This list signals from Explorer that viewed using Data Analyzer. This list based Tutor8XX.abl file, predefined signals. list will vary depending names your .abl file, most signals will same.
above signals dragged Data Analyzer window viewing. Once there, signals made into busses. more information Explorer Data Analyzer, PSDsilosIII's on-line help, PSDsilosIII User Manual. Below table that contains viewable predefined signal names, brief description. conventions used table are: represents number represents letter list above determine which letters and/or numbers apply respective signal.
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Table C1Predefined Signal Names their Descriptions Signal/Bus Name adioh[15:8] adiol[7:0] ctrl_x data[7:0] din_x dirff_x dout_x drive_x ecsdn ee_boot_oe ee_power_down ee_protection[3:0] ee_ready_busy_N ee_sdp_disable ee_sdp_enable ee_toggle eesel_f enable_x f_protection[7:0] flash_oe flash_polling flash_ready_busy flash_toggle flsel_f jtag mask_mcab mask_mcbc mcellabn mcellabn_clk mcellabn_pr mcellabn_reg mcellabn_re mcellbcn mcellbcn_clk mcellbcn_pr mcellbcn_reg mcellbcn_re nib_xn Description register Address/Data high byte Address/Data byte Port control register Non-multiplexed 8-bit data Port data register Port direction register Port data register Port drive register External chip select output EEPROM output enable EEPROM power down signal security EEPROM sector protection EEPROM ready/busy signal EEPROM software data protection disable EEPROM software data protection enable EEPROM toggle signal EEPROM final chip select Enable port driver Flash sector protection register (read only) Flash output enable Flash data polling Flash ready/busy signal Flash toggle Flash final chip select JTAG enable register Mask register outputs Mask register outputs Micro-Cell output Output Micro-Cell clock input Output Micro-Cell preset input Output Micro-Cell register input Output Micro-Cell reset input Output Micro-Cell output Output Micro-Cell clock input Output Micro-Cell preset input Output Micro-Cell register input Output Micro-Cell reset input Product term control port x[7:4] x[3:0] input Micro-Cell
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out_mcab[7:0] out_mcbc[7:0] pxn_imc pxn_oe pgr7_0 pmmrn pseln rd_bsy sram_oe
Output registers Micro-Cell Output registers Micro-Cell Port Port Input Micro-Cell Port output enable product term Power down signal Page register outputs Power management mode register Port peripheral select internal ready/busy status signal SRAM output enable signal
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Appendix DDesign file EPM7064S Figure
-Title: Function: Designed Design date: Description: Tutorial-Discrete Solution Replacement programmable logic portions PSD8XX Harris 6/15/98 This design shows what chip logic would required replace programmable logic portions PSD813F1. This chip will responsible following tasks: Latching address generated 80C31 MCU. Decoding address generating internal/external chip selects. Storing control/status information internal registers. address translation memory paging. Interfacing controlling Analog Front End, PGA, comparator, RTC, SRAM, EEPROM, FLASH, MCU. Interfacing JTAG-compatible port ISP. tilde used throughout this design indicate active signals.
H"09E0"; H"09E2"; H"0902"; H"0920"; H"0901"; H"0921";
Convention:
CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT CONSTANT
PAGE_REG_ADDR VM_REG_ADDR MCU_IO_OUT_ADDR DESIRED_REG_ADDR GAIN_REG_ADDR START_SIG_ADDR
subdesign 8XXtutor following signals generated (U1): A/D[7.0] BIDIR; Multiplexed address (lower byte)/data A[15.8] INPUT; Upper byte addr[] INPUT; Read strobe INPUT; Write strobe INPUT; addr[] latch enable signal PSEN~ INPUT; Program store enable following signal generated (U1): AGC_Interrupt~ OUTPUT; Interrupt when desired measured signals don't match chip select output (U13): RTC_CS~ OUTPUT; to/from Trim Boost ADC_Out[3.0] 4-bit comparator (U12) OUTPUT; True when measured level greater than desired OUTPUT; Opposite Trim INPUT; measured signal strength
These signals used control (U11): Start_Conversn OUTPUT; Indicates when should start analog-to-digital conversion ADC_CS~ OUTPUT; Chip select following signals used control (U9) PGA_Din[2.0] OUTPUT; data used appropriate gain level PGA_CS~ OUTPUT; chip select System-level inputs: Reset~ INPUT; Clock INPUT;
System reset System clock
following outputs external memories: Chip selects FLASH_CS~ OUTPUT; EEPROM_CS~ OUTPUT; SRAM_CS~ OUTPUT; Output enables FLASH_OE~ OUTPUT; EEPROM_OE~ OUTPUT; SRAM_OE~ OUTPUT; Upper address bits FLASH_A[16.14] OUTPUT; addr[] bits 128K Flash segmentation EEPROM_A[14.13] OUTPUT; addr[] bits EEPROM segmentation Latched/demultiplexed address output Addr_Out[7.0] OUTPUT; outputs external memories Control Output mode
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Control[2.0] VARIABLE
OUTPUT;
A/D[7.0] la[7.0] page_reg[7.0] vm_reg[7.0] desired_reg[3.0] gain_reg[2.0] begin_comparrison cntrl_port_reg[2.0] addr[15.0] fs[7.0] ees[3.0] swap enable_data_half measured[3.0] desired[3.0] meqd BEGIN
TRI; Needed drive data output onto data LATCH; Must demux lower byte addr[] DFFE; Page register DFFE; Used memory mapping combined memory space mode DFFE; Register store desired signal level (set MCU) DFFE; Register store gain level (set MCU) DFFE; takes state machine idle state (s0) DFFE; mode control register NODE; Demultiplexed addr[] NODE; Flash segment enable signals NODE; EEPROM segment enable signals NODE; page register NODE; page register NODE; Output from NODE; Input from NODE; True when measured value equals desired MACHINE WITH STATES (s0, s3);
Right now, there nothing output lines A/D[] GND; Latch addr[] la[] A/D[]; la[].ena ALE; addr[7.0] la[]; addr[15.8] A[]; Addr_Out[] la[]; begin_comparrison A/D0; begin_comparrison.clk Clock; begin_comparrison.clrn Reset~; begin_comparrison.ena !WR~ (addr[] START_SIG_ADDR); desired_reg[] A/D[3.0]; desired_reg[].clk Clock; desired_reg[].clrn Reset~; desired_reg[].ena !WR~ (addr[] DESIRED_REG_ADDR); gain_reg[] A/D[2.0]; gain_reg[].clk Clock; gain_reg[].clrn Reset~; gain_reg[].ena !WR~ (addr[] GAIN_REG_ADDR); cntrl_port_reg[] A/D[2.0]; cntrl_port_reg[].clk Clock; cntrl_port_reg[].clrn Reset~; cntrl_port_reg[].ena !WR~ (addr[] MCU_IO_OUT_ADDR); page_reg[] A/D[]; page_reg[].clk Clock; page_reg[].clrn Reset~; page_reg[].ena !WR~ (addr[] PAGE_REG_ADDR); vm_reg[] A/D[]; vm_reg[].clk Clock; vm_reg[].clrn Reset~; vm_reg[].ena !WR~ (addr[] VM_REG_ADDR); measured[] ADC_Out[]; desired[] desired_reg[]; PGA_Din[] gain_reg[]; Control[] cntrl_port_reg[]; Memory Section swap page_reg7; enable_data_half page_reg6; ((addr[] H"8000") (addr[] H"BFFF") (page_reg[] !swap) ((addr[] H"0000") (addr[] H"3FFF") swap); (addr[] H"4000") (addr[] H"7FFF"); (addr[] H"8000") (addr[] H"BFFF") (page_reg[] (addr[] H"C000") (addr[] H"FFFF") (page_reg[]
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(addr[] (addr[] (addr[] (addr[]
H"8000") H"C000") H"8000") H"C000")
(addr[] (addr[] (addr[] (addr[]
H"BFFF") H"FFFF") H"BFFF") H"FFFF")
(page_reg[] (page_reg[] (page_reg[] (page_reg[]
ees0 ((addr[] H"0000") (addr[] H"1FFF") !swap) ((addr[] H"8000") (addr[] H"9FFF") swap !enable_data_half); ees1 ((addr[] H"2000") (addr[] H"3FFF") !swap) ((addr[] H"A000") (addr[] H"BFFF") swap !enable_data_half); ees2 (addr[] H"C000") (addr[] H"DFFF") swap enable_data_half; ees3 (addr[] H"E000") (addr[] H"FFFF") swap enable_data_half; Flash upper EEPROM upper address encoding FLASH_A16 FLASH_A15 FLASH_A14 EEPROM_A14 ees3 EEPROM_A13 ees3 fs4; fs2; fs1; ees2; ees1;
Chip Selects Output Enables SRAM highest priority, followed EEPROM, then Flash !FLASH_CS~ (fs0 fs7) (EEPROM_CS~ SRAM_CS~); !EEPROM_CS~ (ees0 ees1 ees2 ees3) SRAM_CS~; !SRAM_CS~ ((addr[] H"0100") (addr[] H"08FF")); !ADC_CS~ begin_comparrison; !PGA_CS~ ((addr[] H"0B00") (addr[] H"0B07")); !RTC_CS~ ((addr[] H"0A00") (addr[] H"0A1F")); !SRAM_OE~ !(!RD~ (!PSEN~ vm_reg0)); !EEPROM_OE~ !((!PSEN~ vm_reg1) (vm_reg3 !RD~)); !FLASH_OE~ !((!PSEN~ vm_reg2) (vm_reg4 !RD~)); Comparator Trim (measured[] desired[]); meqd (measured[] desired[]); Boost !Trim !meqd;
State Machine sm.clk Clock; sm.reset !Reset~; CASE WHEN Start_Conversn GND; AGC_Interrupt~ VCC; (begin_comparrison) THEN ELSE WHEN Start_Conversn VCC; WHEN Start_Conversn GND; WHEN !AGC_Interrupt~ Trim Boost; Interrupt when Measured equal Desired CASE; END;
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Appendix EDiscrete Solution (Figure Compared Integrated Solution (Figure
This appendix compares circuits Figures following categories: (Only major were compared.) Cost Average Current Usage Board Space Usage Time market
Cost
PSD813F1 PLCC package purchased significantly lower price than total cost individual EEPROM, Flash, SRAM, CPLD devices.
Average Current Usage
PSD813F would typically 4.29 according "Example PSD813F Typical Power Calculation "AC/DC Parameters" section PSD813F Family Data Sheet. Now, take total average current devices discrete solution, 60.37 (with EPM7064S turbo mode). This shows that discrete solution uses 1,407% more current than PLD!
Board Space Usage
PSD813F1 PLCC package takes mm2. chips that make discrete solution take combined 1493 mm2. That equates 373% more board space! (All calculations based PLCC packages.) This calculation does reflect extra board space, complexity, noise with routing signals discrete solution.
Time Market
While specific quantities used calculation, should obvious that time market will reduced significantly following reasons: easiest visualize fact that discrete solution involves complex deal with instead just one. There templates predefined routines that, when used conjunction with user-friendly PSDsoft will help with every step your design process. Issues related concurrent memory, memory mapping, assisted simplified. Even code generated you. JTAG interface greatest benefits time savers. allows program, configure, test entire PSD, leave soldered board whole time! Last, least, there just fewer places wrong, fewer things debug when have this level integration.
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Appendix FSystem Memory UART
Introduction system memory developed this tutorial take full advantage memory available PSD813F1 expand beyond Kbyte address space limitation 8031 MCU. This memory facilitates downloading firmware from host computer Flash memory using 8031 UART. 8031 boots from EEPROM, concurrently downloads Flash memory, then 8031 execution jumps from EEPROM Flash memory. After this jump, EEPROM boot area address space replaced with Flash memory special registers within PSD. After that, entire Flash memory available 8031. This system memory also allows concurrent downloading boot code into EEPROM while executing code Flash memory. This possible non-PSD systems that PROM boot code. total memory available 8031 defined this system Kbytes Flash Kbytes EEPROM boot code Kbytes EEPROM data storage Kbytes SRAM (battery backed) addition bytes SRAM resident 8031
System Memory system memory shown Figures labels EESx names internal memory blocks within PSD813F1 device. blocks main Flash Kbytes each), EESx blocks EEPROM Kbytes each). this design, paging used because system contains more memory than 8031 address linearly. PSD813F1 facilitates paging using page register, which accessible 8031. Because paging used, area common memory needed firmware routines that must accessible regardless what page executing from. This common area resides lower half each memory page (Figures program space, should contain routines that handle initialization, interrupts, implement page switching, drive physical devices. also important keep critical data space items available times. example, this design, control registers, I/O, system SRAM stack global variables available memory page (Figures System I/O).
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There fundamental modes operation; boot/download mode, other normal operation. Figures show memory during transition from boot/download mode normal operation mode. Figure represents memory power-on (boot). system will boot from EEPROM, then facilitate download main Flash memory needed) using 8031 UART. this point, Flash memory 8031 "data" space EEPROM 8031 "program" space declaration made PSDsoft Configuration utility. After Flash been programmed and/or validated, Flash memory moved from 8031 data space 8031 program space when 8031 writes special register inside (while still executing EEPROM). Writing this register overrides power-on configuration data program space which PSDsoft. Figure represents memory after Flash been moved program space. This intermediate step that result writing register. system this state very short time until next step occurs. Next, 8031 execution jumps from EEPROM Flash. While executing from Flash, 8031 will page register that will call "SWAP". Now, EEPROM that booted from during power-up replaced with Flash memory that contains application vectors code, shown Figure transition between maps Figures under control 8031 setting "SWAP" inside PSD. Again, state memory shown Figure intermediate step until next final action occurs.
NOTE: Individual bits within 8-bit page register used things other than memory page definition. example, this tutorial, only eight page register bits define four memory pages, while page register bits used "SWAP" described above.
Finally, while executing from Flash memory, 8031 will write register move EEPROM from 8031 program space 8031 data space. This will finalize memory shown Figure Now, Kbytes Flash memory program space with Kbytes common area Kbytes spread across three memory pages. Also, EEPROM data space accessible from memory page. Notice that EEPROM segments (EES2 EES3) appear Figure These segments general data while other EEPROM segments (EES0 EES1) comprise 8031 power-on boot code. that system memory looks like that Figure another feature becomes available. Besides register SWAP bit, there more memory mapping control used this tutorial design. This bit, "ENABLE_DATA_HALF", another page register used protect boot code EES0 EES1 from inadvertent writes. same time, enables other half EEPROM (EES2 Inc. Fremont 800-832-6974 www.wsipsd.com
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EES3) accessed general data. example, update boot code EES0 EES1 with code downloaded over UART, 8031 would leave ENABLE_DATA_HALF logic zero, perform update writing EES0 EES1, then ENABLE_DATA_HALF logic one. boot code inaccessible (protected while booting) data half EEPROM accessible.
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PROGRAM SPACE (PSEN\)
PAGE FFFF PAGE PAGE
DATA SPACE (RD\)
PAGE PAGE FFFF
C000
NOTHING MAPPED
C000
NOTHING MAPPED
8000
8000
Execute from here
4000
4000
EES1
2000
NOTHING MAPPED NOTHING MAPPED NOTHING MAPPED NOTHING MAPPED
COMMON MEMORY ACROSS DATA PAGES
EES0
0000 SYSTEM SYSTEM SYSTEM SYSTEM
1000 0000
Figure System Memory 8031-PSD813F1, boot/download POWER-UP
PROGRAM SPACE
PAGE FFFF PAGE PAGE PAGE
DATA SPACE
PAGE FFFF
C000
NOTHING MAPPED
C000
8000
NOTHING MAPPED
8000
COMMON MEMORY ACROSS PROGRAM PAGES
Execute from here
4000
4000
EES1
2000
EES1
EES1
EES1
1000 SYSTEM 0000
EES0
0000
EES0
EES0
EES0
Figure System 8031-PSD813F1, move Flash program space WRITE REGISTER
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PROGRAM SPACE
PAGE FFFF PAGE PAGE PAGE
DATA SPACE
PAGE FFFF
C000
NOTHING MAPPED
C000
EES1 Execute from here
EES1
EES1
EES1
EES0
8000
EES0
EES0
EES0
NOTHING MAPPED
8000
COMMON MEMORY ACROSS PROGRAM PAGES
4000
4000
0000
1000 SYSTEM 0000
Figure System Memory 8031-PSD813F1, swap boot EEPROM with Flash segment SWAP
PROGRAM SPACE
PAGE FFFF PAGE PAGE PAGE
DATA SPACE
PAGE FFFF
EES3
C000
EES2
C000
NOTHING MAPPED
EES1
8000
EES0
8000
COMMON MEMORY ACROSS PROGRAM PAGES
4000
NOTHING MAPPED
4000
0000
1000
SYSTEM
0000
Figure Final 8031-PSD813F1, move EEPROM data space
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WRITE REGISTER Code partitioning Now, let's look partitioning code Flash memory pages. Ultimately, will executing from Flash memory since EEPROM only used boot-up this design. Let's assume that will have Kbytes program space Flash memory, shown Figure Kbytes code will reside four areas: Kbytes common area (FS0, accessible from page), Kbytes page zero (FS2, FS3), Kbytes page (FS4, FS5), Kbytes page (FS6, FS7). Keep mind that 8031 never leaves page zero while executing, access Kbytes Flash memory well SRAM I/O. However, 8031 execution jumps Flash memory pages from call upper half page zero (FS2 FS3), care must taken leave path return page zero again. However, call page from routine lower half page zero (common area, FS1), there problem returning from call. When placing code Flash memory upper half pages zero, one, two, software designer must break tasks into logical groups. These groups should need access code other pages frequently (most software split this manner result good modular design). Since system SRAM available page, firmware routines that reside different pages pass data using global variables stack. designer create page switching algorithms jump between tasks which different pages. There many ways implement method paging. method involves table addresses page numbers program tasks, which called from page page. This table these algorithms must reside portion Flash memory that resides common area. This provides very clean paging solution, which implemented using high level compilers (the compilers from Keil support this directly). only penalty when using this method overhead experienced when switching from page page. this tutorial design, five different files from cross-compiler linker will used program into memory sections PSD813F1. These dummy files with code them present illustrate merging firmware with configuration Address Translate operation design flow. this were real design, file common.hex would contain common functions interrupt vectors Flash memory, would programmed into FS0/FS1. Three more files from linker, page_0.hex, page_1.hex, page_2.hex would contain partitioned code described above. such, these three files would programmed into segments FS2/FS3, FS4/FS5, FS6/FS7 respectively. finally, file boot.hex, containing power-up boot code, would programmed into EES0/EES1.
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Start-up sequences, UART downloads Let's assume that desired laptop host download firmware this embedded system over RS-232 UART channel (instead JTAG). These download actions program main Flash memory very first time, update main Flash after been programmed once, update boot code after being programmed first time device programmer JTAG link. There valid boot scenarios that must handled system power (reset). default conditions power-up place main Flash memory data space EEPROM program space. Refer memory maps Figures
RS-232 cable attached, main Flash valid. Action 8031 boots from EES0/EES1, runs checksum Flash memory, checks UART pending host download request main Flash (Figure F1), sets register main Flash into program space (Figure F2), sets SWAP PSD, which swaps EES0/EES1 with (Figure F3), sets register EEPROM into data space (Figure F4). Now, system normal operating mode. Next, 8031 checks UART host download request boot memory, then sets ENABLE_DATA_HALF boot download request exists. Now, normal application code executed from main Flash memory. RS-232 cable attached, main Flash valid, download demands from host. Action same "a." above. RS-232 cable attached, main Flash valid, main Flash demanded host. Action 8031 boots from EES0/EES1, runs checksum Flash memory, checks UART pending host download request main Flash (Figure programs main Flash memory with data from UART, sets register main Flash into program space (Figure F2), sets SWAP which swaps EES0/EES1 with (Figure F3), sets register EEPROM into data space (Figure F4). Now, system normal operating mode. Next, 8031checks UART host download request boot memory, then sets ENABLE_DATA_HALF boot download request exists. Now, normal application code executed from main Flash memory. RS-232 cable attached, main Flash blank invalid. Action 8031 boots from EES0/EES1, runs checksum Flash memory, checks UART pending host download request main Flash, waits until UART traffic present (Figure F1). RS-232 cable attached, main Flash blank invalid. Action 8031 boots from EES0/EES1, runs checksum Flash memory, checks UART pending host download request main Flash, programs main Flash memory with data from UART, sets register main Flash into program space (Figure F2), sets SWAP which swaps EES0/EES1 with (Figure F3), sets register EEPROM into data space (Figure F4). Now, system normal operating
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mode. Next, 8031 checks UART host download request boot memory, then sets ENABLE_DATA_HALF boot download request exists. Now, normal application code executed from main Flash memory. RS-232 cable attached, main Flash valid, system requests boot memory Action System boots from EES0/EES1, runs checksum Flash memory, checks UART pending host download request main Flash (Figure F1), sets register main Flash into program space (Figure F2), sets SWAP which swaps EES0/EES1 with (Figure F3), sets register EEPROM into data space (Figure F4). Now, system normal operating mode. Next, 8031 checks UART host download request boot memory, programs EEPROM boot memory EES0 EES1 with data from UART, runs checksum EES0 EES1, then sets ENABLE_DATA_HALF protect boot code EES0 EES1 from inadvertent writes, enable data access EES2 EES3. Now, normal application code executed from main Flash memory.
Note: these host UART download options, assumed that normal boot (EES0/EES1) area programmed very first time device programmer before installed circuit card JTAG interface while in-system.
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