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Understanding High Speed Testing Evaluation
Brad Brannon Reeder
SCOPE
This document describes both characterization production test methods used Analog Devices' High Speed Converter Group evaluate high speed ADCs. While this application note should considered reference, substitute product data sheet.
DYNAMIC TEST HARDWARE SETUP
SNR, SINAD, worst spur, tested using hardware setup similar that shown Figure production tests, test hardware highly integrated, hardware principles same. basic setup dynamic testing includes signal generator, band-pass filter, test fixture, noise power supply, encode source (often integrated evaluation board), data acquisition module, data analysis software. Analog Devices provides application hardware software bench evaluation. FIFO section.
WALL OUTLET 100V 240V 47Hz 63Hz 3.3V SWITCHING POWER SUPPLY PARALLEL CMOS OUTPUTS EVALUATION BOARD BAND-PASS FILTER XFMR INPUT PARALLEL CMOS OUTPUTS
FIFO board connected through standard cable used with Analyzer software quickly evaluate performance high speed ADCs. Users view specific analog input clock rate analyze SNR, SINAD, SFDR, harmonic information. There single-channel dual-channel versions FIFO board available. FIFO data sheet should consulted determine which version required specific ADC. LVDS serial output devices need additional adapter board called HSC-ADC-FPGA. This will specified product data sheet. more detailed information HSC-ADC-FPGA serial LVDS adapter board, FIFO, Analyzer software works Analog Devices website www.analog.com/FIFO.
STANDARD
ROHDE SCHWARZ, SMHU, SIGNAL SYNTHESIZER ROHDE SCHWARZ, SMHU, SIGNAL SYNTHESIZER
HSC-ADC-EVALB-DC FIFO DATA CAPTURE BOARD CONNECTION
RUNNING ANALYZER
SINGLE DUAL HIGH-SPEED EVALUATION BOARD
HSC-ADC-EVALB-SC HSC-ADC-EVALB-DC FIFO, 32K, 133MHz TIMING CIRCUIT FIFO, 32k, 133MHz
05941-002
05941-001
+3.0V
FIFO
high speed FIFO evaluation includes memory board capture blocks digital data from Analog Devices' high speed analog-to-digital converter (ADC) evaluation boards Analyzersoftware. more information FIFO evaluation kit, visit www.analog.com/FIFO.
CLOCK CIRCUIT CLOCK INPUT
LOGIC
Figure Typical Characterization Test Setup
FILTERED ANALOG INPUT
CTLR
120-PIN CONNECTOR
Figure Typical FIFO Setup
Rev. Page
AN-835 TABLE CONTENTS
Scope Dynamic Test Hardware Setup FIFO Kit. Revision History Background ADIsimADC Analog Signal Source Analog Signal Filter. Encode signal sources Power Supplies Data Acquisition. Test Definitions Testing. Single-Tone Two-Tone Noise Power Ratio (NPR, dB). Full Power Bandwidth (MHz) Dither Testing Analog Input Analog Input Full-Scale Range p-p). Common-Mode Input Range Common-Mode Rejection Ratio (CMRR, Aperture Delay (ps). Aperture Jitter Aperture Uncertainty RMS) Crosstalk (dB) Input-Referred Noise (LSB RMS) Out-of-Range Recovery Time (CLK Cycles) Digital Time Domain. Conversion Error Rate (CER). Test Definitions Gain Error (%FS). Gain Matching (%FS) Offset Error (%FS) Offset Matching (mV) Temperature Drift (ppm) Voltage Output High/Voltage Output (VOH/VOL, Linearity. Power Supply Rejection Ratio (PSRR, References.
REVISION HISTORY
4/06-Revision Initial Version
Rev. Page
AN-835 BACKGROUND
IDT72V283 16-BIT 133MHz FIFO
SWITCHING POWER SUPPLY CONNECTION
TIMING ADJUSTMENT JUMPERS 120-PIN CONNECTOR (PARALLEL CMOS INPUTS)
BOARD +3.3V REGULATOR
OPTIONAL POWER CONNECTION
IDT72V283 16-BIT 133MHz FIFO CONNECTION COMPUTER OPEN SOLDER MASK DATA CLOCK LINES EASY PROBING
Figure Dual-Channel FIFO Board
ADIsimADC
ADIsimADCis Analog Devices behavioral modeling tool. ADIsimADC accurately models many time frequency domain errors common ADCs. This tool invaluable terms both simple converter selection complete system simulation. tool fully integrated into Analyzer software simple converter selection; also supported several third-party vendors. Currently, ADIsimADC supported MATLAB®, C++, National Instruments' LabVIEWand Signal Express, Agilent's ADS, Applied Wave Research's Visual System StimulatiorTM. Others will available future. tool downloaded from website along with complete collection current models. Links provided third-party tools that support ADIsimADC. (For more information ADIsimADC behavioral modeling, visit www.analog.com/ADIsimADC.) mentioned, tool provided with Analyzer software, which provides direct access ADIsimADC, allowing users simulate given based behavioral model
hardware required). Information about ADIsimADC found www.analog.com/ADIsimADC. more detailed information ADIsimADC, AN-737 Application Note.
05941-003
OPTIONAL SERIAL PORT INTERFACE CONNECTOR
RESET SWITCH WHEN ENCODE RATE INTERRUPTED
µCONTROLLER CRYSTAL CLOCK 24MHz, DURING DATA CAPTURE
Figure Analyzer
Rev. Page
05941-004
AN-835
ANALOG SIGNAL SOURCE
Usually, dynamic testing employs Rohde Schwarz (www.rohde-schwarz.com) SMA/SMHU/SMG/SMGU, Agilent (www.agilent.com) 8644 signal generator, Wenzel (www.wenzel.com) crystal oscillator. These sources have proven provide exceptional performance (low phase noise, flat frequency response, reasonable harmonic performance) frequencies kilohertz those gigahertz. Harmonic performance these generators typically good intrinsic linearity given ADC, mandating need additional filtering between signal generator analog input ADC. frequency guaranteed stop-band performance. case TTE's Q56, stop-band rejection
0dBc
RELATIVE ATTENUATION (-10dB/DIV)
RELATIVE ATTENUATION (-10dB/DIV)
Both fixed frequency tunable frequency band-pass filters utilized device testing. fixed frequency filters typically smaller than tunable filters often provide slightly better performance. Tunable filters allow testing across wide range frequencies using filter. Several filter manufacturers, including Microwave (www.klmicrowave.com), (www.tte.com), Allen Avionics, Inc., (www.allenavionics.com), provide excellent filters testing. There types filters that often used testing: low-pass filters band-pass filters. These used individually combined yield level performance required application. Low-pass filters good choice when wide range analog frequencies must applied ADC. However, they allow noise pass from signal generator ADC. This noise reduce level performance measured ADC. typical low-pass filter available from TTE. Usually, low-pass filters have transition band that defines where pass band ends stop band begins. Along with this specification, guaranteed stop-band rejection specified. case J97, transition band defined between times frequency, guaranteed stopband rejection Energy beyond times frequency reduced minimum Band-pass filters used when analog frequencies fixed will changed. Band-pass filters also eliminate much wideband noise generated signal sources typically provide best performance testing. Filters such TTE's series have bandwidth defined percentage center frequency. more narrow bandwidth, less noise that passes through filter; however, analog frequency more restricted, there greater insertion loss. Once center frequency chosen, bandwidth determined. Ideally, bandwidth should selected, keeping mind that good noise performance being traded analog frequency flexibility. with low-pass filters, band-pass filter transition band that defines shape between frequency (above below center frequency)
F/Fo RATIO
NOTE REPRINTED WITH PERMISSION FROM TTE.
Figure Typical Performance TTE's
0dBc
F/Fo RATIO
NOTE REPRINTED WITH PERMISSION FROM TTE.
Figure Typical Band-Pass Performance TTE's
noted previously, band-pass filters only have stopband rejection meaning that signals that fall into stop band will rejected example, signal source harmonic that below fundamental, effective level harmonic after filter. many high performance ADCs, this sufficient. When performance -100 better required, common cascade band-pass filter with low-pass filter. When selecting low-pass filter follow band-pass filter, low-pass frequency should selected such that stop-band performance lowpass filter optimally filters harmonics that pass through band-pass filter. With low-pass filter, stop-band rejection reached times frequency. second harmonic band-pass filter equal times low-pass frequency, ensures that harmonics passing through bandpass filter filtered that additional insertion loss low-pass filter does significantly reduce level desired pass band. this case, low-pass frequency should equal times band-pass frequency theoretically
Rev. Page
05941-006
05941-005
ANALOG SIGNAL FILTER
AN-835
cascaded rejection should about Although this difficult achieve practice coupling radiation effects, this technique useful achieve well beyond -100 harmonic rejection. also worth noting that placed between band-pass low-pass series combination. This helps provide better match between filters, which nominally specified When specifying filters, request those made with large cores prevent saturation. Filters typically designed input power about dBm. many cases, however, drive requirements much larger than this, causing core saturation distortion. Specifying larger cores reduces spurious distortion caused core saturation. Finally, worth mentioning that filter connectors also specified. Although adapters easily found convert between connector types, using them introduces mismatches that subtly affect converter performance. While this might problem with 8-bit 10-bit converters, quite noticeable with 12-, 14-, 16-bit converters. very important that appropriate clock oscillator used each design. Selection proper clock aided Analog Devices AN-501 Application Note AN-756 Application Note. These application notes explain measure aperture jitter specify clock that meets required phase noise jitter specification. Failure properly specify clock source will degrade performance, shown Figure Figure reference, typical Wenzel clock oscillator about 0.07 aperture jitter, whereas CMOS clock oscillators have about more aperture jitter.
ENCODE SIGNAL SOURCES
high performance converters, stock signal generators usually insufficient encode sources because both close-in wideband phase noise. Fixed-frequency oscillators typically used encode sources. High performance crystal oscillators manufactured Wenzel (www.wenzel.com) Techtrol Cyclonetics, Inc., (TCI) (www.tci-ant.com) used. Wenzel's Sprinter Ultra Noise series offer optimum phase noise performance. Another source high quality encode sources Valpey Fisher (www.valpeyfisher.com), which offers several options, including differential PECLs VCXOs. less demanding applications, standard CMOS clock modules used available from various manufacturers. applications that require clock synchronized with external reference, voltage-controlled crystal oscillator (VCXO) loop employed.
05941-008
Figure AD9445 with Analog -1.0 dBFS using Wenzel Clock, 75.2 dBFS
Figure AD9445 with Analog -1.0 dBFS using CMOS Clock, 71.2 dBFS
When clock sources available with desired jitter performance, possible divide higher frequency clock into lower rates. This effect reducing jitter rate log(x), where division ratio. limitation this, however, jitter gates themselves. AN-501 Application Note provides indication clock jitter associated with various logic families. When custom clocking desired, often required. allows synchronized external clock reference using VCXO. However, difficult clock more than device using simple PLL, adding delays between devices facilitate such clocking. Devices such AD9510 ideal clock cleanup distribution.
Rev. Page
05941-007
Figure Typical Cost CMOS Clock Oscillator
05941-009
AN-835
additive jitter AD9510 about 0.22 device optimized driving ADCs, DACs, various logic devices.
DATA ACQUISITION
Data acquisition processing accomplished with high speed caching memory. Data collected full speed decimated depending testing method used. Bench testing uses FIFO data capture board decimation required) conjunction with Analyzer software (See FIFO section more details). Typically 16k, 32k, FFTs performed, bench FFTs large samples. When analog input source synchronized with clock (noncoherent sampling), Hanning BlackmanHarris windowing function typically used. (For more information, Windows Harmonic Analysis with Discrete Fourier Transform," Fredric Harris, Proceedings IEEE. Vol. January 1978.)
POWER SUPPLIES
Power supplies ADCs very important. Therefore, important provide clean, quiet power supplies because most ADCs have poor power supply rejection ratios. While switching regulators fine many applications, linear regulators often provide quieter, higher performance solution. Devices such ADP3338 ADP3339 provide very noise wellregulated sources, they very suitable most applications. Additionally, they available variety voltages source respectively.
ADP3338/ ADP3339
10µH VOUT
05941-011
Figure ADP3338/ADP3339 Typical Application
RSET DISTRIBUTION
CPRSET
AD9510
PHASE FREQUENCY DETECTOR
CHARGE PUMP
REFIN REFINB SYNCB, RESETB
DIVIDER DIVIDER
FUNCTION
SETTINGS
STATUS CLK2
CLK1 CLK1B PROGRAMMABLE DIVIDERS PHASE ADJUST /31, LVPECL /31, LVPECL /31, SCLK SDIO /31, LVDS/CMOS /31, LVDS/CMOS /31, LVDS/CMOS SERIAL CONTROL PORT /31, LVDS/CMOS LVPECL
CLK2B LVPECL OUT0 OUT0B OUT1 OUT1B OUT2 OUT2B OUT3 OUT3B OUT4 OUT4B OUT5 OUT5B OUT6 OUT6B OUT7 OUT7B
05941-010
/31,
Figure AD9510 Jitter Clock Source
Rev. Page
AN-835 TEST DEFINITIONS
dynamic tests typically made with analog signal rated frequency with signal power below full scale (dBFS). different amplitudes used, they will defined data sheet test conditions. these tests, encode rate usually near maximum rated value. data sheet should consulted determine remainder test conditions, including power supply temperature conditions.
Signal-to-Noise Ratio Referenced Full Scale (SNRFS, dBFS)
signal-to-noise ratio referenced full scale (SNRFS) ratio full scale value spectral components except first harmonics SNRFS expressed decibels referenced full scale (dBFS). difference between SNRFS difference between fundamental amplitude full scale.
TESTING
Both coherent noncoherent testing used, depending actual test conditions. When coherent testing used, analog frequency chosen such that captured data samples exercise many converter codes possible record length. This accomplished using prime relationship between analog frequency encode rate. example, coherent sampling used analog input desired with specified sample rate MSPS, calculated coherent analog input frequency 10.0015258789063 MHz, exactly 2521 cycles. This calculated using following equation:
Cycles DESIRED FREQUENCY Sample Rate Samples
Signal-to-Noise-and-Distortion (SINAD,
signal-to-noise distortion (SINAD) ratio signal amplitude value spectral components, including harmonics excluding difference between SINAD energy contained first harmonics.
User-Defined Signal-to-Noise Ratio (UDSNR,
User-defined signal-to-noise ratio (UDSNR) term used Analyzer software (see Analyzer User Manual). ratio signal amplitude spectral components except first harmonics within specified band user. Analyzer software allows noise bandwidth left right desired signal independently. UDSNR reported decibels.
number cycles should rounded nearest integer. When possible, nearest prime number should selected ensure that maximum number quantization levels converter exercised. Once number cycles been selected, previous equation solved using desired analog input frequency. testing typically results measurements expressed decibels. Units expressed dBc, which desired signal referenced carrier, dBFS, which desired signal referenced full scale converter. Either unit converted other adding subtracting level carrier from full scale. (For more information about testing, "The FFT: Fundamentals Concepts," Tektronix, Inc., 070-1754-00, Production Group first printing December 1975.)
Noise Figure (NF,
noise figure (NF) ratio noise power output device noise power input device, where input noise temperature equal reference temperature (298 noise figure expressed decibels. noise figure computed single configuration. Assuming that input range, termination, sample rate fixed, calculated using following equation:
Noise Figure 0.001 Encode Frequency SNRFS 0.001
SINGLE-TONE
Signal-to-Noise Ratio (SNR,
signal-to-noise ratio (SNR) ratio signal amplitude value spectral components except first harmonics input level decreased, typically decreases decibel-for-decibel linear fashion.
where: Boltzman's constant 1.38 10-23 temperature Kelvin bandwidth Encode Frequency clock rate full-scale input voltage input impedance SNRFS full-scale
Noise Floor (dBFS)
Noise floor term used Analyzer software (see Analyzer User Manual). Noise floor equivalent
Bins Noise Floor SNRFS
Rev. Page
AN-835
This indication average noise each bin. size doubled, this number decreases Noise floor does provide absolute measurement, instead gives relative indication where noise given setup. Most ADCs have specifications more harmonics. Typically, second third harmonics singled because they have worst performance harmonics. Harmonic distortion, matter order, ratio signal amplitude value specified harmonic component, reported dBFS. Because ADCs nonlinear devices, output rich spectral components. worst spurious energy directly related first harmonics (2HD 3HD) measured worst other spurious (WoSpur). WoSpur ratio signal amplitude value worst spurious component excluding first harmonically related components; reported dBc.
Effective Number Bits (ENOB, Bits)
effective number bits (ENOB) provide measure ADC's performance that expressed bits. ENOB most accurately measured using sine wave, curve-fit method (see Calculate ADC's Effective Bits). most common method computing ENOB following equation based SINAD full scale converter:
ENOB
SINAD 1.76 6.02
Spurious-Free Dynamic Range (SFDR, dBc)
spurious-free dynamic range (SFDR) ratio value signal value peak spurious spectral component analog input that produces worst result. most cases, SFDR harmonic input signal applied ADC.
Total Harmonic Distortion (THD, dBc)
Total harmonic distortion (THD) ratio signal energy value first harmonics.
Harmonic Image (dBc)
harmonic image measurement result valid only when analyzing interleaved ADCs. This specification does apply most ADCs. Harmonic image ratio signal amplitude value nonharmonic component generated from clocking phase difference ADCs, reported dBc.
Harmonic Distortion (dBc dBFS)
harmonic spectral component that integer multiple driven analog input frequency. example, frequency second harmonic twice analog input.
WENZEL XTAL ROHDE SCHWARZ AGILENT
ANALOG OUTPUT
PAD1
MICROWAVE
PAD1
MICROWAVE LPF1
WENZEL XTAL ROHDE SCHWARZ AGILENT
DIFFERENTIAL SINGLE-ENDED
ENCODE INPUT
ANALOG INPUT ADC-FIFO BOARD
STANDARDIZED SUPPLIES
SUPPLY INPUT
AD92xx, AD94xx, AD66xx EVALUATION BOARD
SUPPLY INPUT
STANDARDIZED SUPPLIES
MONITOR
OPTIONAL
IMPROVE PERFORMANCE.
NOTES LEVELS SHOULD ADJUSTED FREQUENCY LEVEL SPECIFIED. ENCODE SETTING SHOULD ADJUSTED SPECIFIED RATE. UNLESS ONBOARD REGULATORS USED, SUPPLIES SHOULD NOMINAL. TEMPERATURE SHOULD AMBIENT, UNLESS OTHERWISE NOTED. APPROPRIATE CONFIGURATION FILE ANALYZER.
Figure Single-Tone Test Setup
Rev. Page
05941-012
AN-835
TWO-TONE
When multiple tones passed through converter with nonlinearities, intermodulation distortion products (IMD) result. Two-tone testing means specifying these nonlinearities. Because many distortion products relatively high analog spectrum, possible that frequencies have aliased. This should kept mind when identifying distortion products.
(dBc)
These terms represent third-order distortion products converter. measure each term ratio value value input tones expressed dBc. peak spurious component considered product.
Third-Order Input Intercept Point (IIP3, dBm)
third-order input intercept point (IIP3) measure full-scale input signal power converter minus half third-order products. reported dBm.
(dBc)
This term represents second-order distortion product that appears frequency input frequencies. measure this term ratio value value input tones expressed dBc.
Worst Other Spur (WoSpur, dBc)
worst other spur (WoSpur) worst resulting spurious related second- third-order distortion products resulting from mixing analog input signals. measure this term ratio value value input tones expressed dBc.
(dBc)
This term represents second-order distortion product that appears frequency difference input frequencies. measure this term ratio value value input tones expressed dBc.
Two-Tone SFDR (dBc)
spurious-free dynamic range (SFDR) ratio value signal value peak spurious spectral component analog input that produces worst result. most cases, SFDR harmonic input signal applied ADC.
Second-Order Input Intercept Point (IIP2, dBm)
second-order input intercept point (IIP2) measure full-scale input signal power converter minus second-order products. reported dBm.
WENZEL XTAL ROHDE SCHWARZ AGILENT ANALOG OUTPUT MICROWAVE
10dB PAD1
WENZEL XTAL ROHDE SCHWARZ AGILENT
ANALOG OUTPUT
MICROWAVE
10dB PAD1
MINI-CIRCUITS COMBINER ZFSC-2-1
WENZEL XTAL ROHDE SCHWARZ AGILENT
DIFFERENTIAL SINGLE-ENDED
ENCODE INPUT
ANALOG INPUT ADC-FIFO BOARD
STANDARDIZED SUPPLIES
SUPPLY INPUT
AD92xx, AD94xx, AD66xx EVALUATION BOARD
SUPPLY INPUT
STANDARDIZED SUPPLIES
MONITOR
OPTIONAL IMPROVE PERFORMANCE.
NOTES LEVELS SHOULD ADJUSTED FREQUENCY LEVEL SPECIFIED. ENCODE SETTING SHOULD ADJUSTED SPECIFIED RATE. UNLESS ONBOARD REGULATORS USED, SUPPLIES SHOULD NOMINAL. TEMPERATURE SHOULD AMBIENT, UNLESS OTHERWISE NOTED. APPROPRIATE CONFIGURATION FILE ANALYZER.
Figure Two-Tone Test Setup
Rev. Page
05941-013
AN-835
NOISE POWER RATIO (NPR,
noise power ratio (NPR) dynamic test that used assess converters performance with fully loaded Gaussian noise source. noise level adjusted such that converter loaded just below point clipping with Nyquist-limited noise source. Then narrow band noise removed with deep notch filter. noise within notch measured using techniques
16-BIT
determine ratio noise density notch noise density without notch. results expressed decibels. optimized just prior clipping, shown Figure Once clipping begins, falls rapidly input signal increased. input signal reduced, falls approximately each decibel reduction noise power.
60.83dB NOTCH 18.0MHz NOTCH WIDTH 3.0MHz
14-BIT
AMPLITUDE (dBFS)
05941-014
(dB)
12-BIT 10-BIT
-100
05941-015
-120
(VO/N rms) (dBFS)
FREQUENCY (MHz)
Figure Typical Curves
Figure Typical Response 12-Bit Converter
NOISE/COM NC7108 NOISE GENERATOR
ANALOG OUTPUT
18MHz NOISE/COM NOTCH FILTER
MICROWAVE ANTI-ALIAS FILTER
WENZEL XTAL ROHDE SCHWARZ AGILENT
DIFFERENTIAL SINGLE-ENDED
ENCODE INPUT
ANALOG INPUT ADC-FIFO BOARD
STANDARDIZED SUPPLIES
SUPPLY INPUT
AD92xx, AD94xx, AD66xx EVALUATION BOARD
SUPPLY INPUT
STANDARDIZED SUPPLIES
MONITOR
Figure Test Setup
Rev. Page
05941-016
NOTES NOISE/COM ~5dBm DECREMENT/INCREMENT APPROPRIATE NOISE INPUT LEVEL. ENCODE SETTING SHOULD ADJUSTED SPECIFIED RATE. UNLESS ONBOARD REGULATORS USED, SUPPLIES SHOULD NOMINAL. TEMPERATURE SHOULD AMBIENT, UNLESS OTHERWISE NOTED. APPROPRIATE CONFIGURATION FILE ANALYZER. ADC-FIFO BOARD WITH LEAST 64k.
AN-835
FULL POWER BANDWIDTH (MHz)
Analog input bandwidth analog input frequency which spectral power fundamental frequency determined analysis) reduced particular value SFDR performance implied this test.
FUNDAMENTAL LEVEL (dB)
05941-017
-3dB CUTOFF 315MHz
FREQUENCY (MHz)
Figure Typical Full Power Bandwidth Response
ROHDE SCHWARZ AGILENT
ANALOG OUTPUT
ADAPTER
ANALOG INPUT
BOONTON 9200B VOLTMETER
GPIB WENZEL XTAL ROHDE SCHWARZ AGILENT DIFFERENTIAL SINGLE-ENDED ENCODE INPUT STANDARDIZED SUPPLIES SUPPLY INPUT ANALOG INPUT ADC-FIFO BOARD
AD92xx, AD94xx, AD66xx EVALUATION BOARD
SUPPLY INPUT
STANDARDIZED SUPPLIES
MONITOR
GPIB
Figure Full Power Bandwidth Test Setup
Rev. Page
05941-018
NOTES LEVELS SHOULD ADJUSTED -1dB 10MHz REFERENCE FREQUENCY. ENCODE SETTING SHOULD ADJUSTED SPECIFIED RATE. UNLESS ONBOARD REGULATORS USED, SUPPLIES SHOULD NOMINAL. TEMPERATURE SHOULD AMBIENT, UNLESS OTHERWISE NOTED. APPROPRIATE CONFIGURATION FILE ANALYZER. BOONTON PROBES SHOULD UNTERMINATED ADAPTERS.
AN-835
DITHER TESTING
Applying extra noise ADC's analog input causes dithering transfer function, reducing spurious caused static nonlinearities. While dither does little reduce distortion caused slew rate limitations, very efficient reducing localized errors that hinder performance. There types dither: out-of-band wideband. shown setup Figure out-of-band dither bandlimited noise placed band, where will spectrally disrupt converter performance. This technique commonly used communication systems, where digital filters used select desired signals filter others. Wideband dither often used high performance test equipment. this configuration, wideband analog noise added input digital equivalent subtracted from output. effect either technique that spurious performance converter greatly enhanced. more details, AN-410 Application Note. common spurious performance improve more when dither used, depending application. Many data sheets include dithered performance plots comparison. addition, using Analyzer software with ADIsimADC allows dither added simulation, further demonstrating dither will improve performance.
NOISE/COM DNG7500 NOISE GENERATOR
ANALOG OUTPUT
MICROWAVE 1.5MHz
WENZEL XTAL ROHDE SCHWARZ AGILENT
ANALOG OUTPUT
MICROWAVE
MINI-CIRCUITS COMBINER ZFSC-2-1
WENZEL XTAL ROHDE SCHWARZ AGILENT
DIFFERENTIAL SINGLE-ENDED
ENCODE INPUT
ANALOG INPUT ADC-FIFO BOARD
STANDARDIZED SUPPLIES
SUPPLY INPUT
AD92xx, AD94xx, AD66xx EVALUATION BOARD
SUPPLY INPUT
STANDARDIZED SUPPLIES
MONITOR
NOTES LEVELS SHOULD ADJUSTED FREQUENCY LEVEL SPECIFIED. ENCODE SETTING SHOULD ADJUSTED SPECIFIED RATE. UNLESS ONBOARD REGULATORS USED, SUPPLIES SHOULD NOMINAL. TEMPERATURE SHOULD AMBIENT, UNLESS OTHERWISE NOTED. APPROPRIATE CONFIGURATION FILE ANALYZER. ADJUST BINS EXCLUDE DITHER. ADC-FIFO BOARD WITH LEAST 64k. ADJUST NOISE/COM DITHER LEVEL MAXIMUM SFDR PERFORMANCE.
Figure Dither Test Setup
Rev. Page
05941-019
AN-835
ANALOG INPUT
Analog Input Impedance
Analog input impedance ratio complex input voltage divided complex input current analog input. Analog input impedance typically measured with network analyzer displayed Smith chart. some instances, complex input broken down into resistive, capacitive, inductive terms reported such. amount power reflected back from device computed from input impedance based following equation:
Voltage Standing Wave Ratio (VSWR)
VSWR measure amount power that reflected back from input ADC. This measure efficiency transfer energy input port ADC.
where: amount power reflected back from device. complex input impedance ADC. desired impedance network. From reflection coefficient, VSWR calculated using following equation:
VSWR
ENA5071B NETWORK ANALYZER WENZEL XTAL ROHDE SCHWARZ AGILENT
DIFFERENTIAL SINGLE-ENDED
ENCODE INPUT
ANALOG INPUT
STANDARDIZED SUPPLIES
SUPPLY INPUT
AD92xx, AD94xx, AD66xx EVALUATION BOARD
NOTES ENCODE SETTING SHOULD ADJUSTED SPECIFIED RATE. UNLESS ONBOARD REGULATORS USED, SUPPLIES SHOULD NOMINAL. TEMPERATURE SHOULD AMBIENT, UNLESS OTHERWISE NOTED. APPROPRIATE CONFIGURATION FILE ANALYZER. CALIBRATE NETWORK ANALYZER (3.5mm CALIBRATION KIT, PART 85033C EQUIVALENT.
Figure Analog Input Impedance VSWR Test Setup
Rev. Page
05941-020
AN-835
ANALOG INPUT FULL-SCALE RANGE p-p)
Analog input full-scale range range peak-to-peak voltage (either single-ended differential) that applied analog input(s) converter generate valid fullscale response.
ROHDE SCHWARZ AGILENT
ANALOG OUTPUT
ANALOG INPUT
BOONTON 9200B VOLTMETER
GPIB WENZEL XTAL ROHDE SCHWARZ AGILENT DIFFERENTIAL SINGLE-ENDED ENCODE INPUT STANDARDIZED SUPPLIES SUPPLY INPUT ANALOG INPUT ADC-FIFO BOARD
AD92xx, AD94xx, AD66xx EVALUATION BOARD
SUPPLY INPUT
STANDARDIZED SUPPLIES
MONITOR
GPIB
NOTES LEVELS SHOULD ADJUSTED -1dB 10MHz. ENCODE SETTING SHOULD ADJUSTED SPECIFIED RATE. UNLESS ONBOARD REGULATORS USED, SUPPLIES SHOULD NOMINAL. TEMPERATURE SHOULD AMBIENT, UNLESS OTHERWISE NOTED. APPROPRIATE CONFIGURATION FILE ANALYZER. BOONTON PROBES SHOULD UNTERMINATED ADAPTERS.
Figure Analog Input Full-Scale Range Test Setup
Rev. Page
05941-021
AN-835
COMMON-MODE INPUT RANGE
Common-mode input range range offsets applied both inputs differential input which converter will operate normally. many converters, range very limited, some operate over wide common-mode range. converter's data sheet should consulted determine specific common-mode range.
COMMON-MODE REJECTION RATIO (CMRR,
common-mode rejection ratio (CMRR) defined amount rejection differential analog inputs when common signal applied. Typically, CMRR expressed decibels calculated shown following equation:
CMRR DIFFERENTIAL ACOMMON MODE
WENZEL XTAL ROHDE SCHWARZ AGILENT
ANALOG OUTPUT
PAD1
MICROWAVE
PAD1
MICROWAVE LPF1
WENZEL XTAL ROHDE SCHWARZ AGILENT
DIFFERENTIAL SINGLE-ENDED
ENCODE INPUT
ANALOG INPUT
ADC-FIFO BOARD
STANDARDIZED SUPPLIES
SUPPLY INPUT
AD92xx, AD94xx, AD66xx EVALUATION BOARD
SUPPLY INPUT
STANDARDIZED SUPPLIES
MONITOR
OPTIONAL
IMPROVE PERFORMANCE.
Figure CMRR Test Setup
Rev. Page
05941-022
NOTES LEVELS SHOULD ADJUSTED FREQUENCY LEVEL SPECIFIED. ENCODE SETTING SHOULD ADJUSTED SPECIFIED RATE. UNLESS ONBOARD REGULATORS USED, SUPPLIES SHOULD NOMINAL. TEMPERATURE SHOULD AMBIENT, UNLESS OTHERWISE NOTED. APPROPRIATE CONFIGURATION FILE ANALYZER. RESISTIVE DIVIDER NECESSARY SOME ADCs.
AN-835
APERTURE DELAY (ps)
Aperture delay (AD) measure difference delay between analog path encode path. measured observing time from point rising edge sample clock time which input signal actually sampled. measured using following test configuration: Connect analog input analog filtered source. Using program like Analyzer, adjust input until single-tone results full-scale signal dBFS). Disconnect analog input, shorting short analog input ground. continuous average time domain plot measure offset part. Remove shorting from analog input reconnect analog input shown Figure Record offset value solve following equation:
(Code AVERAGE Offset )/(2 Frequency
where: 2N/2 midscale 16-bit ADC. Offset offset part measured using continuous average time domain plot (see Step CodeAVERAGE offset value obtained after removing shorting from analog input reconnecting analog input (see Step
WENZEL XTAL ROHDE SCHWARZ AGILENT
ANALOG OUTPUT ADAPTER SHORTING
WENZEL XTAL ROHDE SCHWARZ AGILENT
DIFFERENTIAL SINGLE-ENDED
ENCODE INPUT
ANALOG INPUT ADC-FIFO BOARD
STANDARDIZED SUPPLIES
SUPPLY INPUT
AD92xx, AD94xx, AD66xx EVALUATION BOARD
SUPPLY INPUT
STANDARDIZED SUPPLIES
MONITOR
Figure Aperture Delay Test Setup
Rev. Page
05941-023
NOTES LEVELS SHOULD ADJUSTED 0dBFS OUTPUT INPUT FREQUENCY MIDBAND. ENCODE SETTING SHOULD ADJUSTED SPECIFIED RATE. UNLESS ONBOARD REGULATORS USED, SUPPLIES SHOULD NOMINAL. TEMPERATURE SHOULD AMBIENT, UNLESS OTHERWISE NOTED. APPROPRIATE CONFIGURATION FILE ANALYZER.
AN-835
APERTURE JITTER APERTURE UNCERTAINTY RMS)
Aperture jitter sample-to-sample variation aperture delay that manifested frequencydependent noise input. Details measuring aperture jitter found AN-501 Application Note, details converting aperture jitter phase noise found AN-756 Application Note. results expressed decibels ratio energy undesired signal quite channel energy driven channel.
INPUT-REFERRED NOISE (LSB RMS)
Input-referred noise measure wideband noise generated ADC. histogram output codes created while input grounded. Input-referred noise calculated using standard deviation histograms, presented terms rms. This measurement also correlated using SNRFS measurements converting decibels volts using following equation:
Noise INPUT
ERROR VOLTAGE
where full-scale input range, full-scale performance when driven small input signal.
OUT-OF-RANGE RECOVERY TIME (CLK CYCLES)
Out-of-range recovery time time required recover rated accuracy after input transient moves from above positive full scale above negative full scale from below negative full scale below positive full scale.
ENCODE
05941-024
Figure Aperture Uncertainty
CROSSTALK (dB)
Crosstalk defined measure feedthrough coupling onto quiet channel multichannel ADC. Crosstalk measured three ways under conditions.
DIGITAL TIME DOMAIN
Minimum Conversion Rate (MSPS)
minimum conversion rate clock rate which lowest specified analog signal frequency drops more than below guaranteed limit.
Condition
signal driven near full scale, crosstalk measured following methods:
Maximum Conversion Rate (MSPS)
maximum conversion rate clock rate which parametric testing performed. Higher operating rates possible, they guaranteed.
Drive channels using different midbaseband frequency each that least apart -0.5 dBFS. Record same fundamental frequency open channel (nondriven). Repeat channel combinations. Drive channel using single midbaseband frequency -0.5 dBFS. Record same fundamental frequency open channel (nondriven). Repeat channel combinations.
Pipeline Delay (CLK Cycles)
Pipeline delay delay through converter function encode cycles. maximize throughput, many high speed converters leverage pipeline processing. result, corresponding data output until several clock cycles after signal sampled. This delay pipeline delay expressed whole fractional clock cycles, depending data converter.
Condition
signal driven over full scale, known overdriven condition, crosstalk measured follows:
either method described Condition section, with midbaseband frequency amplitude above full scale.
Rev. Page
AN-835
Propagation Delay (ns)
Propagation delay delay between clock logic threshold point differential clock input) time when bits within valid logic levels. state insufficient amount time, sample process will fail complete. held state insufficient amount time, circuit will fail accurately acquire signal sampled. Optimal operation achieved when acquire sample times suitably balanced. many converters, encode duty cycle provided instead pulse-width measurements. This usually stated maximum rated encode expressed range percentage time that encode line high state. this test, rated performance defined range over which SNRFS performance within nominal performance.
Encode Pulse Width Encode Duty Cycle
Encode pulse width high minimum amount time that encode signal logic high state achieve specified performance. Encode pulse width minimum amount time that encode signal logic state achieve specified performance. traditional ADC, when encode signal logic high state, circuit sample mode. held high
TEKTRONIX 854C 500MHz OSCILLOSCOPE
WENZEL XTAL ROHDE SCHWARZ AGILENT
ANALOG OUTPUT
WENZEL XTAL ROHDE SCHWARZ AGILENT
DIFFERENTIAL SINGLE-ENDED ENCODE INPUT
ANALOG INPUT
STANDARDIZED SUPPLIES
SUPPLY INPUT
AD92xx, AD94xx, AD66xx EVALUATION BOARD
Figure Propagation Delay Test Setup
Rev. Page
05941-025
NOTES SHOULD FREQUENCY FULL-SCALE SIGNAL. ENCODE SETTING SHOULD ADJUSTED SPECIFIED RATE. UNLESS ONBOARD REGULATORS USED, SUPPLIES SHOULD NOMINAL. TEMPERATURE SHOULD AMBIENT, UNLESS OTHERWISE NOTED. APPROPRIATE REVS EVALUATION BOARD PARTS NOTED. OSCILLOSCOPE PROBES SHOULD SOLDERED DOWN GROUNDED. TEKTRONIX PROBES M/N: P6243 BETTER SHOULD USED. <1pF WITH 1GHz
AN-835
CONVERSION ERROR RATE (CER)
conversion error rate (CER) measurement frequency errors generated ADC. error defined output codes that fall outside bounds converter noise excess that allowed normally distributed noise. Converter noise defined noise normally generated quantization, thermal effects, clock jitter generally considered Gaussian. sample considered error frequency occurrence exceeds that predicted normal distribution.
05941-026
Once sigma been determined based expected from data sheet), method employed capture data such that expected code subtracted from actual code, resulting distribution histogram. With statistically large data set, expected that normal noise, resultant distribution will similar that shown Figure large distribution, excess samples these ranges indication errors, shown Table
Table Sigma Normal Probability Occurrence
3.09 3.72 4.26 4.75 5.20 5.61 6.36 Normal Probability Occurrence 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 Natural Occurrences Outside Million Samples 2000 0.02 0.002 0.0002
Figure Gaussian-Distributed Output
Noise magnitude normalized Sigma determined measuring full-scale then solving following equation using this value:
should noted that with sample rate MSPS, error outside 6.36 sigma normal 50-second window does constitute conversation error. Only when rate exceeds 10-10 conversation error indicated. practice, external devices including latching memory elements make difficult measure anything beyond about 10-6 10-7.
Rev. Page
AN-835 TEST DEFINITIONS
GAIN ERROR (%FS)
Gain error difference between measured full scale ideal full scale. This usually expressed percentage full scale.
VOLTAGE OUTPUT HIGH/VOLTAGE OUTPUT (VOH/VOL,
Voltage output high (VOH) voltage representing high logic level. Voltage output (VOL) voltage representing logic level. static tests typically made with very frequency test signals. purpose these tests determine baseline values many core converter specifications. Test conditions vary product; therefore, product's data sheet should consulted determine actual test conditions.
GAIN MATCHING (%FS)
Gain matching ratio maximum full scale minimum full scale multichannel ADC. expressed percentage full scale using following equation:
Gain Matching FSRMAX FSRMIN 100%
LINEARITY
There types converter linearity: differential nonlinearity (DNL) integral nonlinearity (INL). basic measure range voltages which each code active. integration these voltages determines overall transfer function converter. Together these basic measurements determine characteristic static performance ADC. These tests frequently performed using histogram techniques. histogram collected driving analog input with signal known statistical qualities. example, ramp quality uniform probability density function. This means that when driving input, each code equal probability occurring over large observation window. Other waveforms, such sine waves, have known functions well. Although such waveforms uniform, they accurately described mathematically (see Data Conversion Handbook, Walt Kester, Newness, 2005, Page 315.). Typical histogram tests performed taking large number samples reasonable. high resolution converters, this million samples more.
where FSRMAX most positive gain error ADC, FSRMIN most negative gain error.
OFFSET ERROR (%FS)
Offset error difference between measured ideal voltage analog input that produces midscale code output. This usually expressed percentage full scale.
OFFSET MATCHING (mV)
Offset matching difference offsets, expressed millivolts between channels multichannel converter. computed with following equation: Offset Matching VOFFSETMAX VOFFSETMIN where VOFFSETMAX most positive offset error, VOFFSETMIN most negative offset error. Offset matching usually expressed millivolts with full-scale input range stated product data sheet.
TEMPERATURE DRIFT (ppm)
temperature drifts offset error gain error specify maximum change from initial (25°C) value value TMIN TMAX. This usually expressed ppm.
Rev. Page
AN-835
Differential Nonlinearity Error (DNL, LSB)
Differential nonlinearity (DNL) variation code from ideal step. This measured examining each histogram bins comparing actual probability occurrence ideal probability. This results direct measure each code.
Integral Nonlinearity Error (INL, LSB)
Integral nonlinearity (INL) deviation transfer function from reference line measured fractions using best straight line determined least-mean-squared curve fit. This measured integrating histogram form transfer function then performing linear regression this function. difference between actual transfer function this best line INL.
05941-027
Figure Typical 10-Bit
Missing Code
code said missing that code LSB. missing code defined missing quantization level result from variety causes. Most products designed screened missing codes.
Figure Typical 10-Bit
WENZEL XTAL ROHDE SCHWARZ AGILENT
ANALOG OUTPUT
PAD1
MICROWAVE
PAD1
MICROWAVE LPF1
WENZEL XTAL ROHDE SCHWARZ AGILENT
DIFFERENTIAL SINGLE-ENDED
ENCODE INPUT
ANALOG INPUT ADC-FIFO BOARD
STANDARDIZED SUPPLIES
SUPPLY INPUT
AD92xx, AD94xx, AD66xx EVALUATION BOARD
SUPPLY INPUT
STANDARDIZED SUPPLIES
MONITOR
OPTIONAL
IMPROVE PERFORMANCE.
Figure Test Setup
Rev. Page
05941-029
NOTES LEVELS SHOULD ADJUSTED -0.01dBFS ABOUT 2.2MHz. ENCODE SETTING SHOULD ADJUSTED SPECIFIED RATE. UNLESS ONBOARD REGULATORS USED, SUPPLIES SHOULD NOMINAL. TEMPERATURE SHOULD AMBIENT, UNLESS OTHERWISE NOTED. CUSTOMER SOFTWARE DOES SUPPORT TESTING. APPROPRIATE REVS EVALUATION BOARD PARTS NOTED.
05941-028
AN-835
POWER SUPPLY REJECTION RATIO (PSRR,
Power supply rejection ratio (PSRR) measurement amount signal power supply that coupled digital output ADC. PSRR measured changing power supply then measuring change offset converter, expressed percentage full scale. More typically, PSRR measured injecting signal known amplitude power supply pins then measuring observed spectrum FFT. PSRR difference between values measured volts minus input value measured oscilloscope, expressed decibels.
WENZEL XTAL ROHDE SCHWARZ AGILENT
DIFFERENTIAL SINGLE-ENDED
ENCODE INPUT SUPPLY INPUT
ANALOG INPUT ADC-FIFO BOARD
TEKTRONIX 854C 500MHz OSCILLOSCOPE
AD92xx, AD94xx, AD66xx EVALUATION BOARD
SUPPLY INPUT
SIGNAL GENERATOR HP33120A
ANALOG OUTPUT
100µF, 1000µF, 3300µF NONPOLARIZED
STANDARDIZED SUPPLIES
SUPPLIES
1mH, 10mH, 100mH MONITOR
Figure PSRR Test Setup
Rev. Page
05941-030
NOTES BYPASS CAPACITORS FERRITE BEADS SHOULD REMOVED FROM EVALUATION BOARD. ENCODE SETTING SHOULD ADJUSTED SPECIFIED RATE. VALUE RELATED SOURCE IMPEDANCE POWER SUPPLIES. SIGNAL MEASURED OSCILLOSCOPE COMPARED OUTPUT DETERMINE PSRR. TEKTRONIX PROBES M/N: P6243 BETTER SHOULD USED. <1pF WITH 1GHz
AN-835 REFERENCES
Additional information data converter characterization found Data Conversion Handbook Walt Kester, Newness, ISBN 0-7506-7841-0. Additional reference books, including High Speed Design Techniques, Practical Analog Design Techniques, Linear Design Seminar, System Applications Guide, found ADI's website. addition many reference books, various applications notes, articles, reprints available from your Analog Devices sales representative, visit website www.analog.com additional information.
Rev. Page
AN-835 NOTES
©2006 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. AN05941-0-4/06(0)
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