Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Po

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Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Po

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High-performance, Low-power secure AVR® Enhanced RISC Architecture
Powerful Instructions (Most Executed Single Clock Cycle) Power Idle Power-down Modes Bond Locations Conforming 7816-2 Protection 6000V Operating Ranges: 1.62V 5.5V Compliant with GSM, 3GPP 2000 Specifications; Industry Compatible Available Wafers, Modules, Industry-standard Packages
Memory
320K Bytes Program Memory 288K Bytes EEPROM, Including Bytes 384-byte Bit-addressable Area
128-byte Program Erase Program Erase Typically More than 500,000 Write/Erase Cycles Temperature Years Data Retention EEPROM Erase Only Mode Write EEPROM With Without Autoerase Bytes Bytes Dedicated Atmel's Crypto-library
Secure Microcontroller Smart Cards AT90SC 320288RCT Summary
Peripherals
Ports
Configurable Support Communication Protocols, Including ISO7816-3 2-wire protocols ISO7816 Controller kbps Compliant with Protocols Serial Peripheral Interface (SPI) Contoller MHz) Programmable Internal Oscillator Cryptographic Accelerator 16-bit Timers Random Number Generator (RNG) 2-level, 8-vector Interrupt Controller 32-bit Cryptographic Accelerator Public Operations Including RSA, DSA, ECC, Diffie-Hellman Hardware Triple (DPA Resistant) Checksum Accelerator Engine (Compliant with ISO/IEC 3309)
Security
Dedicated Hardware Protection Against SPA/DPA Attacks Advanced Protection Against Physical Attack, Including Active Shield Environmental Protection Systems Voltage Monitor Frequency Monitor Light Protection Temperature Monitor Secure Memory Management/Access Protection (Supervisor Mode)
6507BS-SMIC-14Apr05
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Development Tools
Voyager Emulation Platform (ATV4 Standard) Support Software Development Embedded Workbench V3.20c Debugger Atmel's Studio Version 4.07 Above Software Libraries Application Notes
Description
AT90SC320288RCT low-power, high-performance, 8/16-bit microcontroller with program memory, EEPROM data memory, based secureAVR enhanced RISC architecture. executing powerful instructions single clock cycle, AT90SC320288RCT achieves throughputs close MIPS MHz. Harvard architecture includes general-purpose working registers directly connected ALU, allowing independent registers accessed single instruction executed clock cycle. ability EEPROM code space allows parts program memory reprogrammed in-system. This technology combined with versatile 8/16-bit monolithic chip provides highly flexible cost-effective solution many smart card applications. AT90SC320288RCT benefits advanced EEPROM functions Mode), also configured offer compatibility with previous product generations (e.g. AT90SC25672R AT90SC19236R). cryptographic accelerator, running with secureAVR core, featured AT90SC320288RCT series AdvXTM. based 32-bit multiplier-accumulator architecture which designed perform fast encryption authentication functions. This enables fast computation low-power operation. controlling firmware located either dedicated memory (Atmel's cryptolibrary supports standard finite field arithmetic functions including RSA, DSA, ECC) program memory (customer specific). Additional security features include power frequency protection logic, logical scrambling program data addresses, Power Analysis countermeasures memory accesses controlled supervisor mode. Figure shows AT90SC320288RCT block diagram.
AT90SC320288RCT
6507BS-SMIC-14Apr05
AT90SC320288RCT
Figure AT90SC320288RCT secureAVR Enhanced RISC Architecture
6507BS-SMIC-14Apr05
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6507BS-SMIC-14Apr05

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