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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Single-Chip Token-Ring Solution IBMToken-Ring NetworkCompatible Compatible With ISO/IEC IEEE 802.5:1992 Token-Ring Access-Method Physical-Layer Specifications Compatible With TI380FPA PacketBlasterGlueless Memory Interface Digital Phase-Locked Loop (PLL) Precise Control Bandwidths Improved Jitter Tolerance Minimizes Accumulated Phase Slope Phantom Drive Physical Insertion Onto Ring Differential Line Receiver With Level-Dependent Frequency Equalization Low-Impedance Differential Line Driver Ease Transmit-Filter Design On-Chip Watchdog Timer Internal Crystal Oscillator Reference-Clock Generation Expandable LAN-Subsystem Memory Bytes
32-Bit Host Address 80x8x 68xxx-Type Memory Organization Dual-Port Direct Memory Access (DMA) Direct Input/Output Transfers Host Supports 16-Bit Pseudo-Direct Memory Access (PDMA) Operation Electrostatic Discharge (ESD) Protection Exceeds (All Pins) 0.8-µm CMOS Technology Token-Ring Features 4-Megabit-Per-Second (Mbit/s) Data Rates Supports 18K-Byte Frame Size Mbit/s Only) Supports Universal Local Addressing Early Token-Release Option Mbit/s Only) Built-In Real-Time Error Detection Automatic Frame-Buffer Management 2-MHz 33-MHz System-Bus Clock Slow-Clock Low-Power Mode 176-Pin Thin Quad Flat Package
Subsystem Attached System MHz)
Transmit TI380C30A Receive Memory Network
Figure Network-Commprocessor Applications Diagram
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. Intel trademark Intel Corporation. Token-Ring Network trademarks International Business Machines Corporation. Motorola trademark Motorola, Inc. PacketBlaster trademarks Texas Instruments Incorporated. PAL® registered trademark Advanced Micro Devices, Inc. Other companies also manufacture programmable array logic devices.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1998, Texas Instruments Incorporated
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Table Abbreviations Acronyms
ARI/FCI EACO Mbit/s Mbit/s MIPS MOSFET PDMA SIFACL Accumulated Phase Slope Adapter-Support Function Address-Recognize Indicator/Frame-Copied Indicator Burn-In Address Copy Frames Clock Generator Communications Processor Central Processing Unit Cyclic Redundancy Check Direct Input/Output Direct Memory Access Electrostatic Discharge Enhanced-Address-Copy Option Logical Link Control Least Significant Media-Access Control Megabits Second Megabytes Second Memory Interface Million Instructions Second Metal Oxide Semiconductor Field-Effect Transistor Most Significant Pseudo-Direct Memory Access Protocol Handler Physical-Layer Interface Phase-Locked Loop System Interface Adapter Control Register Software Trunk-Coupling Unit Upstream Neighbor Address
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
PACKAGE (TOP VIEW)
MBIAEN MRESET MBCLK2 MBCLK1 OSCOUT NSELOUT1 WRAP DRVR+ DRVR WFLT PXTAL RCVR RCLK SSC1 RATER NABL PWRDN VSSL1 SSA1 RCV+ DDA1 RCV- DDL1 XMT- XMT+ PHOUTB PHOUTA SSL1 DDL1
MREF MACS MROMEN OSC32 OSCIN TCLK TRST VSSC SYNCIN VDDL MDDIR MAX0 MAX2 MCAS MRAS VSSC VSSL MBEN MADH7 MADH6 MADH5 MADH4 MADH3 MADH2 MADH1 MADH0 MAXPH MBRQ MBGR MAXPL MADL7 MADL6 MADL5 MADL4 MADL3
VSSO VDDA2 ATEST VSSA2 IREF VSSA3 REDY VDDA3 FRAQ NSRT VSSL XMATCH XFAIL TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 VSSC SADH6 SADH7 SRD/SUDS SRDY/SDTACK SOWN SDBEN SBHE/SRNW SHRQ/SBRQ SADL0 SADL1 SADL2
internal connection
MADL2 MADL1 MADL0 EXTINT3 EXTINT2 EXTINT1 EXTINT0 CLKDIV NSELOUT0 PRTYEN BTSTRP SIACK SRESET SRS1 SRS0 SRSX SBRLS SBBSY SHALT SRS2 SBERR SINTR SIRQ SHLDA SBGR SDDIR SRAS SLDS SXAL SALE SBCLK SADL7 SADL6 SADL5 SADL4 SADL3
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
description
TI380C30A single-chip token-ring solution, combining commprocessor physical-layer (PHY) interface onto single device. TI380C30A supports Mbit/s Mbit/s operation, conforms 8802-5/IEEE 802.5-1992 standards, been verified completely Token-Ring Network compatible. TI380C30A provides high degree integration combines functions TI380C25 TI380C60A onto single chip. Additional information section found TI380C60A data sheet, literature number SPWS033. With TI380C30A, only local memory minimal additional components such PAL® devices crystal oscillators need added complete LAN-subsystem design. TI380C30A provides 32-bit system-memory address reach with high-speed bus-master direct memory access (DMA) interface that supports rapid communications with host system. addition, TI380C30A supports direct low-cost 8-bit 16-bit pseudo-DMA interface that requires only chip-select work directly 80x8x 8-bit slave interface. Selectable 80x8x 68xxx-type host-system memory organization design flexibility. TI380C30A supports addressing bytes local memory. This expanded memory capacity improve LAN-subsystem performance minimizing frequency host LAN-subsystem communications allowing larger blocks information transferred time. support large local memory important applications that require large data transfers (such graphics database transfers) heavily loaded networks where extra memory provide data buffers store data until processed host. proprietary central processing unit (CPU) used TI380C30A allows protocol software downloaded into stored local-memory space. moving protocols [such logical link control (LLC)] LAN-subsystem, overall system performance increased. This accomplished offloading processing from host-system TI380C30A, which also reduce LAN-subsystem-to-host communications. other protocol software developed, greater differentiation products with enhanced system performance possible. TI380C30A includes hardware counters that provide real-time error detection automatic frame-buffer management. These counters control system-bus retries burst size, track host- LAN-subsystem-buffer status. Previously, these counters were maintained software. integrating them into hardware, software overhead reduced LAN-subsystem performance improved. TI380C30A implements Texas Instruments (TITM)-patented enhanced-address-copy-option (EACO) interface. This interface supports external address-checking devices, such TMS380SRA source-routing accelerator. TI380C30A 128-word external space memory support external address-checker devices other hardware extensions TMS380 architecture. PHY, Manchester-encoded data stream received phase-aligned using on-chip dual-digital phase-locked loop (PLL). Both recovered clock data passed protocol-handling circuits TI380C30A serial-to-parallel conversion data processing. transmit, TI380C30A buffers output from protocol-handling circuit drives media suitable isolation waveform-shaping components. TI380C30A uses CMOS technology reduce power consumption PCMCIA-compatible levels. Power-management features incorporated support Green compatibility. addition PLL, other functions required interface IEEE 802.5 token ring provided. These functions include phantom drive control relays within trunk-coupling unit wire-fault detection circuits; internal-wrap function self-test; watchdog timer provide fail-safe deinsertion from ring event station, microcode, commprocessor failure.
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
description (continued)
major blocks TI380C30A include communications processor (CP), system interface (SIF), memory interface (MIF), protocol handler (PH), clock generator (CG), adapter-support function (ASF), PHY, shown functional block diagram.
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
functional block diagram
SADH0 SADH7 SADL0 SADL7 SBRLS SINTR/SIRQ SDDIR SDBEN SALE SXAL SOWN SIACK SBCLK SRD/SUDS SWR/SLDS SRDY/SDTACK SI/M SHLDA/SBGR SBHE/SRNW SRAS/SAS S8/SHALT SRESET SRS0 SRS1 SRS2/SBERR SRSX SHRQ/SBRQ SBBSY BTSTRP PRTYEN NSELOUT0 NSELOUT1 Control Control Control DRAM Refresh Local-Bus Arbitrator Local-Bus Control Local Parity-Check/ Generator MADH0 MADH7 MADL0 MADL7 MRAS MCAS MAXPH MAXPL MDDIR MAX0 MAX2 MRESET MROMEN MBEN MBRQ MBGR MACS MBIAEN MREF OSCIN OSCOUT MBCLK1 MBCLK2 SYNCIN CLKDIV EXTINT0 Interrupts Test Function EXTINT3 TEST0 TEST5 XMATCH XFAIL FRAQ NSRT WRAP DRVR+ DRVR- XMT+ XMT- RCV+ RCV- PWRDN S4/16 NABL RATER
Communications Processor
Token-Ring RCLK REDY WFLT RCVR PXTAL OSC32 TCLK TRST ATEST PHOUTA PHOUTB Signals provided test-monitoring purposes.
Interface Test Port
Analog Signal
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Terminal Functions
TERMINAL NAME ATEST I/O/E DESCRIPTION Analog test. ATEST must left unconnected. Bootstrap. value BTSTRP loaded into BOOT SIFACL register reset (that when SRESET asserted ARESET SIFACL register set) form default value. BTSTRP indicates whether chapters memory ROM. these chapters RAM, TI380C30A denied access local-memory until CPHALT SIFACL register cleared. Chapters local memory based (see Note Chapters local memory based. Clock divider select (see Note CLKDIV DRVR+ DRVR- EXTINT0 EXTINT1 EXTINT2 EXTINT3 FRAQ 64-MHz OSCIN 4-MHz local 32-MHz OSCIN 4-MHz local 48-MHz OSCIN 6-MHz local Differential-driver data outputs (reserved) Equalization/gain points. Connections allow frequency tuning equalization circuit.
BTSTRP
Reserved. EXTINT0-EXTINT3 must pulled high (see Note
resolved
Frequency-acquisition control Clock recovery initialized Normal operation Internal reference. IREF allows internal bias current analog circuitry external resistor. Reserved. MACS must tied (see Note Local-memory address, data, status high byte. first quarter local-memory cycle, these lines carry address bits A0-A6; second quarter, they carry status bits; third fourth quarters, they carry data bits D0-D7. most significant MADH0 least significant MADH7. AX4, A0-A6 Memory Cycle Status D0-D7 D0-D7
IREF MACS MADH0 MADH1 MADH2 MADH3 MADH4 MADH5 MADH6 MADH7 MADL0 MADL1 MADL2 MADL3 MADL4 MADL5 MADL6 MADL7
Signal
Local-memory address, data, status byte. first quarter local-memory cycle, these lines carry address bits A7-A14; second quarter, they carry address bits A0-A6; third fourth quarters, they carry data bits D8-D15. most significant MADL0 least significant MADL7. A7-A14 Memory Cycle AX4, A0-A6 D8-D15 D8-D15
Signal
Memory-address latch. strobe signal sampling address start memory cycle; used SRAMs EPROMs. full 20-bit word address valid MAX0, MAXPH, MAX2, MAXPL, MADH0-MADH7, MADL0-MADL7. Three 8-bit transparent latches used retain 20-bit static address throughout cycle. Rising edge signal latching Falling edge Allows above address signals latched
input, output, provides external-component connection internal circuitry tuning NOTES: Terminal internal pullup device maintain high-voltage level when left unconnected etch). TMS380SRA supported only with 4-MHz local either CLKDIV state. Each terminal must tied individually with pullup resistor. Terminal should connected ground.
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Terminal Functions (Continued)
TERMINAL NAME I/O/E DESCRIPTION Local-memory extended-address bit. MAX0 drives row-address time column-address data-valid times cycles. MAX0 latched MRAS. Driving eases interfacing burn-in address (BIA) ROM. Memory Cycle
MAX0
Signal
MAX2
Local-memory extended-address bit. MAX2 drives row-address time, which latched MRAS, column-address data-valid times cycles. Driving eases interfacing ROM. Memory Cycle
Signal
MAXPH
Local-memory extended address parity high byte. first quarter memory cycle, MAXPH carries extended-address AX1; second quarter memory cycle, MAXPH carries extended-address AX0; last half memory cycle, MAXPH carries parity high data byte. Memory Cycle Parity Parity
Signal
MAXPL
Local-memory extended address parity byte. first quarter memory cycle, MAXPL carries extended-address AX3; second quarter memory cycle, MAXPL carries extended-address AX2; last half memory cycle, MAXPL carries parity data byte. Memory Cycle Parity Parity
Signal
Local-bus clock local-bus clock MBCLK1 MBCLK2 referenced local-bus transfers. MBCLK2 lags MBCLK1 quarter cycle. MBCLK1 MBCLK2 operate according MBCLK1 MBCLK2 MBCLK1- MBCLK2 OSCIN CLKDIV (4-MHz local bus) (4-MHz local bus) (6-MHz local bus)
MBEN
Buffer enable. MBEN enables bidirectional buffer outputs MADH, MAXPH, MAXPL, MADL buses during data phase. MBEN used with MDDIR, which selects buffer-output direction. Buffer output disabled Buffer output enabled Reserved. MBGR must left unconnected. Burned-in address enable. MBIAEN output signal used provide output enable containing adapter's BIA.
MBGR
MBIAEN
MBIAEN driven high write accesses addresses between >00.0000 >00.000F, accesses (read/write) other address. MBIAEN driven read from addresses between >00.0000 >00.000F.
MBRQ Reserved. MBRQ must pulled high (see Note input, output, provides external-component connection internal circuitry tuning NOTE Each terminal must tied individually with pullup resistor.
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Terminal Functions (Continued)
TERMINAL NAME I/O/E DESCRIPTION Column-address strobe DRAMs. column address valid 3/16ths memory cycle following row-address portion cycle. MCAS driven every memory cycle while column address valid MADL0-MADL7, MAXPH, MAXPL, except when following conditions occurs: MCAS When address accessed (>00.0000->00.000F) When address accessed EPROM memory (that when BOOT SIFACL register access made between >00.0010 >00.FFFF >1F.0000 >1F.FFFF) When cycle refresh cycle, which case MCAS driven start cycle before MRAS [for DRAMs that have CAS-before-RAS refresh]. DRAMs that support CAS-before-RAS refresh, necessary disable MCAS with MREF during refresh cycle. Data direction. MDDIR used direction control bidirectional drivers. MDDIR becomes valid before MBEN becomes active. TI380C30A memory-bus write TI380C30A memory-bus read Memory-output enable. enables outputs DRAM memory during read cycle. high EPROM read cycles. Disable DRAM outputs Enable DRAM outputs Row-address strobe DRAMs. address lasts first 5/16ths memory cycle. MRAS driven every memory cycle while address valid MADL0-MADL7, MAXPH, MAXPL both cycles. MRAS also driven during refresh cycles when refresh address valid MADL0-MADL7. DRAM refresh cycle progress. MREF indicates that DRAM refresh cycle occurring. also used disabling MCAS DRAMs that CAS-before-RAS refresh. DRAM refresh cycle process DRAM refresh cycle Memory-bus reset. MRESET reset signal generated when either ARESET SIFACL register SRESET asserted. MRESET used resetting external local-bus glue logic. External logic reset External logic reset enable. During first 5/16ths memory cycle, MROMEN used provide chip select ROMs when BOOT SIFACL (that when code resident ROM, RAM). MROMEN latched MAL. MROMEN goes read from addresses >00.0010->00.FFFF >1F.0000->1F.FFFF when BOOT SIFACL register MROMEN stays high writes these addresses, accesses other addresses, accesses address when BOOT During final three-fourths memory cycle, MROMEN outputs address signal interfacing ROM. This means MBIAEN, MAX0, MROMEN, MAX2 form glueless interface ROM. disabled enabled Local-memory write. used specify write cycle local-memory bus. data MADH MADL buses valid while low. DRAMs latch data falling edge while SRAMs latch data rising edge local-memory write cycle Local-memory write cycle NABL Output-enable control. NABL used physical-layer circuitry (see Note These pins must left unconnected.
MDDIR
MRAS
MREF
MRESET
MROMEN
Nonmaskable interrupt request. must left unconnected. input, output, provides external-component connection internal circuitry tuning NOTE Terminal internal pullup device maintain high-voltage level when left unconnected etch).
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Terminal Functions (Continued)
TERMINAL NAME I/O/E DESCRIPTION Network selection outputs. NSELOUT0 NSELOUT1 controlled host through corresponding bits SIFACL register. value NSELOUT0 NSELOUT1 changed only while TI380C30A reset. NSELOUT0 NSELOUT1 Description 16-Mbit/s token ring 4-Mbit/s token ring
NSELOUT0 NSELOUT1
Insert control. NSRT enables phantom-driver outputs (PHOUTA PHOUTB) through watchdog timer insertion onto token ring. NSRT Static high Inactive, phantom current removed (due watchdog timer) Static Inactive, phantom current removed (due watchdog timer) Falling edge Active, current output PHOUTA PHOUTB Oscillator output. OSC32 provides 32-MHz clock output used drive OSCIN other load. External oscillator input. OSCIN provides clock frequency TI380C30A 4-MHz 6-MHz internal (see Notes OSCIN CLKDIV CLKDIV PHOUTA PHOUTB OSCIN 4-MHz local 4-MHz local 6-MHz local OSCOUT OSCIN OSCIN
OSC32
Oscillator output OSCOUT OSCIN MHz, OSCOUT MHz) OSCIN MHz, OSCOUT MHz) OSCIN MHz, OSCOUT MHz)
Phantom-driver outputs PHOUTA PHOUTB cause insertion onto token ring. PHOUTA PHOUTB should connected center transmit transformer secondary winding phantom-drive generation. Parity enable. value PRTYEN loaded into SIFACL register reset (that when SRESET asserted ARESET SIFACL register set) form default value. PRTYEN enables parity checking local memory. Local-memory data checked parity (see Note Local-memory data checked parity. Power-down control (see Note Normal operation TI380C30A physical-layer circuitry placed into power-down state. outputs physical layer driven high-impedance state. Reference-clock output. PXTAL synthesized from 8-MHz crystal oscillator used XT2. Mbit/s, 32-MHz clock; Mbit/s, 8-MHz clock (see Note RATER indicates that there transitions RCV+/RCV- input pair (DRVR+/DRVR- WRAP asserted low) that transition rate consistent with ring speed selected S4/16 pin. Recovered clock. RCLK clock recovered from token-ring received data. 16-Mbit/s operation, 32-MHz clock. 4-Mbit/s operation, 8-MHz clock. Receiver. RCV+ RCV- differential inputs that receive token-ring data isolation transformers.
PRTYEN
PWRDN
PXTAL RATER RCLK RCV+ RCV-
RCVR Recovered data. RCVR contains data recovered from token ring. input, output, provides external-component connection internal circuitry tuning NOTES: Terminal internal pullup device maintain high-voltage level when left unconnected etch). Terminal expanded input voltage specification. maximum TI380C30A devices connected oscillator. Terminal should tied with 4.7-k pullup resistor. failure occur rising edge PXTAL occurs after rising edge OSCIN. problem only, does affect normal operation.
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Terminal Functions (Continued)
TERMINAL NAME I/O/E DESCRIPTION ready. REDY normally asserted (active) low. cleared following assertion FRAQ reasserted after data recovery been reinitialized. REDY Received data valid signal present) Received data valid signal loss indication lieu ring status (SSB_CMD 0X0001, ring_status signal loss indication. SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 SADH6 SADH7 SADL0 SADL1 SADL2 SADL3 SADL4 SADL5 SADL6 SADL7 SALE Reserved. should left unconnected. System address/data high byte (see Note These lines make most significant byte each address word (32-bit address bus) data word (16-bit data bus). most significant (MSB) SADH0, least significant (LSB) SADH7. Address multiplexing: Bits 31-24 bits 15-8 Data multiplexing: Bits 15-8
System address/data byte (see Note These lines make least significant byte each address word (32-bit address bus) data word (16-bit data bus). most significant SADL0, least significant SADL7. Address multiplexing: Bits 23-16 bits Data multiplexing: Bits System address-latch enable. SALE enable pulse used externally latch LSBs address from SADH SADL buses start cycle. Systems that implement address parity also externally latch parity bits (SPH SPL) latched address. System busy. TI380C30A samples value SBBSY during arbitration (see Note sample values: busy. TI380C30A become master grant condition met. Busy. TI380C30A cannot become master. System clock. TI380C30A requires external clock synchronize timings transfers. Valid frequencies MHz-33 MHz. Intelmode SBHE used system-byte-high enable. SBHE 3-state output driven during DMA; input other times. System byte high enabled (see Note System byte high enabled SRNW used system read, write. SRNW serves control signal indicate read write cycle. Read cycle (see Note Write cycle
SBBSY
SBCLK
SBHE/SRNW
Motorolamode
SBRLS
System-bus release. SBRLS indicates TI380C30A that higher-priority device requires system bus. value SBRLS ignored when TI380C30A performing DMA. SBRLS internally synchronized SBCLK. TI380C30A hold onto system (see Note TI380C30A should release system upon completion current cycle. transfer complete, rearbitrates system bus.
input, output, provides external-component connection internal circuitry tuning Typical ordering Inteland Motorolaprocessor buses NOTE Terminal internal pullup device maintain high-voltage level when left unconnected etch).
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Terminal Functions (Continued)
TERMINAL NAME I/O/E DESCRIPTION System-chip select. activates system interface TI380C30A read write. selected (see Note Selected System data-bus enable. SDBEN signals external data buffers begin driving data. SDBEN activated during both DMA. Keep external data buffers high-impedance state Cause external data buffers begin driving data System data direction. SDDIR provides external data buffers signal indicating direction which data moving. During writes reads, SDDIR (data direction into TI380C30A). During reads writes, SDDIR high (data direction from TI380C30A). When system interface involved operation, SDDIR high default. SDDIR Data Direction Output Input Read Write Write Read
SDBEN
SDDIR
Intel mode SHLDA/SBGR Motorola mode
SHLDA used system-hold acknowledge. SHLDA indicates that system DMA-hold request been acknowledged. SHLDA internally synchronized SBCLK (see Note Hold request acknowledged Hold request acknowledged SBGR used system grant. SBGR active-low grant, defined standard 68xxx interface, internally synchronized SBCLK (see Note System granted System granted SHRQ used system-hold request. SHRQ used request control system preparation transfer. SHRQ internally synchronized SBCLK. System requested System requested SBRQ used system-bus request. SBRQ used request control system preparation transfer. SBRQ internally synchronized SBCLK. System requested System requested
Intel mode SHRQ/SBRQ Motorola mode
SIACK
System-interrupt acknowledge. SIACK host processor acknowledge interrupt request from TI380C30A. System interrupt acknowledged (see Note System interrupt acknowledged: TI380C30A places interrupt vector onto system bus. System-Intel/Motorola mode select. value SI/M specifies system-interface mode. Intel-compatible-interface mode selected. Intel-interface mode (see S8/SHALT description Note Motorola-compatible-interface mode selected. Motorola-interface mode always bits. Intel mode SINTR used system-interrupt request. TI380C30A activates SINTR signal interrupt request host processor. Interrupt requested TI380C30A interrupt request SIRQ used system-interrupt request. TI380C30A activates SIRQ signal interrupt request host processor. interrupt request Interrupt requested TI380C30A
SI/M
SINTR/SIRQ
Motorola mode
input, output, provides external-component connection internal circuitry tuning NOTE Terminal internal pullup device maintain high-voltage level when left unconnected etch).
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Terminal Functions (Continued)
TERMINAL NAME I/O/E DESCRIPTION System owned. SOWN indicates external devices that TI380C30A control system bus. SOWN drives enable signal bus-transceiver chips that drive address bus-control signals. TI380C30A does have control system TI380C30A control system System parity high. optional odd-parity each address data byte transmitted over SADH0-SADH7 (see Note System parity low. optional odd-parity each address data byte transmitted over SADL0-SADL7 (see Note SRAS used system memory-address strobe (see Note SRAS used latch SRSX SRS2 register input signals. minimum-chip system, SRAS tied SALE output system bus. latching capability defeated since internal latch these inputs remains transparent long SRAS remains high. This permits SRAS pulled high signals SCS, SRSX SRS2, SBHE applied independently SALE strobe from system bus. During DMA, SRAS remains input. Transparent mode Holds latched values SCS, SRSX-SRS2, SBHE Falling edge Latches SCS, SRSX SRS2, SBHE used sytem-memory address strobe (see Note active-low address strobe that input during (although ignored address strobe) output during DMA. Address valid Address valid transfer operation progress used system-read strobe (see Note active-low strobe indicating that read cycle performed system bus. input during output during DMA. Read cycle occurring DMA, host provides data system bus. DIO, provides data system SUDS used upper-data strobe (see Note SUDS active-low upper-data strobe. SUDS input during output during DMA. valid data SADH0-SADH7 lines Valid data SADH0-SADH7 lines SRDY used system ready (see Note SRDY indicates master that data transfer complete. SRDY asynchronous, during pseudo-DMA cycles, internally synchronized SBCLK. During cycles, SRDY must asserted before falling edge SBCLK state order prevent wait state. SRDY output when TI380C30A selected DIO; otherwise, input. System ready Data transfer complete; system ready SDTACK used system data-transfer acknowledge (see Note purpose SDTACK indicate master that data transfer complete. SDTACK internally synchronized SBCLK. During cycles, SDTACK must asserted before falling edge SBCLK state order prevent wait state. SDTACK output when TI380C30A selected DIO; otherwise, input. System ready Data transfer complete; system ready input, output, provides external-component connection internal circuitry tuning NOTES: Terminal internal pullup device maintain high-voltage level when left unconnected etch).123456 Terminal should tied with 4.7-k pullup resistor.
SOWN
Intel mode SRAS/SAS
Motorola mode
Intel mode SRD/SUDS Motorola mode
Intel mode
SRDY/SDTACK
Motorola mode
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Terminal Functions (Continued)
TERMINAL NAME I/O/E DESCRIPTION System reset. SRESET activated place TI380C30A into known initial state. Hardware reset puts most TI380C30A outputs into high-impedance state places blocks into reset state. Intel-mode bus-width selection (S8) latched rising edge SRESET. system reset System reset Rising edge Latch width operations (for Intel-mode applications) SRSX SRS0-SRS2 used system-register select. These inputs select word byte transferred during system access. SRSX SRS2 (see Note Register selected SRSX SRS0 SRS1 SRS2/SBERR SRSX SRS0 SRS1 SRS2/SBERR
SRESET
Intel mode
Motorola mode
SRSX, SRS0, SRS1 used system-register select. These inputs select word byte transferred during system access. most significant SRSX least significant SRS1 (see Note Register selected SRSX SRS0 SRS1
SBERR used error. SBERR corresponds bus-error signal 68xxx microprocessor. internally synchronized SBCLK. SBERR driven during cycle indicate TI380C30A that cycle must terminated (see section 3.4.5.3 TMS380 Second-Generation Token-Ring User's Guide, literature number SPWU005, more information). used system-write strobe (see Note active-low write strobe that input during output during DMA. Write cycle occurring DMA, data driven from host bus. DIO, rising edge, data latched written selected register SLDS used lower-data strobe (see Note SLDS input during output during DMA. valid data SADL0-SADL7 lines Valid data SADL0-SADL7 lines
Intel mode SWR/SLDS Motorola mode
SXAL
System extended-address latch. SXAL provides enable pulse used externally latch most significant bits 32-bit system address during DMA. SXAL activated prior first cycle each block transfer, thereafter necessary (whenever increment address counter causes carry-out lower bits). Systems that implement parity addresses SXAL externally latch parity bits (available SPH) address extension. Reserved. SYNCIN must left unconnected (see Note Speed switch. S4/16 specifies token-ring data rate physical layer (see Note 4-Mbit/s data rate 16-Mbit/s data rate
SYNCIN S4/16
input, output, provides external-component connection internal circuitry tuning NOTES: Terminal internal pullup device maintain high-voltage level when left unconnected etch).123456 Terminal should tied with 4.7-k pullup resistor.
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Terminal Functions (Continued)
TERMINAL NAME I/O/E DESCRIPTION used system 8-/16-bit select. selects width used communications through system interface. rising edge SRESET, TI380C30A latches width; otherwise, value dynamically selects width. Selects 8-bit mode (see Note Selects 16-bit mode SHALT used system halt/bus error retry. SHALT asserted along with error (SBERR), adapter retries last cycle. This rerun operation defined 68xxx specification. BERETRY counter decremented SBERR when SHALT asserted (see section 3.4.5.3 TMS380 Second-Generation Token-Ring User's Guide, literature number SPWU005, more information).
Intel mode
S8/SHALT
Motorola mode
TCLK
(see Note (see Note (see Note
Test ports used during production test device. TCLK, TMS, TDI, must left unconnected. Network select inputs. TEST0-TEST2 used select network speed type used TI380C30A. These inputs should changed only during adapter reset. Connect TEST2 VDDL. TEST0 TEST1 TEST2 Description 16-Mbit/s token ring 4-Mbit/s token ring Reserved Test inputs. TEST3-TEST5 should left unconnected (see Note Module-in-place test mode achieved tying TEST3 TEST4 ground. this mode, TI380C30A outputs high-impedance state. Internal pullups TI380C30A inputs disabled (except TEST3-TEST5). Test-port reset. TRST should tied ground normal operation TI380C30A (see Note Reserved Test ports forced idle state
TEST0 TEST1 TEST2
TEST3 TEST4 TEST5
TRST
Positive-supply voltage commprocessor output buffers. pins must attached common-system power-supply plane.
VDDA1 VDDA2 VDDA3 VDDD VDDL VDDL1 VDDO VDDP
Positive-supply voltage receiver circuits Positive-supply voltage data recovery Positive-supply voltage current-bias generator Positive-supply voltage physical layer output buffers Positive-supply voltage commprocessor digital logic. VDDL pins must attached common-system power-supply plane. Positive-supply voltage physical layer digital logic. VDDL pins must attached common-system power-supply plane. Positive-supply voltage XTAL oscillator Positive-supply voltage phantom drive
VDDX Positive-supply voltage transmit output input, output, provides external-component connection internal circuitry tuning NOTE Terminal internal pullup device maintain high-voltage level when left unconnected etch).
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Terminal Functions (Continued)
TERMINAL NAME I/O/E DESCRIPTION
Ground connections commprocessor output buffers. pins must attached system ground plane.
VSSA1 VSSA2 VSSA3 VSSC VSSC1 VSSD VSSL
Ground reference receiver circuits Ground reference data-recovery Ground reference current-bias generator Ground reference commprocessor output buffers (clean ground). VSSC pins must attached common-system ground plane. Ground reference physical layer output buffers Ground reference physical layer output buffers
Ground reference digital logic. VSSL pins must attached common-system ground plane.
VSSL1 VSSO VSSP VSSX
Ground reference internal logic Ground reference XTAL oscillator Ground reference phantom drive Ground reference transmit output Phantom-wire fault. WFLT provides indication presence short open circuit PHOUTA PHOUTB. fault Open short. fault condition present phantom-drive lines. Internal wrap mode control. WRAP indicates TI380C30A placed physical layer loopback-wrap mode adapter self test. Normal ring operation Physical-layer wrap mode selected External fail-to-match signal. EACO device uses XFAIL indicate TI380C30A that should copy frame address-recognize indicator/frame-copied indicator (ARI/FCI) bits token-ring frame external address match.The ARI/FCI bits token-ring frame internal address-matched frame. EACO device used, XFAIL must left unconnected. XFAIL ignored when copy-all-frames (CAF) mode enabled [see table XMATCH description section (see Note 1)]. address match external address checker External address-checker-armed state External match signal. EACO device uses XMATCH indicate TI380C30A copy frame ARI/FCI bits token-ring frame. EACO device used, XMATCH must left unconnected. XMATCH ignored when mode enabled (see Note Address match recognized external address checker External address-checker-armed state
WFLT
WRAP
XFAIL
XMATCH
XMATCH Hi-Z
XFAIL Hi-Z
Function Armed (processing frame data) externally match frame (XFAIL takes precedence) Copy frame externally match frame (XFAIL takes precedence) Reset state (adapter initialized)
input, output, provides external-component connection internal circuitry tuning NOTE Terminal internal pullup device maintain high-voltage level when left unconnected etch).
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Terminal Functions (Continued)
TERMINAL NAME XMT+ XMT- I/O/E DESCRIPTION Transmit differential outputs. XMT+ XMT- provide low-impedance differential source line drive filtering transformer isolation. XTAL connection. 8-MHz crystal network connected here provide reference clock TI380C30A. Alternatively, 8-MHz clock source connected XT1.
input, output, provides external-component connection internal circuitry tuning
architecture
major blocks TI380C30A include SIF, MIF, ASF, PHY. functionality each block described following sections. communications processor (CP) performs control monitoring other functional blocks TI380C30A. control monitoring protocols specified software (downloaded ROM-based) local memory. Available protocols include:
Media access control (MAC) software Logical link control (LLC) software Copy frames (CAF) software
proprietary 16-bit central processing unit (CPU) with data cache single prefetch pipe pipelining instructions. These features enhance TI380C30A maximum performance capability about million instructions second (MIPS), with average about MIPS. system interface (SIF) performs interfacing subsystem host system. This interface require additional logic depending application. system interface transfer information/data using these three methods:
Direct memory access (DMA) Direct input/output (DIO) Pseudo-direct memory access (PDMA)
PDMA) used transfer data to/from host memory from/to local memory. main uses loading software local memory initializing TI380C30A. also allows command/status interrupts occur from TI380C30A. system interface hardware-selected either modes using SI/M. mode selected determines memory organizations control signals used. These modes are:
Intel mode (80x8x families): 16-, 32-bit devices Motorola mode (68xxx microprocessor family): 32-bit devices
system interface supports host-system memory addressing bits (32-bit reach into host system memory). This allows greater flexibility using/accessing host-system memory. System designers allowed customize system interface their particular
Programmable burst transfers cycle-steal operations Optional parity protection
These features implemented hardware reduce system overhead, facilitate automatic rearbitration after burst, repeat cycle when errors occur (parity bus). retries also supported.
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system interface (SIF) (continued) system-interface hardware also includes features enhance integrity TI380C30A operation data. These features include:
Always internally maintain odd-byte parity regardless parity being disabled Monitor presence clock failure Provide switchable speeds
every cycle, system interface compares system clocks reference clock. clocks becomes invalid, TI380C30A enters slow-clock mode, which prevents latch-up TI380C30A. SBCLK invalid, cycle terminated immediately; otherwise, cycle completed TI380C30A placed slow-clock mode. When TI380C30A enters slow-clock mode, clock that failed replaced slow free-running clock, device placed into low-power reset state. When failed clock(s) return valid operation, TI380C30A must reinitialized. with 16-MHz clock, continuous transfer rate MBps megabytes second (MBps)] obtained. with 25-MHz clock, continuous transfer rate Mbit/s MBps) obtained. with 33-MHz clock, continuous transfer rate Mbit/s MBps) obtained. 8-bit 16-bit pseudo-DMA, data rates Table obtained. Table Pseudo-DMA Data Rates
LOCAL SPEED 8-BIT PDMA Mbit/s Mbit/s 16-BIT PDMA Mbit/s Mbit/s
Since main purpose downloading initialization, transfer rate significant issue. memory interface (MIF) performs memory management allow TI380C30A address Mbytes local memory. Hardware allows TI380C30A connected directly DRAMs without additional circuitry. This glueless-DRAM connection includes DRAM-refresh controller. also handles internal arbitration between these blocks. When required, arbitrates external bus. responsible memory mapping task. memory maps DRAMs, EPROMs, burned-in addresses (BIAs), external devices addressed appropriately when required system interface, protocol handler, transfer. memory interface capable 64-Mbit/s continuous transfer rate when using 4-MHz local (64-MHz device crystal) 96-Mbit/s continuous transfer rate when using 6-MHz local bus. protocol handler (PH) performs hardware-based real-time protocol functions token-ring LAN. Network type determined TEST0-TEST2. token-ring network speed determined software either Mbit/s Mbit/s. These speeds fixed software, hardware. converts parallel-transmit data serial-network data appropriate coding converts received serial data parallel data. data-management state machines direct transmission/reception data to/from local memory through MIF. buffer-management state machines automatically oversee this process, directly sending/receiving linked lists frames without intervention.
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protocol handler (continued) contains many state machines that perform following functions:
Transmit receive frames Capture tokens Provide token-priority controls Manage TI380C30A buffer memory Provide frame-address recognition (group, specific, functional, multicast) Provide internal parity protection Control verify physical-layer circuitry-interface signals
Integrity transmitted received data controlled cyclic-redundancy checks (CRC), detection network-data violations, parity internal data paths. data paths registers optionally parity-protected maintain functional integrity. clock generator (CG) performs generation internal clocks required other functional blocks, including local memory-bus clocks (MBCLK1, MBCLK2). also generates reference timer used sample input clocks (SBCLK, OSCIN, RCLK, PXTAL). transition detected within period reference timer input clock signal, places TI380C30A into slow-clock mode. frequency reference timer range kHz-100 kHz. adapter-support function (ASF) performs support functions contained other blocks. features are:
TI380C30A base timer Identification, management, service internal external interrupts Test-pin mode control, including unit-in-place mode board testing Checks illegal states, such illegal opcodes parity
physical-layer interface (PHY) major blocks TI380C30A include receiver/equalizer, clock recovery PLL, wrap function, phantom drive with wire-fault detector, watchdog timer. Figure block diagram illustrating these major blocks, functionality each block described following sections.
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WRAP
External Equalizer
XTAL
S4/16
ATEST
FRAQ
NABL
RCV+ RCV- Receiver
PXTAL RCVR Receiver Clock Recovery RCLK OSC32 FRAQ REDY DRVR+ DRVR-
Data
XMT+ Transmit XMT- WFLT PHOUTA Phantom Drive PHOUTB Rate Error Watchdog Timer Test Port RATER NSRT (internal)
PWRDN
Bias
IREF
TCLK
TRST
Figure Functional Block Diagram
receiver
Figure shows arrangement line-receiver/equalizer circuit. differential-input pair, RCV+ RCV-, designed connected floating winding isolation transformer. Each equipped with bias circuit center operating point differential input approximately differential-input pair consists pair metal oxide semiconductor field effect transistors (MOSFETs), each with identical current source source terminal that supply nominal current signal levels, gain this pair inversely proportional impedance connected between their sources EQ+. frequency-equalization network connected between provide equalization media-signal distortion. internal-wrap mode provided self-test device. When selected taking WRAP low, normal input path disabled multiplexer path enabled from DRVR+/DRVR- input pair. Receiver gain, thresholds, equalization unchanged internal-wrap mode.
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LOAD
LOAD
RCV+ Bias Network RCV- WRAP DATA External Equalizer
DATA
WRAP IEQB From DRVR+/DRVR-
IEQB
Figure Line Receiver/Equalizer
receiver-clock recovery
clock data recovery TI380C30A performed advanced, digitally controlled PLL. contrast TMS38054, TI380C30A digitally controlled loop parameters internally programmed digital constants. This results precise control loop parameters requires external loop-filter components. TI380C30A implements intelligent algorithm determine optimum phase position data sampling extracted-clock synthesis. resulting action TI380C30A modeled cascaded PLLs shown Figure
RCLK Data PLL1 PLL2 RCVR
f3dB (see Note
f3dB (see Note
NOTE f3dB 3-dB bandwidth
Figure Dual-PLL Arrangement
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receiver-clock recovery (continued)
PLL1 represents algorithm recover data from incoming stream detected receiver. relatively high bandwidth provide good jitter tolerance. Data embedded-clock-phase information digital values PLL2, which generates extracted clock (RCLK) commprocessor. recovered data sent commprocessor RCVR signal synchronization with RCLK. addition sampling RCVR signal, commprocessor uses RCLK retransmit data most cases. lower bandwidth PLL2 greatly reduces rate accumulation data-correlated phase jitter token-ring network provides very good accumulated-phase-slope (APS) characteristics. addition RCLK, token-ring reference clock (PXTAL) fixed-frequency 32-MHz clock (OSC32) also synthesized from 8-MHz crystal reference.
line driver wrap function
line-drive function TI380C30A performed XMT+/XMT-. Unlike TMS38054, these pins low-impedance outputs require external-series resistance provide line termination. These pins provide buffering differential signal from DRVR+/DRVR- with action control skew asymmetry, with retiming transmit path. wrap function designed provide signal path system self-test diagnostics. When drives WRAP low, receiver inputs ignored transmit signal receiver input circuitry multiplexer. internal wrap mode, WRAP checked observing signal amplitude equalization pins, EQ-. Equalization active this signal level, although signal does exhibit high-frequency attenuation effects which equalization intended compensate. During wrap mode, both XMT+/XMT- driven state prevent current from flowing into isolation transformer.
phantom driver wire-fault detection
phantom-drive circuit under control NSRT generates voltage both phantom-drive outputs, PHOUTA PHOUTB. maintain phantom drive, NSRT toggled TI380C30A least once every watchdog timer included TI380C30A remove phantom drive NSRT does have required transitions. watchdog timer normally allowed expire because being reinitialized least every there problem TI380C30A microcode, resulting failure toggle NSRT, timer expires maximum this happens, phantom drive deasserted remains until next falling edge NSRT. watchdog timer requires external-timing components. When phantom drive deasserted, phantom-drive lines actively pulled low, reaching level less within voltage from PHOUTA PHOUTB superimposed transmit-signal pair trunk-coupling unit (TCU) request that station inserted into ring. This achieved connecting transmit-signal pair center secondary winding transmit-isolation transformer. Since PHOUTA PHOUTB connected media side isolation transformer, they require extensive protection against line surges. capacitor connected between phantom lines provide path transmit signal, while PHOUTA PHOUTB independently drive voltage each transmit lines, allowing independent wire-fault detection each. phantom voltage detected TCU, causing external wrap path from transmitter outputs back receiver inputs broken ring broken. signal connection established from ring receiver inputs from transmitter outputs ring. return current from dc-phantom voltage transmit pair returned station receive pair. This provides some measure wire-fault detection receive lines. phantom-drive outputs current limited prevent damage short-circuited. They detect either abnormally high abnormally load current either output corresponding short open circuit ring wiring. Either type fault results wire-fault indicator output (WFLT) being driven low. logic state WFLT high when phantom drive active.
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frequency acquisition REDY
Unlike predecessors, TMS3805x family, data-recovery TI380C30A physical layer does require constant frequency monitoring; neither necessary recenter frequency FRAQ control line. When commprocessor asserts FRAQ, initiates reset clock-recovery PLL. REDY signal deasserted duration this action reasserted when complete maximum later). This low-going transition REDY required commprocessor following setting FRAQ high indicate that frequency error that could have detected been corrected. REDY asserted incoming transitions detected rate-error function.
rate error (RATER) function
RATER provides indication that incoming data transitions present RCV+/RCV- pair, that rate transitions outside range that expected ring speed selected S4/16. RATER asserted incoming transitions present. wrap mode, rate-error function monitors transitions DRVR+/DRVR- pair. rate-error function interprets more transitions 1.5-ms period valid 16-Mbit/s data. interprets fewer transitions 1.5-ms period 4-Mbit/s data. transition less 1.5-ms period interpreted incoming transitions, which case, RATER REDY asserted low.
power-down control
TI380C30A disabled PWRDN signal. PWRDN taken low, outputs high-impedance state internal logic powered down, bringing power consumption very level. Upon taking PWRDN high, device resets initializes itself. This process could take care should taken ensure that system does require stable clocks during this period.
user-accessible hardware registers TI380C30A-internal pointers
Table Table show access internal data pointers address registers host interface. adapter-control (SIFACL) register, which directly controls device operation, described detail. adapter-internal pointers table defined only after TI380C30A initialization until OPEN command issued. These pointers defined TI380C30A software (microcode), this table describes release software.
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Table Adapter-Internal Pointers Token Ring
ADDRESS >00.FFF8 >00.FFFA >01.0A00 >01.0A02 DESCRIPTION Pointer software microcode level chapter Pointer starting location copyright notices. Copyright notices separated character terminated character chapter Pointer burned-in address chapter Pointer software level chapter Pointer TI380C30A addresses chapter Pointer node address Pointer group address Pointer functional address Pointer TI380C30A parameters chapter Pointer physical-drop number Pointer upstream neighbor address Pointer upstream physical-drop number Pointer last ring-poll address Pointer reserved Pointer transmit access priority Pointer source class authorization Pointer last attention code Pointer source address last received frame Pointer last beacon type Pointer last major vector Pointer ring status Pointer soft-error timer value Pointer ring-interface error counter Pointer local ring number Pointer monitor error code Pointer last beacon-transmit type Pointer last beacon-receive type Pointer last MAC-frame correlator Pointer last beaconing-station upstream neighbor address (UNA) Pointer reserved Pointer last beaconing-station physical-drop number Pointer buffer special buffer used software transmit adapter-generated frames) chapter Pointer counters chapter Pointer MAX_SAPs Pointer open SAPs Pointer MAX_STATIONs Pointer open stations Pointer available stations Pointer reserved Pointer 4-/16-Mbit/s word flag. zero, adapter Mbit/s. nonzero, adapter Mbit/s.
>01.0A04
>01.0A06
>01.0A08
>01.0A0A
>01.0A0C
>01.0A0E Pointer total TI380C30A found bytes allocation test chapter This table describes pointers release TI380C30A software. This address valid only microcode release
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Table User-Access Hardware Registers
80x8x 16-BIT MODE (SI/M S8/SHALT WORD TRANSFERS BYTE TRANSFERS SRSX SRS0 SRS1 SIFDAT SIFDAT/INC SIFADR SIFCMD SIFACL SIFADR SIFADX SIFDAT SIFDAT/INC SIFADR SIFSTS SIFACL SIFADR SIFADX DMALEN SDMADAT DMALEN SDMAADR SDMAADX SIFACL SIFADR SIFADX DMALEN SDMADAT DMALEN SDMAADR SDMAADX SIFACL SIFADR SIFADX DMALEN NORMAL MODE SBHE SRS2 SBHE SRS2 SBHE SRS2 PSEUDO-DMA MODE ACTIVE SBHE SRS2 SBHE SRS2 SBHE SRS2
DMALEN SBHE SRS2 defined.
80x8x 8-BIT MODE (SI/M S8/SHALT SRSX SRS0 SRS1 SRS2 NORMAL MODE SBHE SIFDAT SIFDAT SIFDAT SIFDAT SIFADR SIFADR SIFSTS SIFCMD SIFACL SIFACL SIFADR SIFADR SIFADX SIFADX DMALEN DMALEN PSEUDO-DMA MODE ACTIVE SBHE SDMADAT SDMADAT DMALEN DMALEN SDMAADR SDMAADR SDMAADX SDMAADX SIFACL SIFACL SIFACL SIFACL SIFADX SIFADX DMALEN DMALEN
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Table User-Access Hardware Registers (Continued)
68xxx MODE (SI/M WORD TRANSFERS BYTE TRANSFERS SRSX SRS0 SRS1 SIFDAT SIFDAT/INC SIFADR SIFCMD SIFACL SIFADR SIFADX SIFDAT SIFDAT/INC SIFADR SIFSTS SIFACL SIFADR SIFADX DMALEN SDMADAT DMALEN SDMAADR SDMAADX SIFACL SIFADR SIFADX DMALEN SDMADAT DMALEN SDMAADR SDMAADX SIFACL SIFADR SIFADX DMALEN NORMAL MODE SUDS SLDS SUDS SLDS SUDS SLDS PSEUDO-DMA MODE ACTIVE SUDS SLDS SUDS SLDS SUDS SLDS
DMALEN 68xxx mode always 16-bit mode.
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adapter-control (SIFACL) register SIFACL register allows host processor control, some extent, reconfigure TI380C30A under software control (see Table SIFACL Register
SWHLDA
SWDDIR
SWHRQ
PSDMAEN
ARESET
CPHALT
BOOT
SINTEN
NSEL OUT0
NSEL OUT1
Legend:
Read Write Write during ARESET only only Value after reset Value BTSTRP Value PRTYEN Indeterminate
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Table SIFACL Definitions
NAME FUNCTION Value TEST0 TEST2 pins. These bits read-only bits reflect value corresponding device pins. This allows host software (S/W) determine speed configuration. network speed type software-configurable, these bits used determine configurations that supported network hardware. TEST0 TEST1 TEST2 Description 16-Mbit/s token ring 4-Mbit/s token ring Reserved
TEST0 TEST1 TEST2
Reserved
Read data should Software-hold acknowledge. Allows function SHLDA/SBGR emulated from software control pseudo-DMA mode. PSDMAEN SWHLDA SWHRQ Result SWHLDA value SIFACL register cannot pseudo-DMA request pending Indicates pseudo-DMA request interrupt Pseudo-DMA process progress
SWHLDA
value SHLDA/SBGR ignored. Current SDDIR signal value. Contains current value pseudo-DMA direction. This enables host easily determine direction transfers, which allows system controlled system software. Pseudo from host system TI380C30A Pseudo from TI380C30A host system Current SHRQ signal value. Contains current value SHRQ/SBRQ when Intel mode inverse value SHRQ/SBRQ Motorola mode. This enables host easily determine pseudo-DMA transfer requested. Intel Mode (SI/M System requested System requested Motorola Mode (SI/M System requested System requested
SWDDIR
SWHRQ
Pseudo-system-DMA enable. Enables pseudo-DMA operation. PSDMAEN Normal bus-master operation possible. Pseudo-DMA operation selected. Operations dependent values SWHLDA SWHRQ bits SIFACL register. Adapter reset. ARESET hardware reset TI380C30A. This same effect SRESET except that interface SIFACL register maintained. This clock failure detected (OSCIN, PXTAL, RCLK, SBCLK valid). TI380C30A operates normally. TI380C30A held reset condition. Communications processor halt. Controls TI380C30A processor access internal TI380C30A buses. This prevents TI380C30A from executing instructions before microcode downloaded. TI380C30A processor access internal TI380C30A buses. TI380C30A processor cannot access internal-adapter buses. Bootstrap code. Indicates whether memory chapters local-memory space ROM/PROM/EPROM. This controls operation MCAS MROMEN. ROM/PROM/EPROM memory chapters memory chapters Local priority. Controls priority levels devices local bus. external devices (such TI380FPA) used with TI380C30A. external device (such TI380FPA) used with TI380C30A. This allows external master operate necessary priority local bus. system uses TMS380SRA only, must system uses both TMS380SRA TI380FPA, must
ARESET
CPHALT
BOOT
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Table SIFACL Definitions (Continued)
NAME FUNCTION System-interrupt enable. Allows host processor enable disable system-interrupt requests from TI380C30A. system-interrupt request from TI380C30A SINTR/SIRQ. following equation shows SINTR/SIRQ driven: SINTR/SIRQ (PSDMAEN SWHRQ !SWHLDA) (SINTEN SYSTEM_INTERRUPT) Results states are: System Interrupt (SIFTS SINTEN Register) Result Pseudo active. TI380C30A generates system interrupt pseudo DMA. pseudo-DMA interrupt TI380C30A generates system interrupt. TI380C30A does generate system interrupt. TI380C30A cannot generate system interrupt.
SINTEN
PSDMAEN
SWHRQ
SWHLDA
value SHLDA/SBGR ignored.
Parity enable. Determines whether data transfers within TI380C30A checked parity. Data transfers checked parity. Data transfers checked correct parity. Network-selection outputs. Values control NSELOUT0 NSELOUT1. These bits modified only while ARESET set. These bits used software-configure TI380C30A: NSELOUT0 should connected TEST0 (TEST1 should left unconnected TEST2 should tied high). NSELOUT0 NSELOUT1 used select network speed follows: 14-15 NSELOUT0 NSELOUT1 NSELOUT0 NSELOUT1 Selection Reserved 16-Mbit/s token ring Reserved 4-Mbit/s token ring
power these bits corresponding 16-Mbit/s token ring (NSELOUT1 NSELOUT0 values saved only written same cycle that ARESET cleared.
SIFACL control pseudo-DMA operation
Pseudo-DMA operation software-controlled using five bits SIFACL register. logic model SIFACL control pseudo-DMA operation shown Figure
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Motorola Mode Internal Signals Host Interface SINTR/SIRQ
SYSTEM_INTERRUPT (SIFSTS register)
Request
SHRQ/SBRQ
SHLDA/SBGR
Grant
DMADIR SWHLDA SWDDIR SWHRQ PSDMAEN SINTEN
SDDIR
SIFACL Register
Figure Pseudo-DMA Logic Related SIFACL Bits
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Supply voltage, (see Note -0.5 Input voltage range (see Note -0.5 Output voltage range -0.5 Power dissipation 1.25 Operating case temperature, 95°C Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE Voltage values with respect VSS, pins should routed minimize inductance system ground.
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recommended operating conditions
Supply voltage TTL-level signal High-level input voltage Low-level input voltage, TTL-level signal (see Note High-level output current Low-level output current (see Note Operating case temperature outputs outputs OSCIN RCLK, PXTAL, RCVR, 4.75 -0.3 5.25 VDD+0.3 VDD+0.3 VDD+0.3 -400 UNIT
NOTES: algebraic convention, where more-negative (less-positive) limit designated minimum, used logic-voltage levels only. Output current sufficient drive five low-power Schottky loads advanced low-power Schottky loads (worst case).
electrical characteristics over recommended ranges supply voltage operating case temperature (unless otherwise noted)
PARAMETER High-level output voltage, TTL-level signal (see Note Low-level output voltage, TTL-level signal High-impedance High impedance output current Input current, input input/output Supply current Input capacitance, input Output capacitance, output input/output Normal mode Power-down mode TEST CONDITIONS MIN, MIN, MAX, MAX, MHz, MHz, Others Others UNIT
conditions shown MIN/MAX, appropriate value specified under recommended operating conditions. NOTE following signals require external pullup resistor: SRAS/SAS, SRDY/SDTACK, SRD/SUDS, SWR/SLDS, EXTINT0-EXTINT3, MBRQ.
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electrical characteristics over recommended ranges supply voltage operating case temperature (unless otherwise noted) (continued)
receiver input (RCV+ RCV-)
PARAMETER Vr(CM) Vf(CM) Receiver-input bias voltage Rising-input threshold voltage Falling-input threshold voltage Asymmetry threshold voltage, (VT+ VT-)/2 Rising-input common-mode rejection [VT+ (@VSB (@VSB Falling-input common-mode rejection [VT+ (@VSB (@VSB Note VICM VSB, Rtst Notes Figure VICM VSB, Rtst Notes Figure VICM VSB, Rtst Notes Figure Notes Figure Notes Figure Both inputs VSB, Note Figure II(RCVR) Receiver input current Input under test Other input Notes Figure Rtst Input under test Other input Note IEQB Equalizer bias current RCV+ RCV- RCV+ RCV- Figure TEST CONDITIONS VSB-1 VSB+1 UNIT
VEQW Equalizer wrap voltage WRAP low, Figure NOTES: self-bias voltage input pair RCV+ RCV-. defined (VSB+ +VSB-) (where VSB+ self-bias voltage RCV+; VSB- self-bias voltage RCV-). self-bias voltage both pins approximately VDD÷2. VICM common-mode voltage applied RCV+ RCV-.
phantom driver (PHOUTA PHOUTB)
PARAMETER IOZH IOZL High level output voltage High-level Short-circuit output current Low-level output current Off-state output current with high-level voltage applied Off-state output current with low-level voltage applied TEST CONDITIONS -100 -100 UNIT
wire fault (WFLT) (see Notes
PARAMETER Phantom load resistance detected short circuit Phantom load resistance detected open circuit 0.15 UNIT
Phantom load resistance detected normal NOTES: wire-fault circuit recognizes fault condition phantom-drive load resistance ground greater than load resistance less than RLS. resistance range specified recognized wire fault. fault condition either PHOUTA PHOUTB results WFLT signal being asserted (low). Resistor (RLS, RLO, RLN) connected from output under test ground, other output loaded with ground.
characteristics
PARAMETER VFILT Reference operating filter voltage TEST CONDITIONS tc(XT1) UNIT
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electrical characteristics over recommended ranges supply voltage operating case temperature (unless otherwise noted) (continued)
crystal-oscillator characteristics
PARAMETER VSB(XT1) IOH(XT2) IOL(XT2) Input self-bias voltage Output high-level current Output low-level current V(XT2) VSB(XT1), V(XT2) VSB(XT1), V(XT1) VSB(XT1) V(XT1) VSB(XT1) TEST CONDITIONS -2.5 -6.5 UNIT
timing parameters
timing parameters signals TI380C30A shown following tables illustrated accompanying figures. purpose these figures tables quantify timing relationships among various signals. parameters numbered convenience. static signals Table lists signals that allowed change dynamically therefore have timing associated with them. They should strapped high, low, left unconnected required. Table Static Signals Functions
SIGNAL SI/M CLKDIV BTSTRP PRTYEN TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 FUNCTION Host-processor select (Intel/Motorola) Clock divider select Default-bootstrap mode (RAM/ROM) Default-parity select (enabled/disabled) Test indicates network type Test indicates network type Test manufacturing test Test manufacturing test Test manufacturing test
unit-in-place test
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
timing parameter symbology Some timing parameter symbols have been created accordance with JEDEC Standard 100-A. shorten symbols, some signal names other related terminology have been abbreviated DRVR DRVR OSCIN SRESET SBCLK VDDL, Cycle time Delay time Hold time Rise time Skew Setup time Transition time Pulse duration
Lower-case subscripts defined
following additional letters phrases defined Falling edge Rising edge High Valid High impedance longer high longer
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
PARAMETER MEASUREMENT INFORMATION
Outputs driven minimum high-logic level maximum low-logic level These levels compatible with devices. Output transition times specified follows: high-to-low transition either input output signal, level which signal said longer high level which signal said low-to-high transition, level which signal said longer level which signal said high shown below. rise fall times specified assumed those standard devices, which typically
(high) (low)
test measurement
test-load circuit shown Figure represents programmable load tester electronics that used verify timing parameters TI380C30A output signals.
Test Point VLOAD Output Under Test Test Point Test Point TTL-OUTPUT TEST LOAD XMT+ XMT- TEST LOAD XMT- XMT+
IEQB VLOAD VEQW
Iref TEST CIRCUIT Where: VLOAD typical dc-level verification typical timing verification
EQUALIZER TEST CIRCUIT
Figure Test Load Circuits
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
switching characteristics over recommended range supply voltage (unless otherwise noted)
transmitter drive characteristics (see Figures
PARAMETER VPP(XMT) XMT+/XMT- peak-to-peak XMT+/XMT peak peak voltage (see Note TEST CONDITIONS 4.75 5.25 10.3 UNIT
NOTE VPP(XMT) determined VOH(XMT+) VOH(XMT-) VOL(XMT+) VOL(XMT-)
transmitter switching characteristics (see Figures
PARAMETER XMT+/XMT skew (see Note XMT+/XMT- XMT+/XMT- XMT+/XMT asymmetry (see Note TEST CONDITIONS tsk(DRV) tsk(DRV) tsk(DRV) tsk(DRV) UNIT
NOTES: XMT+/XMT- skew determined td(XMT td(XMT td(XMT td(XMT XMT+/XMT- asymmetry determined d(XMT)L)
d(XMT
td(XMT)H) td(XMT*L)
DRVR+
0.45 0.45 tsk(DRV) tsk(DRV) VOH(XMT+) V50(XMT+) VOL(XMT+) VOH(XMT-) V50(XMT-) VOL(XMT-) td(XMT- td(XMT-
DRVR-
XMT+ td(XMT+L) XMT- td(XMT+H)
Figure Transmitter
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
clock data switching characteristics over recommended range supply voltage, tc(XT1) (see Figure
PARAMETER tc(XT1) tw(OSC32H) tw(OSC32L) tw(PXTALL) (PXTALL) tw(PXTALH) (PXTALH) tw(RCLKL) (RCLKL) tw(RCLKH) (RCLKH) tsu(RCVR) th(RCVR) Cycle time clock applied Pulse duration, OSC32 high Pulse duration, OSC32 Pulse duration, PXTAL duration Pulse duration, PXTAL high duration Pulse duration, RCLK duration Pulse duration RCLK high duration, Setup time, RCVR valid RCLK rising edge Hold time, RCVR valid after RCLK rising edge tw(PXTALH) tw(PXTALL) PXTAL tw(OSC32H) tw(OSC32L) OSC32 tw(RCLKH) tw(RCLKL) RCLK tsu(RCVR) th(RCVR) RCVR 16-Mbit/s mode 4-Mbit/s mode 16-Mbit/s mode 4-Mbit/s mode 16-Mbit/s mode 4-Mbit/s mode 16-Mbit/s mode 4-Mbit/s mode 16-Mbit/s mode 16-Mbit/s mode TEST CONDITIONS UNIT
Figure PXTAL, OSC32, RCLK, RCVR
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
timing power-up, SBCLK, OSCIN, MBCLK1, MBCLK2, SYNCIN, SRESET (see Figure
tr(VDD) td(VDDH-SCKV) td(VDDH-OSCV) tc(SCK) tw(SCKH) tw(SCKL) tt(SCK) tc(OSC) tw(OSCH) Rise time, minimum VDD-high level Delay time, minimum VDD-high level first valid SBCLK longer high Delay time, minimum VDD-high level first valid OSCIN high Cycle time, SBCLK (see Note Pulse duration, SBCLK high Pulse duration, SBCLK Transition time, SBCLK Cycle time, OSCIN (see Note OSCIN Pulse duration, OSCIN high (see Note OSCIN OSCIN OSCIN tw(OSCL) tt(OSC) td(OSCV-CKV) th(VDDH-RSL) tw(RSH) tw(RSL) tsu(RST) th(RST) Pulse duration, OSCIN (see Note Transition time, OSCIN Delay time, OSCIN valid MBCLK1 MBCLK2 valid Hold time, SRESET after reaches minimum high level Pulse duration, SRESET high Pulse duration, SRESET Setup time, size SRESET high (Intel mode only) Hold time, size from SRESET high (Intel mode only) CLKDIV One-eighth local-memory cycle CLKDIV 2tc(OSC) tc(OSC) OSCIN OSCIN 1/OSCIN 30.3 UNIT
This specification provided board design. parameter cannot met, parameter must extended larger difference: real value parameter minus value listed. NOTES: SBCLK value between MHz. This data sheet describes system interface (SIF) timing parameters cases SBCLK MHz. value OSCIN ±1%, OSCIN used generate PXTAL, OSCIN tolerance must ±0.01%. This maintains duty-cycle crystal, provided that OSCIN meets recommended operating conditions VIL.
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
Minimum VDD-High Level
SBCLK
OSCIN
MBCLK1
MBCLK2
SRESET
S8/SHALT
NOTE represent information illustration, nonactual phase timebase characteristics shown. Refer specified parameters precise information.
Figure Power-Up, System Clocks, SYNCIN, SRESET
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
memory-bus timing
cycle time one-eighth local-memory cycle (31.25 minimum 4-MHz local 20.83 minimum 6-MHz local bus). local-memory clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, address (see Figures
Period MBCLK1 MBCLK2 Pulse duration, MBCLK1/MBCLK2 high Pulse duration, MBCLK1/MBCLK2 Hold time, MBCLK2 after MBCLK1 high Hold time, MBCLK1 high after MBCLK2 high Hold time, MBCLK2 high after MBCLK1 Hold time, MBCLK1 after MBCLK2 Setup time, address/enable MAX0, MAX2, MROMEN before MBCLK1 longer high Setup time, address MADL0-MADL7, MAXPH, MAXPL before MBCLK1 longer high Setup time, address MADH0-MADH7 before MBCLK1 longer high Setup time, high before MBCLK1 longer high Setup time, address MAX0, MAX2, MROMEN before MBCLK1 longer Setup time, column address MADL0-MADL7, MAXPH, MAXPL before MBCLK1 longer Setup time, status MADH0-MADH7 before MBCLK1 longer Setup time, valid before MBCLK1 Hold time, valid after MBCLK1 Delay time, MBCLK1 longer MRESET valid Hold time, column address/status after MBCLK1 longer Reference OSCIN (when CLKDIV OSCIN (when CLKDIV Periods Periods Periods 2tM-9 2tM-9 tM-9 tM-9 tM-9 tM-9 tM-9 tM-14 tM-14 0.5tM-9 0.5tM-9 0.5tM-9 tM-7 Periods UNIT Periods
OSCOUT
MBCLK1
MBCLK2 MBCLK1 MBCLK2 have timing relationship OSCOUT. MBCLK1 MBCLK2 start OSCIN rising edge, depending when memory cycle starts execution.
Figure Clock Waveforms After Clock Stabilization
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
MBCLK1
MBCLK2 MAX0 MAX2 MROMEN MAXPH MAXPL MADL0-MADL7 ADD/EN MADH0-MADH7 Address
Address Status
Valid
MRESET
Figure Memory Local-Memory Clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, Address
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Valid
TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
memory-bus timing (continued)
cycle time one-eighth local-memory cycle (31.25 minimum 4-MHz local 20.83 minimum 6-MHz local bus). clocks, MRAS, MCAS, address (see Figure
Setup time, address MADL0-MADL7, MAXPH, MAXPL before MRAS longer high Hold time, address MADL0-MADL7, MAXPH, MAXPL after MRAS longer high Delay time, MRAS longer high MRAS longer high next memory cycle Pulse duration, MRAS Pulse duration, MRAS high Setup time, column address (MADL0-MADL7, MAXPH, MAXPL) status (MADH0-MADH7) before MCAS longer high Hold time, column address (MADL0-MADL7, MAXPH, MAXPL) status (MADH0-MADH7) after MCAS Hold time, column address (MADL0-MADL7, MAXPH, MAXPL) status (MADH0-MADH7) after MRAS longer high Pulse duration, MCAS Pulse duration, MCAS high, refresh cycle follows read write cycle Hold time, address MAXL0-MAXL7, MAXPH, MAXPL after Setup time, address MAXL0-MAXL7, MAXPH, MAXPL before longer high Pulse duration, high Setup time, address/enable MAX0, MAX2, MROMEN before longer high Hold time, address/enable MAX0, MAX2, MROMEN after Setup time, address MADH0-MADH7 before longer high Hold time, address MADH0-MADH7 after 1.5tM-11.5 tM-6.5 4.5tM-5 3.5tM-5 0.5tM-9 tM-5 2.5tM-6.5 3tM-9 2tM-9 1.5tM-9 tM-9 tM-9 tM-9 1.5tM-9 tM-9 1.5tM-9 UNIT
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
MAXPH MAXPL MADL0-MADL7
Column
Column
MRAS MCAS ADD/EN Address MADH0-MADH7 Address Status Address Status
MAX0 MAX2 MROMEN
Figure Memory Clocks, MRAS, MCAS, Address
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
memory-bus timing (continued)
cycle time one-eighth local-memory cycle (31.25 minimum 4-MHz local 20.83 minimum 6-MHz local bus). memory-bus read cycle (see Figure
Access time, address/enable valid MAX0, MAX2, MROMEN valid data/parity Access time, address valid MAXPH, MAXPL, MADH0-MADH7, MADL0-MADL7 valid data/parity Access time, MRAS valid data/parity Hold time, valid data/parity after MRAS longer Hold time, address high-impedance state MAXPH, MAXPL, MADH0-MADH7 MADL0-MADL7 after MRAS high (see Note Access time, MCAS valid data/parity Hold time, valid data/parity after MCAS longer Hold time, address high-impedance state MAXPH, MAXPL, MADH0-MADH7, MADL0-MADL7 after MCAS high (see Note Delay time, MCAS longer high Setup time, address/status high-impedance state MAXPH, MAXPL, MADL0-MADL7, MADH0-MADH7 before longer high Access time, valid data/parity Pulse duration, Delay time, MCAS longer Hold time, valid data/parity after longer Hold time, address high-impedance state MAXPH, MAXPL, MADH0-MADH7, MADL0-MADL7 after high (see Note Setup time, address/status high-impedance state MAXPH, MAXPL, MADL0-MADL7, MADH0-MADH7, before MBEN longer high Setup time, address/status high-impedance state MAXPH, MAXPL, MADL0-MADL7, MADH0-MADH7 before MBIAEN longer high Access time, MBEN valid data/parity Access time, MBIAEN valid data/parity Pulse duration, MBEN Pulse duration, MBIAEN Hold time, valid data/parity after MBEN longer Hold time, valid data/parity after MBIAEN longer Hold time, address high-impedance state MAXPH, MAXPL, MADH0-MADH7, MADL0-MADL7 after MBEN high (see Note Hold time, address high-impedance state MAXPH, MAXPL, MADH0-MADH7, MADL0-MADL7 after MBIAEN high Hold time, MDDIR high after MBEN high, read follows write cycle Setup time, MDDIR before MBEN longer high Hold time, MDDIR after MBEN high, write follows read cycle 2tM-9 2tM-9 2tM-15 2tM-15 1.5tM-12 3tM-5 2tM-9 3tM-9 2tM-15 2tM-25 2tM-25 2tM-20 2tM-13 tM+13 2tM-10.5 3tM-23 6tM-23 6tM-23 4.5tM-21.5 UNIT
3tM-12 NOTE data/parity that exists address lines most likely will reach high-impedance state some time later than rising edge MRAS, MCAS, MOE, MBEN (between timing parameter will function memory being read. time given represents time from rising edge MRAS, MCAS, MOE, MBEN beginning next address, does represent actual high-impedance period address bus.
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
MAX0 MAX2 MROMEN
Address/ Enable
Address Data/Parity
MAXPH, MAXPL MADH0-MADH7 MADL0-MADL7
Address
Address/ Status
Address
MRAS MCAS
MBIAEN
MBEN
MDDIR
Figure Memory-Bus Read Cycle
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
memory-bus timing (continued)
cycle time one-eighth local-memory cycle (31.25 minimum 4-MHz local 20.83 minimum 6-MHz local bus). memory-bus write cycle (see Figure
Setup time, before MRAS longer Setup time, before MCAS longer Setup time, valid data/parity before longer high Pulse duration, Hold time, data/parity valid after high Setup time, address valid MAX0, MAX2, MROMEN before longer Hold time, MRAS longer Hold time, MCAS longer Setup time, MBEN before longer high Hold time, MBEN after high Setup time, MDDIR high before MBEN longer high Hold time, MDDIR high after MBEN high 1.5tM-6.5 2.5tM-9 0.5tM-10.5 7tM-11.5 5.5tM-9 4tM-11.5 1.5tM-13.5 0.5tM-6.5 2tM-9 1.5tM-12 UNIT
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DALLAS, TEXAS 75265
TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
MAX0 MAX2 MROMEN MAXPH, MAXPL MADH0-MADH7 MADL0-MADL7
Address/ Enable
Address
Address
ADD/STS
Data/Parity
MRAS MCAS MBEN MDDIR
Figure Memory-Bus Write Cycle
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
memory-bus timing (continued)
cycle time one-eighth local-memory cycle (31.25 minimum 4-MHz local 20.83 minimum 6-MHz local bus). DRAM-refresh cycle (see Figure
Setup time, address MADL0-MADL7, MAXPH, MAXPL before MRAS longer high Hold time, address MADL0-MADL7, MAXPH, MAXPL after MRAS longer high Pulse duration, MRAS Pulse duration, MRAS high Setup time, MCAS before MRAS longer high Hold time, MCAS after MRAS Setup time, MREF high before MCAS longer high Hold time, MREF high after MCAS high 1.5tM-11.5 tM-6.5 4.5tM-5 3.5tM-5 1.5tM-11.5 4.5tM-6.5 tM-9 UNIT
MADL0-MADL7
Refresh Address
Address
MRAS MCAS MREF
Figure Memory-Bus DRAM-Refresh Cycle
XMATCH XFAIL timing (see Figure
cycle time one-eighth local-memory cycle (31.25 minimum 4-MHz local 20.83 minimum 6-MHz local bus).
Delay time, status high XMATCH XFAIL recognized Pulse duration, XMATCH XFAIL high duration 4-MHz local 6-MHz local UNIT
MADH7
Status
XMATCH XFAIL
Figure XMATCH XFAIL
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
token-ring timing
ring interface (see Figure
154L 154H 158L 158H Period RCLK (see Note Pulse duration, RCLK duration Pulse duration RCLK high duration, Mbit/s Mbit/s Mbit/s nominal: 62.5 Mbit/s nominal: 15.625 Mbit/s nominal: 62.5 Mbit/s nominal: 15.625 31.25 ±0.01 31.25 UNIT
Setup time, RCVR valid before rising edge (1.8 RCLK Mbit/s Hold time, RCVR valid after rising edge (1.8 RCLK Mbit/s Pulse duration, ring-baud clock duration ring baud Pulse duration, ring-baud clock high duration ring baud Period OSCOUT PXTAL (see Note Tolerance PXTAL input frequency (see Note Mbit/s Mbit/s Mbit/s Mbit/s Mbit/s Mbit/s (for PXTALIN only)
NOTE This parameter tested required IEEE 802.5 specification. 154H RCLK
154L RCVR Valid
158H
158L
OSCOUT PXTAL
Figure Ring Interface
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
transmitter timing (see Figure
tsk(DR) td(DR)H td(DR)L td(DRN)H t(DRN)L DRVR+/DRVR- asymmetry Delay time, DRVR+ rising edge (1.8 DRVR- falling edge DRVR+ falling edge DRVR- rising edge (1.8 Delay time, RCLK PXTAL) falling edge DRVR+ rising edge (1.8 Delay time, RCLK PXTAL) falling edge DRVR+ falling edge Delay time, RCLK PXTAL) falling edge DRVR- falling edge Delay time, RCLK PXTAL) falling edge DRVR- rising edge (1.8 d(DR)L Note Note Note Note ±1.5 UNIT
d(DRN)H
d(DR)H
d(DRN)L
When active-monitor mode, clock source PXTAL; otherwise, clock source either RCLK PXTAL. NOTE This parameter tested minimum maximum, measured used component required parameter 164. DRVR-
RCLK PXTAL
DRVR+
Figure Skew Asymmetry From RCLK PXTAL DRVR+ DRVR-
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
80x8x timing
80x8x read cycle (see Figure
261a 266a 272a 273a 282a 282R 283R Delay time, SRDY either high Pulse duration, SRAS high Hold time, high-impedance state after (see Note Setup time, SADH0-SADH7, SADL0-SADL7, SPH, valid before SRDY Delay time, high high-impedance state (see Note Hold time, output data valid after high (see Note Setup time, SRSX, SRS0-SRS2, SCS, SBHE valid SRAS longer high (see Note Hold time, SRSX, SRS0-SRS2, SCS, SBHE valid after SRAS Setup time, SRAS high longer high (see Note Setup time, SRSX, SRS0-SRS2 valid before longer high (see Note Hold time, SRSX, SRS0-SRS2 valid after longer (see Note Setup time, SRD, SWR, SIACK high from previous cycle longer high Hold time, SRD, SWR, SIACK high after high Delay time, SWR, high SRDY high (see Note Delay time, SWR, high SRDY high-impedance state Delay time, SDBEN SRDY read cycle Delay time, SDBEN (see TMS380 Second Generation Token-Ring User's Guide, literature number SPWU005, subsection 3.4.1.1.1), provided previous cycle completed Delay time, high SDBEN high (see Note tc(SCK) tc(SCK) tc(SCK) tc(SCK)/2+4 tc(SCK)+3 tc(SCK)/2+4 25-MHZ OPERATION tc(SCK) tc(SCK) tc(SCK) tc(SCK)/2+4 tc(SCK)+3 tc(SCK)/2+4 33-MHZ OPERATION UNIT
Pulse duration, high between accesses (see Note tc(SCK) tc(SCK) This specification provided board design. later that indicates start cycle. NOTES: inactive chip-select SIACK DIO-read DIO-write cycles; inactive chip-select interrupt-acknowledge cycles. 80x8x mode, SRAS used strobe values SBHE, SRSX, SRS0-SRS2, SCS. When used SRAS must meet parameter 266a, SBHE, SRS0-SRS2, must meet parameter 264. SRAS strapped high, parameters 266a irrelevant parameter must met.
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
SCS, SRSX SRS0-SRS2 SBHE
Valid
Valid
SRAS 266a SIACK 272a 273a
272a 273a 272a High SDDIR 282R SDBEN 282a SRDY Hi-Z SADH0-SADH7 SADL0-SADL7 SPH, Hi-Z Output Data Valid 261a Hi-Z Hi-Z 283R 273a
80x8x mode, SRAS used strobe values SBHE, SRSX, SRS0-SRS2, SCS. When used SRAS must meet parameter 266a; SBHE, SRS0-SRS2, must meet parameter 264. SRAS strapped high, parameters 266a irrelevant parameter must met. When TMS380C30A begins drive SDBEN inactive, already latched write data internally. Parameter must input data buffers. 8-bit 80x8x-mode reads, SADH0-SADH7 contain don't-care data.
Figure 80x8x Read Cycle
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
80x8x write cycle (see Figure
266a 272a 273a Delay time, SRDY either high Pulse duration, SRAS high Setup time, SADH0-SADH7, SADL0-SADL7, SPH, valid before longer Hold time, SADH0-SADH7, SADL0-SADL7, SPH, valid after high Setup time, SRSX, SRS0-SRS2, SCS, SBHE SRAS longer high (see Note Hold time, SRSX, SRS0-SRS2, SCS, SBHE after SRAS Setup time, SRAS high longer high (see Note Setup time, SRSX, SRS0-SRS2 before longer high (see Note Hold time, SRSX, SRS0-SRS2 valid after longer (see Note Setup time, SRD, SWR, SIACK high from previous cycle longer high Hold time, SRD, SWR, SIACK high after high Delay time, SRDY first access register SRDY immediately following access (see TMS380 Second-Generation Token-Ring User's Guide, literature number SPWU005, subsection 3.4.1.1.1) Delay time, high SRDY high (see Note Delay time, high SRDY high-impedance state Delay time, SDDIR (see Note Delay time, SDBEN SRDY (see TMS380 Second Generation Token-Ring User's Guide, literature number SPWU005, subsection 3.4.1.1.1) Delay time, SDDIR SDBEN Delay time, high SDBEN longer register ready waiting required) register ready (waiting required) 25-MHZ OPERATION tc(SCK) tc(SCK) 4000 33-MHZ OPERATION tc(SCK) tc(SCK) 4000 UNIT
tc(SCK) tc(SCK)/2+4 tc(SCK)/2+4 4000 tc(SCK)/2+4 tc(SCK)/2+4
tc(SCK) tc(SCK)/2+4 tc(SCK)/2+4
282b
4000 tc(SCK)/2+4 tc(SCK)/2+4
282W 283W
Pulse duration, high between accesses (see Note tc(SCK) tc(SCK) later that indicates start This specification provided board design. NOTES: inactive chip-select SIACK DIO-read DIO-write cycles; inactive chip-select interrupt-acknowledge cycles. 80x8x mode, SRAS used strobe values SBHE, SRSX, SRS0-SRS2, SCS. When used SRAS must meet parameter 266a, SBHE, SRS0-SRS2, must meet parameter 264. SRAS strapped high, parameters 266a irrelevant parameter must met.
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
SCS, SRSX SRS0-SRS2 SBHE
Valid
SRAS SIACK 266a 272a 273a
273a
272a 272a SDDIR
273a
282W SDBEN 282b SRDY Hi-Z SADH0-SADH7 SADL0-SADL7 Hi-Z Data
283W
Hi-Z Hi-Z
When TMS380C30A begins drive SDBEN inactive, already latched write data internally. Parameter must input data buffers. 8-bit 80x8x-mode writes, value placed SADH0-SADH7 don't care.
Figure 80x8x Write Cycle
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
80x8x interrupt-acknowledge-cycle timing
first SIACK pulse (see Figure
Pulse duration, SIACK high between accesses (see Note Pulse duration, SIACK first pulse pulses 25-MHZ OPERATION tc(SCK) tc(SCK) 33-MHZ OPERATION tc(SCK) tc(SCK) UNIT
NOTE inactive chip-select SIACK DIO-read DIO-write cycles; inactive chip-select interrupt-acknowledge cycles. SIACK First Second
Figure 80x8x Interrupt-Acknowledge Cycle First SIACK Pulse second SIACK pulse (see Figure
261a 272a 273a 282a 282R Delay time, SRDY high Hold time, high-impedance state after SIACK (see Note Setup time, output data valid before SRDY Delay time, SIACK high high-impedance state (see Note Hold time, output data valid after SIACK high (see Note Setup time, inactive data strobe high SIACK longer high Hold time, inactive data strobe high after SIACK high Delay time, SIACK high SRDY high (see Note Delay time, SRDY first access register SRDY immediately following access Delay time, SIACK high SRDY high-impedance state Delay time, SDBEN SRDY read cycle Delay time, SIACK SDBEN (see TMS380 Second Generation Token-Ring User's Guide, literature number SPWU005, subsection 3.4.1.1.1), provided previous cycle completed tc(SCK) tc(SCK) 4000 tc(SCK) tc(SCK)/2+4 tc(SCK)+3 25-MHZ OPERATION tc(SCK) tc(SCK) 4000 tc(SCK) tc(SCK)/2+4 tc(SCK)+3 33-MHZ OPERATION UNIT
283R Delay time, SIACK high SDBEN high (see Note tc(SCK)/2+4 tc(SCK)/2+4 This specification provided board design. NOTE inactive chip-select SIACK DIO-read DIO-write cycles; inactive chip-select interrupt-acknowledge cycles.
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
SRSX SRS0-SRS2, SBHE
Only needs inactive. others don't care.
SIACK 272a 273a
272a 273a
272a High SDDIR 282R 283R SDBEN 273a
282a SRDY Hi-Z
Hi-Z 261a Hi-Z
SADH0-SADH7 SADL0-SADL7
Hi-Z
Output Data Valid
SRDY active-low bus-ready signal. must asserted before data output. 8-bit 80x8x-mode writes, value placed SADH0-SADH7 don't care.
Figure 80x8x Interrupt-Acknowledge Cycle Second SIACK Pulse
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
80x8x-mode bus-arbitration timing 80x8x-mode arbitration takes control (see Figure
Setup time, asynchronous signal SBBSY SHLDA before SBCLK longer high assure recognition that cycle Hold time, asynchronous signal SBBSY SHLDA after SBCLK assure recognition that cycle Delay time, SBCLK SADH0-SADH7, SADL0-SADL7, SPH, valid Delay time, SBCLK cycle SOWN Delay time, SBCLK cycle SDDIR read Delay time, SBCLK high SHRQ high Delay time, SBCLK high cycle high, acquisition Hold time, high-impedance state after SOWN low, acquisition User Master tc(SCK)-15 25-MHZ OPERATION 208a 208b 224a 224c 241a tc(SCK)-15 33-MHZ OPERATION UNIT
Exchange
Master
SBCLK Inputs 208a SBBSY SHLDA SHRQ SBHE Outputs SADH0- SADH7 SADL0- SADL7 SDDIR Read 224a SOWN While system interface controls active (that SOWN asserted), input disabled. Address Valid 224c Write 208b
241a
Figure 80x8x-Mode Arbitration Takes Control
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
80x8x-mode timing
80x8x-mode read cycle (see Figure
Setup time, SADL0-SADL7, SADH0-SADH7, SPH, valid before SBCLK cycle longer high Hold time, SADL0-SADL7, SADH0-SADH7, SPH, valid after SBCLK cycle parameters 207a 207b Hold time, SADL0-SADL7, SADH0-SADH7, SPH, valid after high Hold time, SADL0-SADL7, SADH0-SADH7, SPH, valid after SDBEN longer Setup time, asynchronous signal SRDY before SBCLK longer high assure recognition this cycle Hold time, asynchronous signal SRDY after SBCLK assure recognition this cycle Delay time, SBCLK address valid Delay time, SBCLK cycle SADH0-SADH7, SADL0-SADL7, SPH, high-impedance state Delay time, SBCLK high SALE SXAL high Hold time, SALE SXAL after high Delay time, SBCLK high SXAL cycle SALE cycle Hold time, SADH0-SADH7, SADL0-SADL7, SPH, valid after SALE SXAL Delay time, SBCLK cycle high (see Note Delay time, SBCLK cycle SDBEN high Delay time, SADH0-SADH7, SADL0-SADL7, SPH, high-impedance state Delay time, SBCLK cycle Hold time, SADH0-SADH7, SADL0-SADL7, SPH, high-impedance state after SBCLK cycle Pulse duration, Setup time, SADH0-SADH7, SADL0-SADL7, SPH, valid before SALE, SXAL longer high Delay time, SBCLK high cyle SDBEN Setup time, data valid before SRDY parameter 208a 2tc(SCK)-25 2tc(SCK)-25 25-MHZ OPERATION 207a 207b 208a 208b 216a 223R 225R 227R 237R 33-MHZ OPERATION UNIT
NOTE While system-interface controls active (that SOWN asserted), disabled.
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
SBCLK
TWAIT
Hi-Z SRAS Valid High 227R 223R
SXAL SALE SADH0-SADH7 SADL0-SADL7 SRDY 237R SDBEN 208b 225R Extended Address Address 208a Data 207b 207a Address 216a
SDDIR
8-bit 80x8x mode, SBHE/SRNW don't care input during inactive (high) output during DMA. Motorola-style slaves hold SDTACK active until master deasserts SAS. 8-bit 80x8x mode, most significant byte address maintained SADH address maintained according parameter 221; that held after high. parameter 208A met, then valid data must present before SRDY goes low.
Figure 80x8x-Mode Read Cycle
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SBHE
TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
80x8x-mode write cycle (see Figure
Setup time, asynchronous signal SRDY before SBCLK longer high assure recognition that cycle Hold time, asynchronous signal SRDY after SBCLK assure recognition that cycle Delay time, SBCLK SADH0-SADH7, SADL0-SADL7, SPH, valid Delay time, SBCLK high SALE SXAL high Hold time, SALE SXAL after high Delay time, SBCLK high SXAL cycle SALE cycle Hold time, address valid after SALE, SXAL Delay time, SBCLK cycle output data parity valid Hold time, SADH0-SADH7, SADL0-SADL7, SPH, valid after high Delay time, SBCLK high Delay time, SBCLK high cycle SDBEN high Hold time, SDBEN after SWR, SUDS, SLDS high Delay time, SBCLK cycle Setup time, SADH0-SADH7, SADL0-SADL7, SPH, valid before SALE, SXAL longer high Delay time, SBCLK high cycle SDBEN tc(SCK)/2-7 tc(SCK)-12 tc(SCK)/2-7 tc(SCK)-12 25-MHZ OPERATION 208a 208b 216a 223W 225W 225WH 227W 237W 33-MHZ OPERATION UNIT
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
SBCLK
TWAIT
SBHE
Valid
High
227W
223W
SXAL SALE SADH0-SADH7 SADL0-SADL7 SRDY 237W SDBEN 208b 225WH 225W Address Extended Address 208a Output Data 216a
High SDDIR cycle-steal mode, state present every system transfer. burst mode, state present first transfer whenever increment address register carries beyond least significant bits. 8-bit 80x8x mode, SBHE/SRNW don't care input during inactive (high) output during DMA. 8-bit 80x8x mode, most significant byte address maintained SADH address maintained according parameter 221; that held after high.
Figure 80x8x-Mode Write Cycle
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
80x8x-mode arbitration returns control (see Figure
Delay time, SBCLK cycle SADH0-SADH7, SADL0-SADL7, SPL, SPH, SRD, high-impedance state Delay time, SBCLK cycle SBHE high-impedance state Delay time, SBCLK cycle SOWN high Delay time, SBCLK cycle SDDIR high Delay time, SBCLK high cycle SHRQ Setup time, SRD, SWR, SBHE high-impedance state before SOWN longer 25-MHZ OPERATION 223b 224b 224d 33-MHZ OPERATION UNIT
Master SBCLK
Exchange (T1)
User Master (T2)
SHLDA SHRQ 223b SBHE Outputs SADH0- SADH7 SADL0- SADL7 SDDIR Read 224b SOWN 80x8x mode, system interface deasserts SHRQ rising edge SBCLK following state last system transfer controls. 68xxx mode, system interface deasserts SBRQ rising edge SBCLK state first system transfer controls. While system-interface controls active (that SOWN asserted), disabled. 224d Write Hi-Z Hi-Z Hi-Z
Figure 80x8x-Mode Arbitration Returns Control
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
80x8x-mode bus-release timing (see Figure
Setup time, asynchronous input SBRLS before SBCLK longer high assure recognition Hold time, asynchronous input SBRLS after SBCLK assure recognition Hold time, SBRLS after SOWN high 25-MHZ OPERATION 208a 208b 208c 33-MHZ OPERATION UNIT
SBCLK 208a
208b SBRLS 208c SOWN Unless otherwise specified, signals specified maximum delay from SBCLK transition signal valid, signal also specified hold previous value (including high impedance) until start that SBCLK transition. system interface ignores assertion SBRLS does system bus. does bus, when detects assertion SBRLS, completes internally started cycle relinquishes control bus. transfer started internally, system interface releases before starting another.
Figure 80x8x-Mode Release
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
68xxx timing
68xxx read cycle (see Figure
Delay time, SDTACK either SCS, SUDS, SLDS high Hold time, high-impedance state after SUDS SLDS (see Note Setup time, SADH0-SADH7, SADL0-SADL7, SPH, valid before SDTACK Delay time, SCS, SUDS, SLDS high SADH0-SADH7, SADL0-SADL7, SPH, high-impedance state (see Note Hold time, output data valid after SUDS SLDS longer (see Note Setup time, register address before SUDS SLDS longer high (see Note Hold time, register address valid after SUDS SLDS longer (see Note Setup time, SRNW before SUDS SLDS longer high (see Note Hold time, SRNW after SUDS SLDS high Hold time, SIACK high after SUDS SLDS high Delay time, SCS, SUDS, SLDS high SDTACK high (see Note Delay time, SDTACK first access register SDTACK immediately following access Delay time, SUDS SLDS high SDTACK high-impedance state Delay time, SDBEN SDTACK Delay time, SUDS SLDS SDBEN (see TMS380 Second Generation Token-Ring User's Guide, literature number SPWU005, subsection 3.4.1.1.1), provided previous cycle completed Delay time, SUDS SLDS high SDBEN high (see Note Pulse duration, SUDS SLDS high between accesses (see Note tc(SCK) 4000 tc(SCK) tc(SCK)/2+4 tc(SCK)+3 tc(SCK)/2+4 25-MHZ OPERATION 33-MHZ OPERATION UNIT
261a 273a 282a
tc(SCK) 4000 tc(SCK) tc(SCK)/2+4 tc(SCK)+3 tc(SCK)/2+4
282R
283R
tc(SCK)
tc(SCK)
This specification provided board design. NOTES: inactive chip-select SIACK DIO-read DIO-write cycles; inactive chip-select interrupt-acknowledge cycles. 80x8x mode, SRAS used strobe values SBHE, SRSX, SRS0-SRS2, SCS. When used SRAS must meet parameter 266a, SBHE, SRS0-SRS2, must meet parameter 264. SRAS strapped high, parameters 266a irrelevant parameter must met.
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
SRSX SRS0 SRS1 SIACK
Valid
273a SRNW SUDS SLDS High SDDIR 282R SDBEN 282a SDTACK Hi-Z SADH0-SADH7 SADL0-SADL7 Hi-Z 261a Output Data Valid Hi-Z Hi-Z 283R
SDTACK active-low bus-ready signal. must asserted before data output.
Figure 68xxx Read Cycle
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
68xxx write cycle (see Figure
272a 273a Delay time, SDTACK either SCS, SUDS, SLDS high Setup time, write data valid before SUDS SLDS longer Hold time, write data valid after SUDS SLDS high Setup time, register address before SUDS SLDS longer high (see Note Hold time, register address valid after SUDS SLDS longer (see Note Setup time, SRNW before SUDS SLDS longer high (see Note Setup time, inactive SUDS SLDS high active data strobe longer high Hold time, SRNW after SUDS SLDS high Hold time, inactive SUDS SLDS high after active data strobe high Delay time, SCS, SUDS, SLDS high SDTACK high (see Note Delay time, SDTACK first access register SDTACK immediately following access Delay time, SUDS SLDS high SDTACK high-impedance state Delay time, SUDS SLDS SDDIR (see Note Delay time, SDBEN SDTACK (see TMS380 Second Generation Token-Ring User's Guide, literaure number SPWU005, subsection 3.4.1.1.1) Delay time, SDDIR SDBEN Delay time, SUDS SLDS high SDBEN longer Pulse duration, SUDS SLDS high between accesses (see Note register ready waiting required) register ready (waiting required) tc(SCK) 25-MHZ OPERATION tc(SCK) tc(SCK) 4000 tc(SCK) tc(SCK)/2+4 tc(SCK)/2+4 4000 tc(SCK)/2+4 tc(SCK)/2+4 tc(SCK) 33-MHZ OPERATION tc(SCK) tc(SCK) 4000 tc(SCK) tc(SCK)/2+4 tc(SCK)/2+4 4000 tc(SCK)/2+4 tc(SCK)/2+4 UNIT
282b
282W 283W
later that indicates start cycle. This specification provided board design. NOTES: inactive chip-select SIACK DIO-read DIO-write cycles; inactive chip-select interrupt-acknowledge cycles. 80x8x mode, SRAS used strobe values SBHE, SRSX, SRS0-SRS2, SCS. When used SRAS must meet parameter 266a, SBHE, SRS0-SRS2, must meet parameter 264. SRAS strapped high, parameters 266a irrelevant parameter must met.
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
SRSX SRS0 SRS1 SIACK
Valid
273a SRNW 272a SUDS SLDS SDDIR 282W SDBEN Hi-Z SADH0-SADH7 SADL0-SADL7 282b Hi-Z Data Hi-Z Hi-Z 283W 273a
68xxx mode, skew between SLDS SUDS must exceed Provided this limitation observed, events referenced data strobe edge later occurring edge. Events defined data strobes, edges, such parameter 286, measured between latest earlier edges. When TMS380C25 begins drive SDBEN inactive, already latched write data internally. Parameter must input data buffers. SDTACK active-low ready signal. must asserted before data output.
Figure 68xxx Write Cycle
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
68xxx interrupt-acknowledge-cycle timing (see Figure
261a 272a 273a 282a 282R 283R Delay time, SDTACK either SUDS, SIACK high Hold time, high-impedance state after SIACK longer high (see Note Setup time, output data valid before SDTACK longer high Delay time, SIACK high high-impedance state (see Note Hold time, output data valid after SIACK longer (see Note Setup time, register address before SIACK longer high (see Note Setup time, inactive high SIACK active data strobe longer high Hold time, inactive SRNW high after active data strobe high Delay time, SRNW high SDTACK high (see Note Delay time, SDTACK first access register SDTACK immediately following access Delay time, SIACK high SDTACK high-impedance state Delay time, SDBEN SDTACK read cycle Delay time, SIACK SDBEN (see TMS380 Second Generation Token-Ring User's Guide, literature number SPWU005, subsection 3.4.1.1.1), provided previous cycle completed Delay time, SIACK high SDBEN high (see Note Pulse duration, SIACK high between accesses (see Note tc(SCK) tc(SCK) tc(SCK) 4000 tc(SCK) tc(SCK)/2+4 tc(SCK)+3 tc(SCK)/2+4 25-MHZ OPERATION tc(SCK) tc(SCK) tc(SCK) 4000 tc(SCK) tc(SCK)/2+4 tc(SCK)+3 tc(SCK)/2+4 33-MHZ OPERATION UNIT
This specification provided board design. later that indicates start cycle. NOTE inactive chip-select SIACK DIO-read DIO-write cycles; inactive chip-select interrupt-acknowledge cycles.
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
SRSX SRS0 SRS1 SBHE
Only needs Inactive. others don't care.
SIACK 272a SRNW 273a SLDS High SDDIR 282R SDBEN 282a SDTACK Hi-Z SADH0-SADH7 SADL0-SADL7 Hi-Z 261a Hi-Z Hi-Z 283R
Output Data Valid
SDTACK active-low ready signal. must asserted before data output. Internal logic drives SDTACK high verifies that reached valid-high level before making 3-state signal.
Figure 68xxx Interrupt-Acknowledge Cycle
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
68xxx-mode bus-arbitration timing
68xxx-mode arbitration takes control (see Figure
Setup time, asynchronous input SBGR before SBCLK longer high assure recognition this cycle Hold time, asynchronous input SBGR after SBCLK assure recognition this cycle Delay time, SBCLK address valid Delay time, SBCLK cycle SOWN (see Note Delay time, SBCLK cycle SDDIR read Delay time, SBCLK high either SHRQ SBRQ high Delay time, SBCLK high cycle SUDS SLDS high Hold time, SUDS, SLDS, SRNW, high-impedance state after SOWN low, aquisition tc(SCK-15) 25-MHZ OPERATION 208a 208b 224a 224c 241a tc(SCK-15) 33-MHZ OPERATION UNIT
NOTE Motorola-style slaves hold SDTACK active until master deasserts SAS.
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
User Master
Exchange
Master
SBCLK 208a Inputs SBGR 208b
SBERR SDTACK SBBSY SBRQ 208a SLDS SUDS Input Read SRNW Outputs SADH0- SADH7 SADL0- SADL7 SDDIR Read 224a 241a SOWN 80x8x mode, system interface deasserts SHRQ rising edge SBCLK following state last system-bus transfer controls. 68xxx mode, system interface deasserts SBRQ rising edge SBCLK state first system-bus transfer controls. While system-interface controls active (that SOWN asserted), input disabled. Write Hi-Z 224c Write 208b Output
Figure 68xxx-Mode Arbitration Takes Control
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DALLAS, TEXAS 75265
TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
68xxx-mode timing
68xxx-mode read cycle (see Figure
207a 207b 208a 208b 216a 223R 225R 233a 237R Setup time, input data valid before SBCLK cycle longer high Hold time, input data valid after SBCLK cycle parameters 207a 207b Hold time, input data valid after data strobe longer Hold time, input data valid after SDBEN longer Setup time, asynchronous input SDTACK before SBCLK longer high assure recognition this cycle Hold time, asynchronous input SDTACK after SBCLK assure recognition this cycle Pulse duration, SAS, SUDS, SLDS high Delay time, SBCLK high cycle SUDS SLDS active Delay time, SBCLK address valid Delay time, SBCLK cycle high impedance Delay time, SBCLK high SALE SXAL high Hold time, SALE SXAL after SUDS high Delay time, SBCLK high SXAL cycle SALE cycle Hold time, address valid after SALE, SXAL Delay time, SBCLK high Delay time, SBCLK cycle SUDS, SLDS, high (see Note Delay time, SBCLK cycle SDBEN high Hold time, high-impedance state after SBCLK cycle Setup time, address valid before SALE SXAL longer high Setup time, address valid before longer high Delay time, SBCLK high cycle SDBEN Setup time, data valid before SDTACK parameter 208a tw(SCKL)-15 tw(SCKL)-15 25-MHZ OPERATION tc(SCK)+ tw(SCKL)-18 33-MHZ OPERATION tc(SCK)+ tw(SCKL)-18 UNIT
NOTE While system-interface controls active (that SOWN asserted), disabled.
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
SBCLK
TWAIT
SUDS SLDS High SRNW SXAL SALE SADL0-SADH7 SADH0-SADL7 208b SDDIR 237R SDBEN read cycle, read strobe remains active until internal sample incoming data completed. Input data removed when either read strobe SDBEN becomes inactive. parameter 208a met, then valid data must present before SDTACK goes low. Motorola-style slaves hold SDTACK active until master deasserts SAS. pins should routed minimize inductance system ground. 225R 233a Address Extended Address 208a Data 207a Hi-Z 207b 216a 223R
Figure 68xxx-Mode Read Cycle
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TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
68xxx-mode write cycle (see Figure
208a 208b 211a 216a 223W 225W 225WH 233a 237W Setup time, asynchronous input SDTACK before SBCLK longer high assure recognition this cycle Hold time, asynchronous input SDTACK after SBCLK assure recognition this cycle Pulse duration, SAS, SUDS, SLDS high Delay time, SBCLK high cycle SUDS SLDS active Delay time, output data valid SUDS SLDS longer high Delay time, SBCLK address valid Delay time, SBCLK high SALE SXAL high Hold time, SALE SXAL after SUDS high Delay time, SBCLK high SXAL cycle SALE cycle Hold time, address valid after SALE, SXAL Delay time, SBCLK cycle output data parity valid Hold time, output data, parity valid after SUDS SLDS high Delay time, SBCLK high Delay time, SBCLK SUDS, SLDS, high Delay time, SBCLK high cycle SDBEN high Hold time, SDBEN after SUDS SLDS high Setup time, address valid before SALE SXAL longer high Setup time, address valid before longer high Delay time, SBCLK high cycle SDBEN tc(SCK)/2-7 tw(SCKL)-15 tc(SCK)-12 tc(SCK)/2-7 tw(SCKL)-15 tc(SCK)-12 tw(SCKL)-15 25-MHZ OPERATION tc(SCK)+ tw(SCKL)-18 tw(SCKL)-15 33-MHZ OPERATION tc(SCK)+ tw(SCKL)-18 UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
SBCLK
TWAIT
233a SUDS SLDS SRNW
223W
SXAL SALE SADL0-SADH7 SADH0-SADL7 208b SDDIR 237W SDBEN cycle-steal mode, state present every system transfer. burst mode, state present first transfer whenever increment address register carries beyond least significant bits. read cycle, read strobe remains active until internal sample incoming data completed. Input data removed when either read strobe SDBEN becomes inactive. terminals should routed minimize inductance system ground. 225WH 225W Address Extended Address 208b Output Data 216a
Figure 68xxx-Mode Write Cycle
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DALLAS, TEXAS 75265
TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
68xxx-mode arbitration returns control (see Figure
Delay time, SBCLK cycle SAD, SPL, SPH, SUDS, SLDS high-impedance state, release Delay time, SBCLK cycle SBHE/SRNW high-impedance state Delay time, SBCLK cycle SOWN high Delay time, SBCLK cycle SDDIR high Delay time, SBCLK high either SHRQ SBRQ high Setup from, SUDS, SLDS, SRNW, control signals high-impedance state before SOWN longer Master SBCLK Exchange 25-MHZ OPERATION 223b 224b 224d 33-MHZ OPERATION User UNIT
Inputs
SBGR
SDTACK SBRQ SUDS SLDS 223b Read SRNW Outputs SADH0-SADH7 SADL0-SADL7 Write Hi-Z 224d Write SDDIR Read 224b SOWN 80x8x mode, system interface deasserts SHRQ rising edge SBCLK following state last system-bus transfer controls. 68xxx mode, system interface deasserts SBRQ rising edge SBCLK state first system-bus transfer controls. Hi-Z
Figure 68xxx-Mode Arbitration Returns Control
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DALLAS, TEXAS 75265
TI380C30A INTEGRATED TOKEN-RING COMMPROCESSOR PHYSICAL-LAYER INTERFACE
68xxx-mode bus-release error timing (see Figures
208a 208b 208c Setup time, asynchronous input before SBCLK longer high assure recognition Hold time, asynchronous input SBRLS, SOWN, SBERR after SBCLK assure recognition Hold time, SBRLS after SOWN high Setup time, SBERR before SDTACK longer high parameter 208a 25-MHZ OPERATION 33-MHZ OPERATION UNIT
SBCLK 208a 208b SBRLS 208b SOWN 208a SDTACK Unless otherwise specified, signals specified maximum delay from SBCLK transition signal valid, signal also specified hold previous value (including high impedance) until start that SBCLK transition. system interface ignores assertion SBRLS does system bus. does bus, when detects assertion SBRLS, completes internally started cycle relinquishes control bus. transfer started internally, system interface releases before starting another. SBERR asserted when system interface controls system bus, current transfer completed, regardless value SDTACK. BERETRY register nonzero, cycle retried. BERETRY register zero, system interface then releases control system bus. system interface ignores assertion SBERR performing DMA-bus cycle system bus. When SBERR properly asserted BERETRY zero, however, system interface releases upon completion current transfer halts further system side. error synchronized local stops local sides. value SDMAADR, SDMADDRX, SDMALEN registers system interface defined after system-bus error. 208c
Figure 68xxx-Mode Release Error
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