Programmable Line Lock Clock Generator Features Applications

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Programmable Line Lock Clock Generator Features Applications

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FS6131-01
Programmable Line Lock Clock Generator
Features
Applications
Complete programmable control -bus Selectable CMOS PECL compatible outputs External feedback loop capability allows genlocking Tunable VCXO loop jitter attenuation Commercial (FS6131-01) industrial (FS6131-01i) temperature versions available
Frequency Synthesis Line-Locked Genlock Applications Clock Multiplication Telecom Jitter Attenuation
Figure Configuration
ADDR XOUT XTUNE
Description
CLKN CLKP EXTLF LOCK/IPRG
FS6131-01 monolithic CMOS clock generator/regenerator designed minimize cost compo2 nent count variety electronic systems. Cbus interface, FS6131-01 adapted many clock generation requirements. ability tune on-board voltage-controlled crystal oscillator (VCXO), length Reference Feedback Dividers, their granularity, flexibility Post Divider make FS6131-01 most flexible stand-alone phase-locked loop (PLL) clock generator available.
FS6131
16-pin 0.150" SOIC
Figure Block Diagram
LFTC XLROM[2:0] XLPDEN, XLSWAP
XTUNE
(optional)
XCT[3:0], XLVTEN
Control VCXO Divider
CRYSTAL LOOP
XLCP[1:0]
VCXO XOUT
(optional)
Internal Loop Filter
EXTLF STAT[1:0]
PhaseFrequency Detector
EXTLF
(optional)
Charge Pump
DOWN
Lock Detect
REFDIV[11:0]
CMOS
POST3[1:0] POST2[1:0] POST1[1:0]
LOCK/ IPRG
(optional)
REFDSRC
(fREF)
Reference Divider
(NR)
MLCP[1:0] PDREF
VCOSPD, OSCTYPE
PDFBK
PhaseFrequency Detector
Charge Pump
DOWN
Voltage Controlled Oscillator
Clock Gobbler
OUTMUX[1:0]
Post Divider (NPx) CMOS/PECL Output
CLKP
(fCLK)
CLKN
ADDR Feedback Divider (NF) Interface Registers
FBKDIV[13:0]
FBKDSRC[1:0]
(fVCO)
MAIN LOOP
FS6131
licensed trademark Philips Electronics, N.V. Windows Windows registered trademarks Microsoft Corporation. American Microsystems, Inc. reserves right change detail specifications required permit improvements design products.
FS6131-01
Programmable Line Lock Clock Generator
Table Descriptions
Key: Analog Input; Analog Output; Digital Input; Input with Internal Pull-Up; Input with Internal Pull-Down; Digital Input/Output; DI-3 Three-Level Digital Input, Digital Output; Power/Ground; Active
TYPE
NAME ADDR XOUT XTUNE LOCK/IPRG EXTLF CLKP CLKN
DESCRIPTION Serial Interface Clock (requires external pull-up) Serial Interface Data Input/Output (requires external pull-up) Address Select (see Section 5.2.1) Ground VCXO Feedback VCXO Drive VCXO Tune Power Supply (+5V) Lock Indicator PECL Current Drive Programming External Loop Filter Ground Reference Frequency Input Feedback Input Power Supply (+5V) Differential Clock Output Differential Clock Output
Functional Block Description
Main Loop
frequency appearing inputs equal. input/output relationship between reference frequency frequency
Main Loop Phase Locked Loop (ML-PLL) standard phase- frequency- locked loop architecture. shown Figure ML-PLL consists Reference Divider, Phase-Frequency Detector (PFD), charge pump, internal loop filter, Voltage-Controlled Oscillator (VCO), Feedback Divider, Post Divider. During operation, reference frequency (fREF), generated either on-board crystal oscillator external frequency source, first reduced Reference Divider. integer value that frequency divided called modulus, denoted Reference Divider. divided reference then into PFD. controls frequency (fVCO) through charge pump loop filter. provides high-speed, noise, continuously variable frequency clock source ML-PLL. output back through Feedback Divider (the modulus denoted close loop. will drive down frequency until divided reference frequency divided
fVCO
frequency used output frequency (fCLK) then basic equation rewritten
4.1.1 Reference Divider Reference Divider designed phase jitter. divider accepts either output either Crystal Loop (the VCXO output) external reference frequency, provides divided-down frequency PFD. Reference Divider 12-bit divider, programmed modulus from 4095. both Table Table additional programming information.
FS6131-01
Programmable Line Lock Clock Generator
4.1.2 Feedback Divider Feedback Divider based dual-modulus prescaler technique. technique allows same granularity fully programmable feedback divider, while still allowing programmable portion operate speed. high-speed pre-divider (also called prescaler) placed between programmable Feedback Divider because high speeds which operate. dual-modulus technique insures reliable operation speed that achieve reduces overall power consumption divider. example, fixed divide-by-eight could used Feedback Divider. Unfortunately, divide-by-eight would limit effective modulus feedback divider path multiples eight. limitation would restrict ability achieve desired ratio without making both Reference Feedback Divider values comparatively large. Large divider moduli generally undesirable increased phase jitter.
4.1.3
Feedback Divider Programming
requirement that means that Feedback Divider only programmed certain values below divider modulus selection divider values listed Table desired Feedback Divider less than find divider value table. Follow column find A-counter program value. Follow left find M-counter value. Above modulus Feedback Divider programmed value 16383. both Table Table additional programming information.
Table Feedback Modulus Below
M-COUNTER: FBKDIV[13:3] 00000000001 00000000010 00000000011 A-COUNTER: FBKDIV[2:0]
Figure Feedback Divider
fvco
DualModulus Prescaler Counter
00000000100 00000000101 00000000110 00000000111
FEEDBACK DIVIDER MODULUS
Counter
understand operation, refer Figure Mcounter (with modulus cascaded with dualmodulus prescaler. prescaler modulus were fixed overall modulus feedback divider chain would However, A-counter causes prescaler modulus altered first outputs prescaler. A-counter then causes dual-modulus prescaler revert modulus until M-counter reaches terminal state resets entire divider. overall modulus expressed where which simplifies
4.1.4 Post Divider Post Divider consists three individually programmable dividers, shown Figure
Figure Post Divider
POST1[1:0] POST2[1:0] POST3[1:0]
fGBL
Post Divider (NP1)
Post Divider (NP2)
POST DIVIDER (NPx)
Post Divider (NP3)
fout
moduli individual dividers denoted NP1, NP2, NP3, together they make array modulus NPx.
FS6131-01
Programmable Line Lock Clock Generator
Post Divider performs several useful functions. First, allows operated narrower range speeds compared variety output clock speeds that device required generate. Second, changes basic equation
extra integer denominator permits more flexibility programming loop many applications where frequencies must achieved exactly. Note that nominal 50/50 duty factor preserved selections which have modulus.
4.2.1 Clock Gobbler (Phase Adjust) Clock Gobbler circuit takes advantage unknown relationship between input output clocks permit adjustment CLKP/CLKN output clock phase relative input. Clock Gobbler circuit removes clock pulse before pulse clocks Post Divider. this way, phase output clock slipped until output phase aligned with input clock phase. adjust phase relationship, switch Feedback Divider source Post Divider input FBKDSRC bit, toggle register bit. Clock Gobbler output clock delayed clock period each transition from zero one. 4.2.2 Phase Alignment maintain fixed phase relation between input output clocks, Post Divider must placed inside feedback loop. source Feedback Divider obtained from output Post Divider FBKDSRC switch. addition, Feedback Divider must dividing multiple Post Divider.
Phase Adjust Sampling
line-locked genlocked applications, necessary know exact phase relation output clock relative input clock. Since included within feedback loop simple structure, output exactly phase aligned with input clock. Every cycle input clock equals NR/NF cycles clock.
Figure Simple
Reference Divider (NR)
Figure Aligned Phase
Phase Frequency Detect
fOUT
Reference Divider (NR)
fOUT
Phase Frequency Detect
Post Divider (NF)
fOUT
Feedback Divider (NF)
fOUT
Feedback Divider (NF)
addition Post Divider, while adding flexibility, makes phase relation between input output clock unknown because Post Divider outside feedback loop.
Figure with Post Divider
Reference Divider (NR) Phase Frequency Detect Post Divider (NF)
fOUT
fVCO fOUT
Feedback Divider (NF)
fVCO
4.2.3 Phase Sampling Initial Alignment However, ability adjust phase useless without knowing initial relation between output input phase. initial synchronization output phase input phase, Phase Align "flag" makes transition (zero zero) when output clock phase becomes aligned with feedback source phase. feedback source clock definition, locked input clock phase. First, FS6131 used sample output clock with feedback source clock set/clear Phase Align flag when clocks match within feedback source clock period. Then, Clock Gobbler used delay output phase relative input phase clock time until transition flag occurs. When transition occurs, output input clocks phase aligned.
FS6131-01
Programmable Line Lock Clock Generator
enter this mode, STAT[1] clear STAT[0] zero. CMOS one, LOCK/IPRG display flag. flag always available under software control reading back STAT[1] bit, which will overwritten flag this mode. 4.2.4 Feedback Divider Monitoring Feedback Divider clock brought LOCK/IPRG independent output clock allow monitoring Feedback Divider clock. enter this mode, both STAT[1] STAT[0] bits one. CMOS must also enable LOCK/IPRG output. transfer function rad/s, accounting phase integration that occurs VCO)
2AVCO
transfer function Feedback Divider
Finally, sampling effect that occurs Phase Detector accounted
SAMP
Loop Gain Analysis
applications where external loop filter required, following analysis example used determine loop gain stability. loop gain product gains within loop. Establish basic operating parameters: charge pump current:
loop gain
LOOP SAMP
Figure Loop Gain Frequency
chgpump
loop filter values:
0.015µF
gain (VCOSPD): Feedback Divider:
3500
Amplitude
AVCO
Reference frequency input Phase Detector: 20kHz transfer function Phase Detector Charge Pump combination A/rad):
chgpump
0.01 0.1kHz
1kHz
10kHz
100kHz
transfer function loop filter V/A):
Frequency (fi)
FS6131-01
Programmable Line Lock Clock Generator
loop phase angle
LOOP
Voltage-Controlled Crystal Oscillator
Figure Loop Phase Frequency
-100°
-150°
0.1kHz
1kHz
10kHz
100kHz
Frequency (fi)
Nyquist plot gain amplitude shown below.
Figure Loop Nyquist Plot
135°
Amplitude
VCXO provides tunable, low-jitter frequency reference rest FS6131 system components. Loading capacitance crystal internal device. external components (other than resonator itself) required operation VCXO. resonator loading capacitance adjustable under register control. This feature permits factory coarse tuning inexpensive resonators necessary precision digital video applications. Continuous fine-tuning VCXO frequency accomplished varying voltage XTUNE pin. total change (from extreme other) effective loading capacitance 1.5pF nominal, effect shown Figure oscillator operates crystal resonator parallelresonant mode. Crystal warping, "pulling" crystal oscillation frequency, accomplished altering effective load capacitance presented crystal oscillator circuit. actual amount that changing load capacitance alters oscillator frequency will dependent characteristics crystal well oscillator circuit itself. motional capacitance crystal (usually referred crystal manufacturers C1), static capacitance crystal (C0), load capacitance (CL) oscillator determine warping capability crystal oscillator circuit. simple formula determine total warping capability crystal
Phase
Gain Margin
180°
ppm)
Phase Margin
225°
315°
where extremes applied load capacitance obtained from Table Example: crystal with following parameters used with FS6131. total coarse tuning range C1=0.02pF, C0=5.0pF, CL1=10.0pF, CL2=22.66pF
270°
Phase
0.02 (22.66 22.66
FS6131-01
Programmable Line Lock Clock Generator
4.4.1 VCXO Tuning VCXO coarse tuned programmable adjustment crystal load capacitance XCT[3:0] control bits. Table control code associated loading capacitance. actual amount frequency warping caused tuning capacitance will depend crystal used. VCXO tuning capacitance includes external load capacitance (12pF from ground 12pF from XOUT ground). fine tuning capability VCXO enabled setting XLVTEN one, disabled setting zero. Figure shows typical effect coarse fine tuning mechanisms. total coarse tune range about 350ppm. difference VCXO frequency parts million (ppm) shown fine tuning voltage XTUNE varies from Note that crystal load capacitance increased VCXO frequency pulled somewhat less with each coarse step, fine tuning range decreases. fine tuning range always overlaps coarse tuning ranges, eliminating possibility holes VCXO response. different crystal warping characteristics change scaling Y-axis, overall characteristic curves.
Crystal Loop
Crystal Loop designed attenuate jitter highly jittered, low-Q, frequency reference. Crystal Loop also maintain constant frequency output into Main Loop frequency reference intermittent. Crystal Loop consists Voltage-Controllable Crystal Oscillator (VCXO), divider, PFD, charge pump that tunes VCXO frequency reference. frequency reference phase-locked divided frequency external, high-Q, jitter-free crystal, thereby locking VCXO reference frequency. VCXO continue crystal even frequency reference becomes intermittent. 4.5.1 Locking External Frequency Source When Crystal Loop synchronized external frequency source, FS6131 monitor Crystal Loop detect loop unlocks from external source. Crystal Loop tries drive zero frequency external source dropped, sets Lock Status error flag. Crystal Loop also detect VCXO dropped Fine Tune range, requiring change Coarse Tune. Lock Status also latches direction loop went range (high low) when loop became unlocked. 4.5.1.1 Crystal Loop Lock Status Flag enable this mode, clear STAT[1] STAT[0] bits zero. CMOS one, LOCK/IPRG will Crystal Loop becomes unlocked. flag always available under software control reading back STAT[1] bit, which overwritten with status flag (low unlocked) this mode (see Table
Figure VCXO Coarse Fine Tuning
VCXO Range (ppm) XTUNE Voltage
VCXO Range (ppm)
XTUNE Voltage 0.0V XTUNE Voltage 5.0V
-100 -150 -200
Coarse Tune Setting XCT[3:0]
FS6131-01
Programmable Line Lock Clock Generator
4.5.1.2 Out-Of-Range High/Low direction loop gone out-of-range determined clearing STAT[1] zero setting STAT[0] one. CMOS one, LOCK/IPRG will high Crystal Loop went range high. goes logic-low, loop went range low. out-of-range information also available under software control reading back STAT[1] bit, which overwritten flag (high out-of-range high, out-of-range low) this mode. cleared only Crystal Loop loses lock (see Table 4.5.1.3 Crystal Loop Disable Crystal Loop disabled setting XLPDEN logic-high (1). disables charge pump circuit loop. Setting XLPDEN permits crystal loop operate control loop.
Differential Output Stage
differential output stage supports both CMOS pseudo-ECL (PECL) signals. desired output interface chosen program registers (see Table PECL interface used, transmission line usually terminated using termination. output stage only sink current PECL mode, amount sink current programming resistor LOCK/IPRG pin. ratio IPRG current output drive current shown Figure Source current provided pull-up resistor that part termination.
Figure IPRG CLKP/CLKN Current
25.0
IPRG Input Current (mA)
20.0
15.0
Connecting FS6131 External Reference Frequency
10.0
crystal oscillator used, ground shut down crystal oscillator setting XLROM[2:0]=1. pins have pull-up pull-down current, have small amount hysteresis reduce possibility extra edges. Signals ACcoupled into these inputs with external DC-bias circuit generate DC-bias 2.5V. Reference Feedback signal should square best results, signals should rail-to-rail. Unused inputs should grounded avoid unwanted signal injection.
CLKP/CLKN PECL Output Current (mA)
FS6131-01
Programmable Line Lock Clock Generator
Each data transfer initiated START condition terminated with STOP condition. number data bytes transferred between START STOP conditions determined master device, continue indefinitely. However, data that overwritten device after first eight bytes will overflow into first register, then second, first-in, firstoverwritten fashion. 5.1.5 Acknowledge When addressed, receiving device required generate Acknowledge after each byte received. master device must generate extra clock pulse coincide with Acknowledge bit. acknowledging device must pull line during high period master acknowledge clock pulse. Setup hold times must taken into account. master must signal data slave generating acknowledge last byte that been read (clocked) slave. this case, slave must leave line high enable master generate STOP condition.
C-bus Control Interface
This device read/write slave device meeting Philips C-bus specifications except "general call." controlled master device that generates serial clock SCL, controls access, generates START STOP conditions while device works slave. Both master slave operate transmitter receiver, master device determines which mode activated. device that sends data onto defined transmitter, device receiving data receiver. C-bus logic levels noted herein based percentage power supply (VDD). logic-one corresponds nominal voltage VDD, while logic-zero corresponds ground (VSS).
Conditions
Data transfer only initiated when busy. During data transfer, data line (SDA) must remain stable whenever clock line (SCL) high. Changes data line while clock line high will interpreted device START STOP condition. following conditions defined C-bus protocol. 5.1.1 Busy Both data (SDA) clock (SCL) lines remain high indicate busy. 5.1.2 START Data Transfer high transition line while input high indicates START condition. commands device must preceded START condition. 5.1.3 STOP Data Transfer high transition line while held high indicates STOP condition. commands device must followed STOP condition. 5.1.4 Data Valid state line represents valid data line stable duration high period line after START condition occurs. data line must changed only during period signal. There clock pulse data bit.
I2C-bus Operation
programmable registers accessed randomly sequentially this bi-directional wire digital interface. crystal oscillator does have communication occur. device accepts following C-bus commands: 5.2.1 Slave Address After generating START condition, master broadcasts seven-bit slave address followed bit. address device
where controlled logic level ADDR pin. variable ADDR allows different FS6131 devices exist same bus. Note that every device C-bus must have unique address avoid conflicts. default address sets pulldown ADDR pin.
FS6131-01
Programmable Line Lock Clock Generator
initiate write procedure, that transmitted after seven-bit device address logic-low. This indicates addressed slave device that register address will follow after slave device acknowledges device address. register address written into slave's address pointer. Following acknowledge slave, master allowed write eight bytes data into addressed register before register address pointer overflows back beginning address. acknowledge device between each byte data must occur before next data byte sent. Registers updated every time device sends acknowledge host. register update does wait STOP condition occur. Registers therefore updated different times during Sequential Register Write. 5.2.5 Sequential Register Read Procedure Sequential read operations allow master read from each register order. register pointer automatically incremented after each read. This procedure more efficient than Random Register Read several registers must read. perform read procedure, that transmitted after seven-bit address logic-low, Register Write procedure. This indicates addressed slave device that register address will follow after slave device acknowledges device address. register address then written into slave's address pointer. Following acknowledge slave, master generates repeated START condition. repeated START terminates write procedure, until after slave's address pointer set. slave address then resent, with this time logic-high, indicating slave that data will read. slave will acknowledge device address, then transmits eight bytes data starting with initial addressed register. register address pointer will overflow initial register address larger than zero. After last byte data, master does acknowledge transfer does generate STOP condition.
5.2.2 Random Register Write Procedure Random write operations allow master directly write register. initiate write procedure, that transmitted after seven-bit device address logic-low. This indicates addressed slave device that register address will follow after slave device acknowledges device address. register address written into slave's address pointer. Following acknowledge slave, master allowed write eight bits data into addressed register. final acknowledge returned device, master generates STOP condition. either STOP repeated START condition occurs during Register Write, data that been transferred ignored. 5.2.3 Random Register Read Procedure Random read operations allow master directly read from register. perform read procedure, that transmitted after seven-bit address logic-low, Register Write procedure. This indicates addressed slave device that register address will follow after slave device acknowledges device address. register address then written into slave's address pointer. Following acknowledge slave, master generates repeated START condition. repeated START terminates write procedure, until after slave's address pointer set. slave address then resent, with this time logic-high, indicating slave that data will read. slave will acknowledge device address, then transmits eight-bit word. master does acknowledge transfer does generate STOP condition. 5.2.4 Sequential Register Write Procedure Sequential write operations allow master write each register order. register pointer automatically incremented after each write. This procedure more efficient than Random Register Write several registers must written.
FS6131-01
Programmable Line Lock Clock Generator
Figure Random Register Write Procedure
DEVICE ADDRESS REGISTER ADDRESS DATA
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From host device
Data Acknowledge STOP Condition Acknowledge From device host
Figure Random Register Read Procedure
DEVICE ADDRESS REGISTER ADDRESS DEVICE ADDRESS DATA
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From host device
7-bit Receive Device Address Repeat START Acknowledge From device host
Data Acknowledge READ Command STOP Condition Acknowledge
Figure Sequential Register Write Procedure
DEVICE ADDRESS REGISTER ADDRESS DATA DATA DATA
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From host device
Data Acknowledge
Data Acknowledge Acknowledge
Data Acknowledge STOP Command
From device host
Figure Sequential Register Read Procedure
DEVICE ADDRESS REGISTER ADDRESS DEVICE ADDRESS DATA DATA
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From host device
7-bit Receive Device Address Repeat START Acknowledge From device host
Data Acknowledge READ Command Acknowledge
Data Acknowledge STOP Command
FS6131-01
Programmable Line Lock Clock Generator
Programming Information
register bits cleared zero power-up. register bits read back written except STAT[1] (Bit 63).
Table Register
ADDRESS STAT[1]
(Bit
STAT[0]
(Bit
XLVTEN
(Bit Fine Tune Inactive Fine Tune Active
CMOS
(Bit PECL CMOS, Lock Status
XCT[3]
(Bit
XCT[2]
(Bit
XCT[1]
(Bit
XCT[0]
(Bit
Crystal Loop Lock Status
BYTE
Crystal Loop Range Main Loop Phase Status Feedback Divider Output
VCXO Coarse Tune Table
XLPDEN
(Bit
XLSWAP
(Bit with External VCXO with Internal VCXO
XLCP[1]
(Bit
XLCP[0]
(Bit
XLROM[2]
(Bit
XLROM[1]
(Bit
XLROM[0]
(Bit
(Bit Clock Phase Adjust Clock Phase Delay
BYTE
Crystal Loop Operates Crystal Loop Powered Down
1.5µA 24µA Crystal Loop Control Table
OUTMUX[1]
(Bit
OUTMUX[0]
(Bit
OSCTYPE
(Bit Phase Jitter Oscillator FS6031 Oscillator
VCOSPD
(Bit High Speed Range Speed Range
LFTC
(Bit Short Time Constant Long Time Constant
EXTLF
(Bit Internal Loop Filter External Loop Filter
MLCP[1]
(Bit
MLCP[0]
(Bit 1.5µA 24µA
Output
BYTE
Reference Divider Output Phase Detector Input VCXO Output
FBKDSRC[1]
(Bit
FBKDSRC[0]
(Bit
FBKDIV[13]
(Bit 8192
FBKDIV[12]
(Bit 4096
FBKDIV[11]
(Bit 2048
FBKDIV[10]
(Bit 1024
FBKDIV[9]
(Bit
FBKDIV[8]
(Bit
Post Divider Output
BYTE
Post Divider Input Counter
FBKDIV[7]
(Bit
FBKDIV[6]
(Bit
FBKDIV[5]
(Bit Counter
FBKDIV[4]
(Bit
FBKDIV[3]
(Bit
FBKDIV[2]
(Bit
FBKDIV[1]
(Bit Counter Table
FBKDIV[0]
(Bit
BYTE
POST3[1]
(Bit
POST3[1]
(Bit
POST2[1]
(Bit
POST2[0]
(Bit
POST1[1]
(Bit
POST1[0]
(Bit
Divide
Divide Divide Divide Divide
Divide Divide Divide Divide
BYTE
Reserved
Reserved
Divide Divide Divide
PDFBK
(Bit
PDREF
(Bit Reference Divider
SHUT
(Bit Main Loop Operates Main Loop Powered Down
REFDSRC
(Bit VCXO
REFDIV[11]
(Bit
REFDIV[10]
(Bit
REFDIV[9]
(Bit
REFDIV[8]
(Bit
BYTE
Feedback Divider
2048
1024
REFDIV[7] BYTE
(Bit
REFDIV[6]
(Bit
REFDIV[5]
(Bit
REFDIV[4]
(Bit
REFDIV[3]
(Bit
REFDIV[2]
(Bit
REFDIV[1]
(Bit
REFDIV[0]
(Bit
FS6131-01
Programmable Line Lock Clock Generator
Table Device Configuration Bits
NAME REFDSRC (Bit DESCRIPTION REFerence Divider SouRCe SHUT (Bit PDREF (Bit PDFBK (Bit FBKDSRC[1:0] (Bits 39-38) EXTLF (Bit OSCTYPE (Bit OUTMUX[1:0] (Bits 47-46) (Bit Crystal Oscillator (VCXO) Disabled (main loop operates) Enabled (main loop shuts down) Reference Divider Feedback Divider
Table LOCK/IPRG Configuration Bits
NAME DESCRIPTION crystal loop lock STATus mode main loop phase align STATus mode (see also Table STAT[1:0] (Bits 63-62) Crystal Loop Lock status: Locked Unlocked Crystal Loop Lock status: Range High Main Loop Phase Align status Feedback Divider output
main loop SHUT down select
Phase Detector REFerence source
Phase Detector FeedBacK source
Table Lock Status
CMOS STAT STAT LOCK IPRG STAT[1] READ STATUS Locked Unlocked Out-ofRange: Out-ofRange: High
FeedBacK Divider SouRCe Post Divider Output Output (Post Divider Input)
EXTernal Loop Filter select Internal Loop Filter EXTLF Phase Jitter Oscillator FS6031 Compatible Oscillator VCOSPD (Bit
OSCillator TYPe
Table Main Loop Tuning Bits
NAME DESCRIPTION SPeeD range select (see Table MLCP[1:0] (Bits 41-40) LFTC (Bit High Speed Range Speed Range
OUTput MUltipleXer select Main Loop (VCO Output) Reference Divider Output Phase Detector Input VCXO Output
Main Loop Charge Pump current Current 1.5µA Current Current Current 24µA
clock GobBLer control Clock Phase Adjust Clock Phase Delay PECL Output (positive-ECL output drive) CMOS Output Lock Status Indicator
Loop Filter Time Constant (internal) Short Time Constant: 13.5µs Long Time Constant: 135µs
CLKP/CLKN output mode CMOS (Bit
FS6131-01
Programmable Line Lock Clock Generator
Table Divider Control Bits
NAME REFDIV[11:0] (Bits 11-0) FBKDIV[13:0] (Bits 37-24) DESCRIPTION REFerence DIVider (NR) FeedBacK DIVider (NF) FBKDIV[2:0] FBKDIV[13:3] POST1[1:0] (Bits 17-16) POST2[1:0] (Bits 19-18) POST3[1:0] (Bits 21-20) Reserved (Bits 23-22) A-Counter Value M-Counter Value
Table Crystal Loop Tuning Bits
NAME DESCRIPTION Crystal Loop Charge Pump current XLCP[1:0] (Bits 53-52) XLROM[2:0] (Bits 51-49) XLVTEN (Bit Current 1.5µA Current Current Current 24µA
POST Divider (NP1) Divide Divide Divide Divide
Crystal Loop Divider select Crystal Oscillator Power-Down (see Table Crystal Loop Voltage fine Tune ENable Disabled (fine tune inactive) Enabled (fine tune active) with external VCXO that increases frequency response increasing voltage XTUNE pin. with VCXO that increases frequency response decreasing voltage XTUNE pin. this setting Internal VCXO Crystal Loop Power Down Enable
POST Divider (NP2) Divide
Crystal Loop SWAP polarity
Divide Divide Divide
XLSWAP (Bit
POST Divider (NP3) Divide Divide Divide Divide XLPDEN (Bit XCT[3:0] (Bits 59-56)
Disabled (crystal loop operates) Enabled (crystal loop powered down)
Crystal Coarse Tune (see Table
these reserved bits
Table Crystal Loop Control
XLROM XLROM XLROM VCXO DIVIDER 3072 3156 2430 2500 4000 3375 CRYSTAL FREQUENCY (MHz) 24.576 25.248 19.44 20.00 32.00 27.00
Crystal Oscillator Power-Down
FS6131-01
Programmable Line Lock Clock Generator
VCXO Coarse Tune
Table VCXO Coarse Tuning Capacitance
XCT[3] XCT[2] XCT[1] XCT[0] VCXO TUNING CAPACITANCE (pF) 10.00 10.84 11.69 12.53 13.38 14.22 15.06 15.91 16.75 17.59 18.43 19.28 20.13 20.97 21.81 22.66
VCXO coarse tuned programmable adjustment crystal load capacitance XCT[3:0]. actual amount frequency warping caused tuning capacitance will depend crystal used. VCXO tuning capacitance includes external load capacitance (12pF from ground 12pF from XOUT ground). fine tuning capability VCXO enabled setting XLVTEN logic-one, disabled setting logiczero.
FS6131-01
Programmable Line Lock Clock Generator
Electrical Specifications
Table Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These conditions represent stress rating only, functional operation device these other conditions above operational limits noted this specification implied. Exposure maximum rating conditions extended conditions affect device performance, functionality, reliability.
PARAMETER Supply Voltage, (VSS ground) Input Voltage, Output Voltage, Input Clamp Current, VDD) Output Clamp Current, VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
SYMBOL
MIN. VSS-0.5 VSS-0.5 VSS-0.5
MAX. VDD+0.5 VDD+0.5
UNITS
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting loss functionality performance occur this device subjected high-energy electrostatic discharge.
Table Operating Conditions
PARAMETER Supply Voltage Ambient Operating Temperature Range Crystal Resonator Frequency Crystal Resonator Load Capacitance Crystal Resonator Motional Capacitance Serial Data Transfer Rate PECL Mode Programming Current (LOCK/IPRG High-Level Input Current) Output Driver Load Capacitance SYMBOL fXIN Parallel resonant, Parallel resonant, Standard mode PECL Mode CONDITIONS/DESCRIPTION MIN. 19.44 TYP. MAX. UNITS kb/s
FS6131-01
Programmable Line Lock Clock Generator
Table Electrical Specifications
Unless otherwise stated, 5.0V 10%, load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data production tested specific limits. characterization data from typical. Negative currents indicate current flows device.
PARAMETER Overall Supply Current, Dynamic, (with Loaded Outputs) Supply Current, Static Serial Communication (SDA, SCL) High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage Input Leakage Current Low-Level Output Sink Current (SDA) Tristate Output Current Address Select Input (ADDR) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current (pull-down) Low-Level Input Current Reference Frequency Input (REF, FBK) High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage Input Leakage Current Loop Filter Input (EXTLF) Input Leakage Current
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
IDDL
fCLK 66MHz; CMOS Mode, 5.5V SHUT XLROM[2:0] XLPDEN 5.5V
Vhys
Outputs Outputs Outputs
VSS-0.3
VDD+0.3
0.4V
5.5V
VSS-0.3
VDD+0.3
Vhys
VSS-0.3
VDD+0.3
EXTLF 0.8V; EXTLF MLCP[1:0] 0.8V; EXTLF MLCP[1:0] 0.8V; EXTLF MLCP[1:0] 0.8V; EXTLF MLCP[1:0] 4.2V; EXTLF MLCP[1:0] 4.2V; EXTLF MLCP[1:0] 4.2V; EXTLF MLCP[1:0] 4.2V; EXTLF MLCP[1:0]
-1.5
High-Level Output Source Current
Low-Level Output Sink Current
Crystal Oscillator Input (XIN) Threshold Bias Voltage High-Level Input Current Low-Level Input Current Crystal Loading Capacitance Input Loading Capacitance CL(xtal) CL(XIN) Outputs off; Outputs off; seen external crystal connected XOUT; VCXO tuning disabled seen external clock driver XOUT; unconnected; VCXO disabled
FS6131-01
Programmable Line Lock Clock Generator
Table
Electrical Specifications, continued
Unless otherwise stated, 5.0V 10%, load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data production tested specific limits. characterization data from typical. Negative currents indicate current flows device.
PARAMETER Crystal Oscillator Output (XOUT) High-Level Output Source Current Low-Level Output Sink Current VCXO Tuning (XTUNE) High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage Input Leakage Current
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Vhys
float float Lock Status: Range HIGH Lock Status: Range XLPDEN 0.8V; XLCP[1:0] 0.8V; XLCP[1:0] 0.8V; XLCP[1:0] 0.8V; XLCP[1:0] 4.2V; XLCP[1:0] 4.2V; XLCP[1:0] 4.2V; XLCP[1:0] 4.2V; XLCP[1:0]
VSS-0.3
VDD+0.3
-1.5 -100
High-Level Output Source Current
Low-Level Output Sink Current
Lock Indicator PECL Current Program (LOCK/IPRG) Low-Level Input Current High-Level Output Source Current Low-Level Output Sink Current Output Impedance Short Circuit Source Current Short Circuit Sink Current Clock Outputs, CMOS Mode (CLKN, CLKP) High-Level Output Source Current Low-Level Output Sink Current Output Impedance Short Circuit Source Current Short Circuit Sink Current Clock Outputs, PECL Mode (CLKN, CLKP) IPRG Current Output Current Ratio Low-Level Output Sink Current Tristate Output Current IPRG input current 15mA ISCH ISCL 2.4V 0.4V 0.5VDD; output driving high 0.5VDD; output driving shorted 30s, max. shorted 30s, max. ISCH ISCL PECL Mode CMOS Mode; 2.4V CMOS Mode; 0.4V 0.5VDD; output driving high 0.5VDD; output driving shorted 30s, max. shorted 30s, max.
FS6131-01
Programmable Line Lock Clock Generator
Table Timing Specifications
Unless otherwise stated, 5.0V 10%, load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data production tested specific limits. characterization data from typical.
PARAMETER Overall Output Frequency
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK (MHz)
MIN.
TYP.
MAX.
UNITS
fO(max)
CMOS Outputs PECL Outputs Phase Jitter Oscillator (OSCTYPE VCOSPD 13.5
Frequency
fVCO
VCOSPD FS6031 Compatible Oscillator (OSCTYPE VCOSPD VCOSPD Phase Jitter Oscillator (OSCTYPE VCOSPD VCOSPD FS6031 Compatible Oscillator (OSCTYPE VCOSPD VCOSPD LFTC LFTC
Gain
AVCO
MHz/V
Loop Filter Time Constant Rise Time Fall Time Lock Time (Main Loop) Disable Time Divider Modulus Feedback Divider Reference Divider Post Divider
CMOS Outputs, 0.5V 4.5V; 15pF CMOS Outputs, 4.5V 0.5V; 15pF Frequency Synthesis Line Locked Modes (8kHz reference) From falling edge last data (SHUT output locked FBKDIV[13:0] (See also Table REFDIV[11:0] POST1[1:0] (See also Table POST2[1:0] (See also Table POST3[1:0] (See also Table
16383 4095
FS6131-01
Programmable Line Lock Clock Generator
Table Timing Specifications, continued
Unless otherwise stated, 5.0V 10%, load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data 27°C production tested specific limits. characterization data from typical.
PARAMETER Clock Output (CLKP, CLKN) Duty Cycle
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK (MHz)
MIN.
TYP.
MAX.
UNITS
Ratio pulse width measured from rising edge next falling edge 2.5V) clock period Rising edges 50ms apart 2.5V, relative ideal clock, CL=15pF, fREF=8kHz, NR=1, NF=193, NPx=64, CLF=0.054µF, RLF=15.7k, CLP=1800pF, OSCTYPE=0, MLCP=3, XLROM=7 Rising edges 50ms apart 2.5V, relative ideal clock, CL=15pF, fREF=15kHz, NR=1, NF=800, NPx=10, CLF=0.0246µF, RLF=15.7k, CLP=820pF, OSCTYPE=0, MLCP=3, XLROM=7
1.544 12.00 25.175 1.544 12.00 25.175
Jitter, Long Term (y())
tj(LT)
rising edges apart 2.5V relative ideal clock, CL=15pF, fREF=31.5kHz, NR=1, NF=799, NPx=4, CLF=0.015µF, RLF=15.7k, CLP=470pF, OSCTYPE=0, MLCP=3, XLROM=7 rising edges 500µs apart 2.5V relative ideal clock, CL=15pF, CMOS mode, fXIN=27MHz, NF=200, NR=27, NPx=2 rising edges 500µs apart 2.5V relative ideal clock, CL=15pF, PECL mode, fXIN=27MHz, NF=200, NR=27, NPx=1 From rising edge next rising edge 2.5V, CL=15pF, fREF=8kHz, NR=1, NF=193, NPx=64, CLF=0.054µF, RLF=15.7k, CLP=1800pF, OSCTYPE=0, MLCP=3, XLROM=7 From rising edge next rising edge 2.5V, CL=15pF, fREF=15kHz, NR=1, NF=800, NPx=10, CLF=0.0246µF, RLF=15.7k, CLP=820pF, OSCTYPE=0, MLCP=3, XLROM=7
Jitter, Period (peak-peak)
tj(P)
From rising edge next rising edge 2.5V, CL=15pF, fREF=31.5kHz, NR=1, NF=799, NPx=4, CLF=0.015µF, RLF=15.7k, CLP=470pF, OSCTYPE=0, MLCP=3, XLROM=7 From rising edge next rising edge 2.5V, CL=15pF, CMOS mode, fXIN=27MHz, NF=200, NR=27, NPx=2 From rising edge next rising edge 2.5V, CL=15pF, PECL mode, fXIN=27MHz, NF=200, NR=27, NPx=1
FS6131-01
Programmable Line Lock Clock Generator
Table Serial Interface Timing Specifications
Unless otherwise stated, 5.0V 10%, load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data production tested specific limits. characterization data from typical.
PARAMETER Clock frequency free time between STOP START time, START (repeated) Hold time, START time, data input Hold time, data input Output data valid from clock Rise time, data clock Fall time, data clock High time, clock time, clock time, STOP
SYMBOL fSCL tBUF tsu:STA thd:STA tsu:DAT thd:DAT tsu:STO
CONDITIONS/DESCRIPTION
STANDARD MODE MIN. 1000 MAX.
UNITS
Minimum delay bridge undefined region falling edge avoid unintended START STOP
SDA, SDA,
Figure Timing Data
tsu:STA thd:STA tsu:STO
START
ADDRESS DATA VALID
DATA CHANGE
STOP
Figure Data Transfer Sequence
tsu:STA thd:STA thd:DAT tsu:DAT tsu:STO
tBUF
FS6131-01
Programmable Line Lock Clock Generator
Table CLKP, CLKN Clock Outputs (CMOS Mode)
Voltage Drive Current (mA) MIN. TYP. MAX. Voltage High Drive Current (mA)
MIN.
TYP.
MAX. -153 -150 -148 -142
Output Current (mA)
-135 -124 -119 -111 -105
-100
-150
-200 Output Voltage
data this table represents nominal characterization data only.
Table LOCK/IPRG Clock Output (CMOS Mode)
Voltage Drive Current (mA) MIN. TYP. MAX. Voltage High Drive Current (mA)
MIN.
TYP.
MAX.
Output Current (mA)
Output Voltage
data this table represents nominal characterization data only.
FS6131-01
Programmable Line Lock Clock Generator
Package Information
Table 16-pin SOIC (0.150") Package Dimensions
DIMENSIONS INCHES MIN. 0.061 0.004 0.055 0.013 0.0075 0.386 0.150 0.230 0.010 0.016 MAX. 0.068 0.0098 0.061 0.019 0.0098 0.393 0.157 0.244 0.016 0.035 MILLIMETERS MIN. 1.55 0.102 1.40 0.33 0.191 9.80 3.81 5.84 0.25 0.41 MAX. 1.73
0.249 1.55 0.49 0.249 9.98 3.99 6.20 0.41 0.89
AMERICAN MICROSYSTEMS, INC.
RADII: 0.005" 0.01"
typ.
SEATING PLANE
0.050
1.27
BASE PLANE
Table 16-pin SOIC (0.150") Package Characteristics
PARAMETER Thermal Impedance, Junction Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk SYMBOL CONDITIONS/DESCRIPTION flow ft./min. Corner lead Center lead lead adjacent lead lead TYP. UNITS °C/W
FS6131-01
Programmable Line Lock Clock Generator
Ordering Information
Device Ordering Codes
DEVICE NUMBER FS6131 FS6131 FS6131 FS6131 FONT PACKAGE TYPE 16-pin (0.150") SOIC (Small Outline Package) 16-pin (0.150") SOIC (Small Outline Package) 16-pin (0.150") SOIC (Small Outline Package) 16-pin (0.150") SOIC (Small Outline Package) OPERATING TEMPERATURE RANGE 70°C (Commercial) 70°C (Commercial) -40°C 85°C (Industrial) -40°C 85°C (Industrial) SHIPPING CONFIGURATION Tape-and-Reel Tubes Tape-and-Reel Tubes
ORDERING CODE
11274-001 11274-011 11274-901 11274-911
-01i -01i
Demo Ordering Codes
DEVICE NUMBER: DESCRIPTION includes: Populated board with example device Interface Cable Programming Assistance Software
ORDERING CODE
11274-201
FS6131-01
Purchase components American Microsystems, Inc., sublicensed Associated Compa2 nies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips. Copyright 1998, 1999 American Microsystems, Inc. Devices sold covered warranty patent indemnification provisions appearing Terms Sale only. makes warranty, express, statutory implied description, regarding information forth herein regarding freedom described devices from patent infringement. makes warranty merchantability fitness purposes. reserves right discontinue production change specifications prices time without notice. AMI's products intended commercial applications. Applications requiring extended temperature range, unusual environmental requirements, high reliability applications, such military, medical life-support life-sustaining equipment, specifically recommended without additional processing such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, 83201, (208) 233-4690, (208) 234-6796, Address: http://www.amis.com E-mail: tgp@amis.com
FS6131-01
Programmable Line Lock Clock Generator
10.0
Demonstration Board Software
simple demonstration board Windows 3.1x/95/98-based software available from American Microsystems that illustrates capabilities FS6131. software operate under Windows cannot communicate with board. board schematic shown below. Components listed with asterisk required actual application, used here preserve signal integrity with cabling associated with board. cabled interface between computer parallel port (DB25 connector) board (J1) provided. Components shown dashed lines optional, depending application. Contact your local sales representative more information.
Figure Board Schematic
ADDR 2.2µF 0.1µF 27MHz 12pF 12pF CLKP 2.2µF 0.1µF CLKN
ADDR
CLKN CLKP
FS6131
XOUT XTUNE EXTLF LOCK/ IPRG
LOCK
AMERICAN MICROSYSTEMS, INC. FS6131 DEMO BOARD
FS6131-01
Programmable Line Lock Clock Generator
Connect Volt power supply board: +5V, BLACK ground. Remove software keys from computer parallel port. Connect supplied interface cable parallel port (DB25 connector) demo board (6pin connector). Make sure cable facing away from board. wire Figure Connect clock outputs target application board with twisted-pair cable.
10.1
Demo Contents
Demonstration board Interface cable (DB25 6-pin connector) Data sheet Programming software
10.2
Requirements
running Windows 3.1x 95/98 with accessible parallel (LPT1) port. Software also runs Windows calculation mode only. 2.0MB available space hard drive
10.4
Demo Program Operation
10.3
Board Setup Software Installation Instructions
self-expanding file unzip compressed demo files directory your choice. setup.exe file install programming software.
fs6131.exe program. Note that parallel port accessed your machine running Windows warning message will appear stating: "This version demo program cannot communicate with FS6131 hardware when running Windows operating system. want continue anyway, using just calculation features this program?" Clicking starts program calculation only. opening screen shown Figure
Figure Opening Screen
FS6131-01
Programmable Line Lock Clock Generator
best performance obtained running high speed possible. last three solutions show speed 200MHz. Furthermore, good performance obtained with smallest dividers possible, which means solution should provide best results.
10.4.1 Device Mode Device Mode block presets demo program program FS6131 either frequency synthesizer stand alone clock generator) line-locked genlock clock generator. Frequency Synthesis: stand alone clock generator. Note that Reference Source on-chip crystal oscillator, expected crystal frequency 27MHz, Voltage Tune Crystal Oscillator (i.e. VCXO) disabled. default output frequency (CLK freq.) requested 100MHz, with maximum error 10ppm, about 100Hz. Output Stage defaults CMOS mode. Line-Locked/Genlock: line lock genlock application. Note that Reference Source Pin, that expected reference frequency 8kHz. default output frequency requested 100x multiple reference frequency. 10.4.2 Example: Frequency Synthesizer Mode default demo program assumes FS6131 configured stand alone clock generator. Note that Reference Source defaults on-chip crystal oscillator, expected crystal frequency 27MHz, Voltage Tune Crystal Oscillator block (i.e. VCXO) disabled. default output frequency (CLK freq.) requested 100MHz, with maximum error 10ppm, about 100Hz. Output Stage defaults CMOS mode. Loop Filter block internal, Check Loop Stability switch exercise, click Calculate Solutions. program takes into account screen settings calculates possible combinations Reference, Feedback, Post Divider values that will generate output frequency (100MHz) from input frequency (27MHz) within desired tolerance (10ppm). will momentarily appear: "Calculating Solutions: Press cancel stop with solutions calculated far." number will increment every unique solution that found. This example will create unique solutions, which then displayed window lower right portion program screen.
Figure Frequency Synthesizer Screen
Clicking Solution highlights row, clicking Disp/Save Register Values provides window with final values settings. click then displays second window containing register information Register Map. solutions saved file, formats available: text format viewing, data format loading into FS6131. Clicking Load Solution into Hardware enabled) sends information format FS6131 parallel port. Note: This option available under Windows operating system. your operating system support parallel port communication connection cable attached, error message displayed: "The FS6131 Hardware detected! "Make sure that connected LPT# printer port that properly connected +5Volt power supply."
FS6131-01
Programmable Line Lock Clock Generator
10.4.3 Example: Line Locked Mode Selecting Line-Locked/Genlock option Device Mode block changes program default settings. Reference Source changes input, block appears permit entry input frequency MHz. Desired Multiple block allows entry reference frequency multiplying factor used generate output frequency. Exercise: Change Frequency 0.0315MHz, alter Desired Multiple 800. Change Loop Filter block external, leave values alone. Click Calculate Solutions. program takes into account current screen settings calculates possible combinations Reference, Feedback, Post Divider values that will generate output frequency from input frequency (31.5kHz) multiplied desired multiple 800. will appear: solutions were found! want retry calculations with Check Loop Stability option turned off?" Choose Yes. Another will momentarily appear: "Calculating Solutions: Press cancel stop with solutions calculated far." number will increment every unique solution that found. This example will create eight unique solutions, which then displayed window lower right portion program screen. best results, keep PostDiv value multiplied FbkDiv value from getting larger than 5000 while running much above 70MHz possible. tradeoff must made, better faster allow divider values large. Solution provides PostDiv value FbkDiv value combined value 3200. running about 100MHz. Click Solution highlight row, then click Suggest Loop Filter have program choose loop filter values. Suggested values external loop filter 4700pF 47k. reselect Check Loop Stability turn this feature Clicking Calculate Solutions regenerates same solutions provided earlier, only this time Loop Filter values were used.
Figure Line-Locked Screen
Clicking Solution highlights row, clicking Disp/Save Register Values provides window with final values settings. click then displays second window containing register information Register Map. solutions saved file, formats available: text format viewing data format loading into FS6131. Clicking Load Solution into Hardware enabled) sends information format FS6131 parallel port. Note that this option disabled Windows operating system. your operating system support parallel port communication connection cable attached, error message displayed: "The FS6131 Hardware detected! "Make sure that connected LPT# printer port that properly connected +5Volt power supply."
Table Cable Interface
Color White Green Blue Brown Black DB25 Signal ADDR
FS6131-01
Programmable Line Lock Clock Generator
Table Sample Text Output
FS6131 Solution Text File Line-Locked Genlock Mode Desired Multiple Source .0315MHz Reference External Loop Filter 47pF 4700Ohms Crystal Oscillator Voltage Tune Disabled Output Stage CMOS Reference Divider Feedback Divider Post Divider Charge Pump (uA) EXTLF XLVTEN CMOS Register Register Register Register Register Register Register Register
Figure Board Silkscreen
(64) (32) (36) (23)
Figure Board Traces Component Side
Figure Cable Connections
Figure Board Traces Solder Side
DB-25
FS6131-01
Programmable Line Lock Clock Generator
Applications Information
signal reflection will occur point PC-board trace where impedance mismatches exist. Reflections cause several undesirable effects high-speed applications, such increase clock jitter rise electromagnetic emissions from board. Using properly designed series termination each high-speed line alleviate these problems eliminating signal reflections.
11.1.1 Example Calculation PECL mode, output driver does source current, value determined ratios terminating resistors using equation
where pull-up resistor, pull-down resistor, VNMH desired noise margin,
11.1
PECL Output Mode
resistor ratio must also match line impedance equation
PECL interface desired, transmission line must terminated using dual, termination. output stage only sink current PECL mode, amount sink current programming resistor LOCK/IPRG pin. Source current provided pull-up resistor that part termination.
where line impedance. Combining these equations, solving gives
Figure Termination (PECL)
PECL Mode Output CLKP CLKN from IPRG
LOAD
load's VIH(min) 0.6, choose VNMH 0.45V. line impedance then about Substituting into equation line impedance solving gives value (choose 910). solve load's VIL, output sink current must programmed IPRG pin. desired 1.6, choose some extra margin. sink current 25mA through resistor generates 2.05V drop. sink current programmed IPRG pin, where ratio IPRG current output sink current 1:4. IPRG programming resistor generates 6.6mA, about 27mA output sink current.
termination uses resistors transmission line. parallel resistance termination resistors should sized equal transmission line impedance, taking into account driver sink current, desired rise fall times, specifications load.
FS6131-01
Programmable Line Lock Clock Generator
11.2
CMOS Output Mode
11.3
Serial Communications
CMOS interface desired, transmission line typically terminated using series termination. Series termination adds loading driver, requires less power than other resistive termination methods. addition, extra impedance exists from signal line reference voltage, such ground.
Figure Series Termination (CMOS)
DRIVER LINE
RECEIVE
Connection devices standard-mode implementa2 tion C-bus similar that shown Figure Selection pull-up resistors (RP) optional series resistors (RS) lines depends supply voltage, capacitance, number connected devices with their associated input currents. Control clock data lines done through open drain/collector current-sink outputs, thus requires external pull-up resistors both lines. guideline
shown Figure driver's output impedance (zO) series termination resistance (RS) must equal line impedance (zL). That
Cbus
When source impedance (zO+RS) matched line impedance, then voltage division incident wave amplitude one-half full signal amplitude.
where maximum rise time (minus some margin) Cbus total capacitance. Assuming controller other devices bus, including this one, results values range. series resistor provide protection against high voltage spikes will alter values
Figure Connections Serial
(optional)
However, full signal amplitude take twice long propagation delay line develop, reducing noise immunity during half-amplitude period. Note that voltage receive must signal amplitude that meets receiver switching thresholds. slew rate signal reduced additional delay load capacitance line impedance. Also, note that output driver impedance will vary slightly with output logic state (high low).
(optional)
(optional)
(optional)
Data Clock Data Clock
Data
Data
TRANSMITTER
RECEIVER
11.3.1 More Information More information C-bus found document C-bus (Including Specifications), available from Philips Semiconductors
FS6131-01
Programmable Line Lock Clock Generator
where reference source frequency (fREF) either supplied VCXO applied pin. Great flexibility permitted programming FS6131 achieve exact desired output frequencies since three integers involved computation.
12.0
Device Application: Stand-Alone Clock Generation
length reference feedback dividers, their granularity, flexibility post Divider make FS6131 most flexible monolithic stand-alone clock generation device available. effective block diagram FS6131 when programmed StandAlone mode shown Figure source Feedback Divider Stand-Alone mode output VCO. dividing input reference frequency down Reference Divider (NR), then multiplying Main Loop through Feedback Divider (NF), finally dividing Main Loop output frequency Post Divider (NPx), have defining relationship this mode. equation output clock frequency (fCLK) written
12.1
Example Calculation
Visual BASIC program available completely program FS6131 based given parameters. Suppose that reference source frequency 14.318MHz desired output frequency 100MHz. First, factor 14.318MHz reference frequency (which four times NTSC television color sub-carrier) into prime numbers. exact expression
14318181.81
(Eqn.1)
Figure Block Diagram: Stand-Alone Clock Generation
LFTC XLROM[2:0] XLPDEN, XLSWAP
XTUNE
(optional)
XCT[3:0], XLVTEN
Control VCXO Divider
CRYSTAL LOOP
XLCP[1:0]
VCXO XOUT
(optional)
Internal Loop Filter
PhaseFrequency Detector
EXTLF
EXTLF STAT[1:0] RIPRG
Charge Pump
DOWN
(optional)
Lock Detect
REFDIV[11:0]
CMOS
LOCK/ IPRG
(optional)
(fREF)
REFDSRC
Reference Divider
(NR)
MLCP[1:0] PDREF
VCOSPD, OSCTYPE
POST3[1:0] POST2[1:0] POST1[1:0]
PDFBK
PhaseFrequency Detector
Charge Pump
DOWN
Voltage Controlled Oscillator
Clock Gobbler
OM[1:0]
Post Divider (NPx) CMOS/PECL Output
CLKP
(fCLK)
CLKN
ADDR Feedback Divider (NF) Interface
FBKDSRC[1:0]
(fVCO)
Registers
MAIN LOOP
FBKDIV[14:0]
FS6131
FS6131-01
Programmable Line Lock Clock Generator
Next, express output input frequencies ratio fCLK fREF, where fCLK also been converted product prime numbers. Eqn. shows, frequency doubled multiplying Feedback Divider two. Post Divider return output frequency desired modulus. These divider settings place frequency 200MHz.
100000000.00 14318181.81 Simplifying above equation yields
12.2
Example Programming
(Eqn.
generate 100.000MHz from 14.318MHz, program following (refer Figure 30): Reference Divider input select VCXO REFDSRC=0 input select Reference Divider Feedback Divider PDREF=0 PDFBK=0 Reference Divider (NR) modulus REFDIV[11:0] Feedback Divider input select FBKDSRC=1 Feedback Divider (NF) modulus FBKDIV[14:0] NP1=2, NP2=1, NP3=1 combined Post Divider modulus NPx=2 POST1[1:0], POST2[1:0], POST3[1:0]. Select internal loop filter EXTLF=0 XLVTEN=0 XLPDEN=1 disable VCXO fine tune Crystal Loop Phase Frequency Detector VCOSPD=0 select high speed range
Deciding apportion denominator integers between Reference Divider Post Divider iterative process. obtain best performance, should operated highest frequency possible without exceeding upper limit 230MHz. (see Table 16). frequency (fVCO) calculated
Recall that Reference Divider have value between 4096, Post Divider limited values derived from
where values NP1, NP2, found Table this example, smallest integer that removed from denominator Eqn. three. Post Divider NPx=3, ratio fCLK fREF becomes (from Eqn.
Unfortunately, Post Divider modulus three requires frequency 300MHz, which greater than allowable fVCO noted Table best performance, program Post Divider modulus allow operate nominal frequency that least 70MHz less then 230MHz. Therefore, Reference Divider cannot reduced below modulus shown Eqn. However, still operated frequency higher than fCLK. Multiplying both numerator denominator does alter output frequency, does increase frequency.
(Eqn.
FS6131-01
Programmable Line Lock Clock Generator
13.0
Device Application: Line-Locked Clock Generation
13.1
Example Calculation
Line-locked clock generation, used here, refers process synthesizing clock frequency that some integer multiple horizontal line frequency graphics system. FS6131 easily configured perform that function, shown Figure line reference signal (fHSYNC) applied input direct application Main Loop PFD. Feedback Divider (NF) programmed desired number output clocks line. source Feedback Divider selected output Post Divider (NPx) that edges output clock maintain consistent phase alignment with line reference signal. modulus Post Divider should selected maintain frequency that comfortably within operating range noted Table
Visual BASIC program available completely program FS6131 based given parameters. Suppose that wish reconstruct pixel clock from source. This typical requirement projection panel application. First, establish total number pixel clocks desired between horizontal sync (HSYNC) pulses. number pixel clocks known horizontal total, Feedback Divider programmed that value. this example, choose horizontal total 800. Next, establish frequency HSYNC pulses (fHSYNC) line reference signal video mode. this case, fHSYNC=31.5kHz. output clock frequency fCLK calculated
HSYNC 31.5kHz 25.175MHz
Figure Block Diagram: Line-Locked Clock Generation
LFTC XLROM[2:0] XLPDEN, XLSWAP
XTUNE
(optional)
XCT[3:0], XLVTEN
Control VCXO Divider
CRYSTAL LOOP
XLCP[1:0]
VCXO XOUT
(optional)
Internal Loop Filter
PhaseFrequency Detector
EXTLF
EXTLF STAT[1:0] RIPRG
Charge Pump
DOWN
(optional)
Reference HSYNC
REFDIV[11:0]
Lock Detect
(fREF)
REFDSRC POST3[1:0], POST2[1:0], POST1[1:0]
CMOS
LOCK/ IPRG
(optional)
Reference Divider
(NR)
MLCP[1:0] PDREF
VCOSPD, OSCTYPE
PDFBK
PhaseFrequency Detector
Charge Pump
DOWN
Voltage Controlled Oscillator
Clock Gobbler
OM[1:0]
Post Divider (NPx) CMOS/PECL Output
CLKP
(fCLK)
CLKN
ADDR Feedback Divider (NF) Interface
FBKDSRC[1:0]
(fVCO)
Registers
MAIN LOOP
FBKDIV[14:0]
FS6131
FS6131-01
Programmable Line Lock Clock Generator
However, 31.5kHz line reference signal frequency internal loop filter used. series combination 0.015µF capacitor resistor from power (VDD) EXTLF provides external loop filter. 100pF 220pF capacitor parallel with combination improve filter performance. best performance, program Post Divider modulus allow operate nominal frequency that least 70MHz less then 230MHz. frequency (fVCO) calculated
13.2
Example Programming
generate pixel clocks between HSYNC pulses occurring line reference signal every 31.5kHz, program following (refer Figure 31): Clear OSCTYPE Turn crystal oscillator XLROM=7 inputs select Feedback Divider PDREF=1 PDFBK=0 Feedback Divider input select Post Divider FBKDSRC=0 Feedback Divider (NF) modulus (the desired number pixel clocks line) FBKDIV[14:0] NP1=4, NP2=1, NP3=1 combined Post Divider modulus NPx=4 POST1[1:0], POST2[1:0], POST3[1:0]. Select external loop filter EXTLF=1 XLVTEN=0 XLPDEN=1 disable VCXO fine tune Crystal Loop Phase Frequency Detector VCOSPD=1 select speed range
HSYNC
Setting Post Divider equal four (NPx=4) reasonable solution, although there number values that will work. keep
5000
avoid divider values from becoming large. These settings place frequency about 100MHz. Calculate ideal charge pump current (Ipump)
pump
HSYNC 15kHz AVCO
where external loop filter series resistor, external loop filter series capacitor, AVCO gain. gain either: AVCO=125MHz/V High Range selected, AVCO=75MHz/V Range selected. Table more information range. With fhsync=31.5kHz, Clf=0.015µF, Rlf=15k, NF=800, NPx=4, AVCO=125MHz/V, charge pump current 39.3µA. 220pF across entire loop filter also helpful.
MLCP[1:0] select 32µA range output clock frequency fCLK 25.175MHz, with internal frequency 100.8MHz. Note that Crystal Loop unused this application.
FS6131-01
Programmable Line Lock Clock Generator
output clock frequency
14.0
Device Application: Genlocking
HSYNC horizontal total
only remaining task select Post Divider modulus (NPx) that allows frequency within nominal range.
Genlocking refers process synchronizing horizontal sync pulses (HSYNC) target graphics system HSYNC source graphics system. genlocked mode, FS6131 increases decreases) frequency until input frequency matched phase-aligned frequency applied input. Since feedback divider within graphics system graphics system source signal applied input FS6131, graphics system effectively synchronized input shown Figure configure FS6131 genlocking, input (pin input (pin switched directly onto feedback input PFD. Reference Feedback dividers used.
14.1
Example Calculation
Visual BASIC program available completely program FS6131 based given parameters. FS6131 being used genlock projection panel system card-generated HSYNC. total number pixel clocks generated card, known horizontal total, 800. Therefore, panel graphics system that clocked FS6131 divide output clock frequency (fCLK) 800. input HSYNC reference frequency (fHSYNC) 15kHz.
Figure Block Diagram: Genlocking
LFTC XLROM[2:0] XLPDEN, XLSWAP
XTUNE
(optional)
XCT[3:0], XLVTEN
Control VCXO Divider
CRYSTAL LOOP
XLCP[1:0]
VCXO XOUT
(optional)
Internal Loop Filter
PhaseFrequency Detector
EXTLF
EXTLF STAT[1:0] RIPRG
Charge Pump
DOWN
(optional)
Reference HSYNC
REFDIV[11:0]
Lock Detect
(fCLK)
REFDSRC POST3[1:0], POST2[1:0], POST1[1:0]
CMOS
LOCK/ IPRG
(optional)
Reference Divider
(NR)
MLCP[1:0] PDREF
VCOSPD, OSCTYPE
PDFBK
PhaseFrequency Detector
Charge Pump
DOWN
Voltage Controlled Oscillator
Clock Gobbler
OM[1:0]
Post Divider (NPx) CMOS/PECL Output
CLKP
(fCLK)
CLKN
ADDR Feedback Divider (NF) Interface
FBKDSRC[1:0]
(fVCO)
Registers
FBKDIV[14:0]
MAIN LOOP
FS6131
System HSYNC Video Graphics System Clock
FS6131-01
Programmable Line Lock Clock Generator
output clock frequency calculated
15kHz 12.0MHz
best performance, program Post Divider (NPx) modulus allow operate nominal frequency that least 70MHz less then 230MHz. frequency (fVCO) calculated
14.2
Example Programming
generate pixel clocks between HSYNC pulses occurring line reference signal every 15kHz, program following (refer Figure 32): Clear OSCTYPE Turn crystal oscillator XLROM=7 inputs select pins PDREF=1 PDFBK=1 NP1=2, NP2=3, NP3=1 combined Post Divider modulus NPx=6 POST1[1:0], POST2[1:0], POST3[1:0]. Select external loop filter EXTLF=1 XLVTEN=0 XLPDEN=1 disable VCXO fine tune Crystal Loop Phase Frequency Detector VCOSPD=1 select speed range
Selecting Post Divider modulus NPx=6 reasonable solution, although there number values that will work. keep
5000
avoid divider values from becoming large. settings place frequency about 72MHz. Calculate ideal charge pump current (Ipump)
pump
HSYNC 15kHz AVCO
where external loop filter series resistor, external loop filter series capacitor, AVCO gain. gain either AVCO=125MHz/V High Range selected, AVCO=75MHz/V Range selected. Table more information range. With fhsync=15kHz, Clf=0.015µF, Rlf=15k, NF=800, NPx=6, AVCO=125MHz/V, charge pump current 24µA. 220pF across entire loop filter also helpful.
MLCP[1:0] select 32µA range output clock frequency fCLK 12MHz, with internal frequency 72MHz. Note that Crystal Loop unused this application.
FS6131-01
Programmable Line Lock Clock Generator
15.0
Device Application: Telecom Clock Regenerator
15.1
Example Calculation
FS6131 used clock regenerator shown Figure This mode uses voltagecontrolled crystal oscillator (VCXO) phaselocked loop, referred Crystal Loop. VCXO provides "de-jittered" multiple reference frequency (usually 8kHz telecom applications) Main Loop. essence, Crystal Loop "cleans reference signal Main Loop. Control VCXO Divider preloaded with most common ratios permit locking most standard telecommunications crystals 8kHz signal applied pin. de-jittered multiple reference frequency from VCXO then supplied Reference Divider Main Loop. Reference Divider, along with Feedback Divider, programmed achieve desired output clock frequency.
Visual BASIC program available completely program FS6131 based given parameters. this example, 8kHz reference frequency supplied FS6131 output clock frequency 51.84MHz desired. First, select frequency which VCXO will operate from Table table shows external crystal frequency options available choose from, since VCXO runs crystal frequency. While Main Loop programmed work with frequencies table, best performance will achieved with highest frequency Main Loop PFD. frequency Main Loop (fMLpfd) VCXO frequency (fVCXO) divided Main Loop Reference Divider (NR).
MLpfd
VCXO
Figure Block Diagram: Telecom Clock Regenerator
LFTC
XTUNE
(optional)
XCT[3:0], XLVTEN
Control VCXO Divider
XLROM[2:0] XLPDEN, XLSWAP
CRYSTAL LOOP
XLCP[1:0]
VCXO XOUT
(optional)
Internal Loop Filter
PhaseFrequency Detector
EXTLF
EXTLF STAT[1:0] RIPRG
Charge Pump
DOWN
(optional)
8kHz (typical)
Lock Detect
REFDIV[11:0]
CMOS
LOCK/ IPRG
(optional)
(fREF)
REFDSRC
Reference Divider
(NR)
MLCP[1:0] PDREF
VCOSPD, OSCTYPE
POST3[1:0], POST2[1:0], POST1[1:0]
PDFBK
PhaseFrequency Detector
Charge Pump
DOWN
Voltage Controlled Oscillator
Clock Gobbler
OM[1:0]
Post Divider (NPx) CMOS/PECL Output
CLKP
(fCLK)
CLKN
ADDR Feedback Divider (NF) Interface
FBKDSRC[1:0]
(fVCO)
Registers
MAIN LOOP
FBKDIV[14:0]
FS6131
FS6131-01
Programmable Line Lock Clock Generator
goal choose highest crystal frequency from Table that generates smallest value equation establishing output frequency (fCLK) function input VCXO frequency
15.2
Example Programming
VCXO
(Eqn.
generate de-jittered output frequency 51.84MHz from 8kHz reference, program following (refer Figure 33): Program VCXO Control XLROM[2:0] select external 19.44MHz crystal Enable VCXO fine tune XLVTEN=1 Enable Crystal Loop XLPDEN=0 XLSWAP=0 Reference Divider input select VCXO REFDSRC input select Reference Divider Feedback Divider PDREF PDFBK Reference Divider (NR) modulus REFDIV[11:0] Feedback Divider input select FBKDSRC Feedback Divider (NF) modulus FBKDIV[14:0] NP1=1, NP2=3, NP3=1 combined Post Divider modulus NPx=3 POST1[1:0], POST2[1:0], POST3[1:0]. Select internal loop filter EXTLF
where Feedback Divider modulus. Choose different crystal frequencies from Table factor both input VCXO output clock frequencies into prime numbers. Look factors that will give smallest modulus with largest FVCXO. output VCXO frequencies reduced factors from Eqn. Table
Table Clock Regenerator Example
VCXO FREQUENCY FROM Table (fVCXO, MHz)
VCXO
20.00 19.44 25.248 24.576
51840000 20000000 51840000 19440000
51840000 25248000 51840000 24576000
VCOSPD=0 select high speed range These settings provide highest frequency Main Loop Phase Frequency Detector 6.48MHz. 19.44MHz crystal requires that XLROM[2:0] three shown Table
19.44MHz crystal provides smallest modulus (NR=3) with highest crystal frequency. Finally, choose Post Divider (NPx) modulus that keeps frequency most comfortable range. frequency (fVCO) calculated
Selecting overall modulus NPx=3 sets frequency 155.52MHz when loop locked.

Programmable Line Lock Clock Generator Features Applications

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