4-channel Digital Decimation Filter Multiple On-chip Coefficient
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CS5376A Low-power, Multi-channel Decimation Filter
4-channel Digital Decimation Filter
Multiple On-chip Coefficient Sets Programmable Coefficients Custom Filters Synchronous Operation
Description
CS5376A multi-function digital filter utilizing low-power signal processing architecture achieve efficient filtering four modulators. combining CS5376A with CS3301/02 differential amplifiers, CS5371/72 modulators, CS4373A test synchronous, high-resolution, self-testing, multi-channel measurement system designed quickly easily. Digital filter coefficients CS5376A filters included on-chip simple setup, they programmed custom applications. Selectable digital filter decimation ratios produce output word rates from 4000 SPS, resulting measurement bandwidths ranging from 1600 down when using on-chip coefficient sets.
Selectable Output Word Rate
4000, 2000, 1000, 500, 333, 200, 125, 100,
Digital Gain Offset Corrections Test Stream Generator
Sine Wave Impulse Output Mode
Time Break Controller, General Purpose Secondary SPIPort, Boundary Scan JTAG Microcontroller EEPROM Configuration CS5376A includes integrated peripherals simplify Small-footprint, 64-pin TQFP Package system design: offset gain corrections, test stream generator, time-break controller, generLow Power Consumption
Channel
Flexible Power Supplies
Interface: Digital Logic Core:
al-purpose pins, secondary port, boundary scan JTAG port. ORDERING INFORMATION page 107.
VDD2 (x2)
SDRDY
SDCLK
RESET
(x2)
SDDAT
SDTKI
BOOT
VDD1
SYNC SYNC
SCK1
TBSCLK
ilte
JTAG
SCK2
MDATA [4:1]
MFLAG [4:1]
GND1
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved)
GND2 (x2)
(x2)
TRST
DS612F3
CS5376A
TABLE CONTENTS
General Description
1.1. 1.2. 1.3. 1.4. Digital Filter Features Integrated Peripheral Features System Level Features Configuration Interface.
Characteristics Specifications
Specified Operating Conditions Absolute Maximum Ratings Thermal Characteristics Digital Characteristics Power Consumption. Switching Characteristics
System Design with CS5376A
3.1. 3.2. 3.3. 3.4. 3.5. 3.6. 3.7. 3.8. Power Supplies Reset Control Clock Generation Synchronization System Configuration. Digital Filter Operation Data Collection. Integrated peripherals
Power Supplies
4.1. Descriptions 4.2. Bypass Capacitors 4.3. Power Consumption.
Reset Control
5.1. Descriptions 5.2. Reset Self-Tests. 5.3. Boot Configurations
Clock Generation.
6.1. Description 6.2. Synchronous Clocking 6.3. Master Clock Jitter Skew.
Synchronization.
7.1. 7.2. 7.3. 7.4. 7.5. 8.1. 8.2. 8.3. 8.4. 8.5. Description MSYNC Generation Digital Filter Synchronization Modulator Synchronization Test Stream Synchronization Descriptions EEPROM Hardware Interface EEPROM Organization EEPROM Configuration Commands Example EEPROM Configuration
Configuration EEPROM.
Configuration Microcontroller
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CS5376A
9.1. 9.2. 9.3. 9.4. 9.5. 10.1. 10.2. 10.3. 10.4. 10.5. Descriptions Microcontroller Hardware Interface Microcontroller Serial Transactions Microcontroller Configuration Commands Example Microcontroller Configuration Descriptions Modulator Clock Generation Modulator Synchronization. Modulator Data Inputs Modulator Flag Inputs
Modulator Interface
Digital Filter Initialization
11.1. Filter Coefficient Selection 11.2. Filter Configuration Options
SINC Filter
12.1. 12.2. 12.3. 12.4. 13.1. 13.2. 13.3. 13.4. 13.5. 14.1. 14.2. 14.3. 14.4. 14.5. 14.6. 14.7. SINC1 Filter SINC2 Filter SINC3 Filter SINC Filter Synchronization FIR1 Filter FIR2 Filter On-Chip Coefficients Programmable Coefficients Filter Synchronization Architecture IIR1 Filter IIR2 Filter IIR3 Filter On-Chip Coefficients Programmable Coefficients Filter Synchronization
Filter
Filter
Gain Offset Correction.
15.1. Gain Correction 15.2. Offset Correction 15.3. Offset Calibration
Serial Data Port
16.1. Descriptions 16.2. Port Data Format 16.3. Port Transactions
Test Stream Generator
17.1. 17.2. 17.3. 17.4. 17.5. 17.6. Descriptions Architecture Configuration Data Source Sine Wave Output Impulse Output.
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CS5376A
17.7. Loopback Testing. 17.8. Synchronization
Time Break Controller
18.1. Description 18.2. Time Break Operation 18.3. Time Break Delay.
General Purpose
19.1. 19.2. 19.3. 19.4. 19.5. 20.1. 20.2. 20.3. 20.4. Descriptions GPIO Architecture GPIO Registers GPIO Input Mode GPIO Output Mode Descriptions Architecture Registers Transactions.
Serial Peripheral Interface
Boundary Scan JTAG
21.1. Descriptions 21.2. JTAG Architecture
Device Revision History
22.1. Changes from CS5376 CS5376 22.2. Changes from CS5376 CS5376A
Register Summary.
23.1. Registers 23.2. Digital Filter Registers
Descriptions Package Dimensions. Ordering Information Environmental, Manufacturing, Handling Information Revision History
LIST FIGURES
Figure CS5376A Block Diagram Figure Digital Filtering Stages Figure Coefficient Selection Word. Figure MOSI Write Timing Slave Mode Figure MISO Read Timing Slave Mode Figure Port Read Timing. Figure SYNC, MCLK, MSYNC, MDATA Interface Timing Figure Output Clock Data Timing. Figure Multi-Channel System Block Diagram Figure Power Supply Block Diagram Figure Reset Control Block Diagram Figure Clock Generation Block Diagram.
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CS5376A
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Synchronization Block Diagram EEPROM Configuration Block Diagram EEPROM Read Transactions Kbyte EEPROM Memory Organization. Serial Peripheral Interface (SPI Block Diagram Microcontroller Serial Transactions Registers Modulator Data Interface Digital Filter Stages Coefficient Selection Word. SINC Filter Block Diagram SINC Filter Stages Filter Block Diagram Filter Stages Minimum Phase Group Delay Filter Block Diagram Filter Stages Gain Offset Correction Serial Data Port Block Diagram Port Data Format Port Transaction Test Stream Generator Block Diagram Time Break Block Diagram GPIO Bi-directional Structure Serial Peripheral Interface (SPI Block Diagram Master Mode Transactions Transaction Details JTAG Block Diagram Control Register SPI1CTRL. Command Register SPI1CMD Data Register SPI1DAT1 Data Register SPI1DAT2 Hardware Configuration Register CONFIG GPIO Configuration Register GPCFG0 GPIO Configuration Register GPCFG1 Control Register SPI2CTRL. Command Register SPI2CMD Data Register SPI2DAT Filter Configuration Register FILTCFG Gain Correction Register GAIN1 Offset Correction Register OFFSET1 Time Break Counter Register TIMEBRK Test Stream Configuration Register TBSCFG Test Stream Gain Register TBSGAIN User Defined System Register SYSTEM1. .100 Hardware Version Register VERSION .101 Self Test Result Register SELFTEST .102
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CS5376A
LIST TABLES
Table Microcontroller EEPROM Configuration Commands Table Configurations Using On-Chip Data Table Digital Filter Registers Table Maximum EEPROM Configuration Table EEPROM Boot Configuration Commands Table Example EEPROM File. Table Microcontroller Boot Configuration Commands Table Example Microcontroller Configuration Table SINC Filter Configurations Table SINC1 SINC2 Filter Coefficients Table SINC3 Filter Coefficients. Table Filter Characteristics Table SINC Group Delay Table FIR1 Coefficients Table FIR2 Linear Phase Coefficients Table FIR2 Minimum Phase Coefficients Table Filter Characteristics Table Filter Coefficients. Table Configurations Using On-chip Data Table Impulse Characteristics. Table JTAG Instructions IDCODE Table JTAG Scan Cell Mapping
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CS5376A
VDD2 (x2)
SDRDY
SDCLK
SDDAT
(x2)
RESET
SDTKI
BOOT
VDD1
Serial Data Output Port
Clock Synchronization
SYNC MCLK MSYNC SCK1 MISO MOSI SINT TIMEB TBSCLK TBSDATA GPIO11:EECS GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4:CS4 GPIO3:CS3 GPIO2:CS2 GPIO1:CS1 GPIO0:CS0 SCK2
Serial Peripheral Interface Time Break Controller Test Stream Controller Decimation Filtering Engine
GPIO General Purpose
JTAG Interface
Modulator Data Interface
Serial Peripheral Interface
MDATA [4:1]
MFLAG [4:1]
(x2)
GND1
Figure CS5376A Block Diagram
GENERAL DESCRIPTION
CS5376A multi-channel digital filter with integrated system peripherals. Figure illustrates simplified block diagram CS5376A. bandwidth rates: 200, 125, 100, SPS.
Digital Filter Multi-channel decimation filter CS5371/72 modulators. channel concurrent operation. Synchronous operation simultaneous sampling multi-sensor systems. Internal synchronization digital filter phase external SYNC signal.
Flexible digital filter configuration. (See Figure Cascaded SINC, FIR, filters with selectable output stage. Linear minimum phase low-pass filter coefficients included. Butterworth high-pass filter coefficients included. coefficients programmable create custom filter response. Individual channel gain correction normalize signal amplitudes.
Multiple output word rates, including bandwidth rates. Standard output rates: 4000, 2000, 1000, 500, 333, SPS.
Digital gain correction.
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GND2 (x2)
TRST
CS5376A
Modulator Input
Sinc Filter 64000
FIR1
FIR2
IIR1 Order
IIR2
Order
Gain Offset Corrections
Output High Speed Serial Data Port Output Word Rate from 4000
Figure Digital Filtering Stages
Digital offset correction calibration. Individual channel offset correction remove measurement offsets. Calibration engine automatic calculation offset correction factors.
Programmable waveform data custom test signal generation.
Time break controller record system timing information. Dedicated status output data stream. Programmable output delay match system group delay.
Integrated Peripheral Synchronous operation simultaneous sampling multi-sensor systems. MCLK MSYNC output signals synchronize external components. Asynchronous operation direct connection system telemetry. Internal 8-deep data FIFO flexible output timing.
Additional hardware peripherals simplify system design. General Purpose (GPIO) pins local hardware control. Secondary serial port control local serial peripherals. JTAG port boundary scan (IEEE 1149.1 compliant).
High speed serial data output port port).
Digital test stream signal generator suitable CS4373A test DAC. Sine wave output mode testing total harmonic distortion. Impulse output mode transfer function characterization.
System Level Flexible configuration options. Configuration 'on-the-fly' microcontroller system telemetry. Fixed configuration stand-alone boot
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CS5376A
EEPROM. power consumption. 4-channel operation (9.25 mW/channel). standby mode. Separate digital logic core, telemetry I/O, modulator power supplies. Telemetry modulator interfaces operate from Digital logic core operates from Total footprint plus five bypass capacitors.
Configuration Interface
Configuration from microcontroller standalone boot EEPROM. Microcontroller boot permits reconfiguration during operation. EEPROM boot sets fixed operational configuration.
Flexible power supply configurations.
Configuration commands written through Serial Peripheral Interface (See Table Standardized microcontroller interface using registers. (See Table Commands write digital filter registers, filter coefficients, test stream data. Digital filter registers hardware configuration options.
Small 64-pin TQFP package.
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CS5376A
Microcontroller Boot Configuration Commands
Name WRITE REGISTER READ REGISTER WRITE COEFFICIENTS WRITE COEFFICIENTS 24-bit 000000 000001 000002 000003 000004 DAT1 24-bit [DATA] FIR1 (FIR COEF) COEF (TBS DATA) DAT2 24-bit DATA FIR2 (FIR COEF) (TBS DATA) Description Operation Write Digital Filter Register Read Digital Filter Register Write Custom Coefficients Write Custom Coefficients
WRITE COEFFICIENTS WRITE DATA WRITE FILTER START FILTER STOP
000005 000006 000007 000008 000009
On-Chip Coefficients Write Custom Test Stream Data On-Chip Data Start Digital Filter Operation Stop Digital Filter Operation
EEPROM Boot Configuration Commands
Name WRITE REGISTER WRITE COEFFICIENTS 8-bit DATA 24-bit DATA FIR1 FIR2 (FIR COEF) COEF (TBS DATA) Operation Write Digital Filter Register Write Custom Coefficients Description
WRITE COEFFICIENTS
Write Custom Coefficients
WRITE COEFFICIENTS WRITE DATA WRITE FILTER START
On-Chip Coefficients Write Custom Test Stream Data On-Chip Data Start Digital Filter Operation
[DATA] indicates data word returned from digital filter. (DATA) indicates multiple words this type written.
Table Microcontroller EEPROM Configuration Commands
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CS5376A
Bits Selection
23:20 0000
19:16 0000
15:12 IIR2
11:8 IIR1
FIR2
FIR1
Bits 15:12 0000 0001 0010 0011 0100
IIR2 Coefficients 2000 1000
Bits 11:8 0000 0001 0010 0011 0100
IIR1 Coefficients 2000 1000
Bits 0000 0001
FIR1 Coefficients Linear Phase Minimum Phase
Bits 0000 0001
FIR2 Coefficients Linear Phase Minimum Phase
Figure Coefficient Selection Word
Test Stream Characteristic Equation: (Signal Freq) Data) (Interpolation Output Rate Example: (31.25 (1024) (0x07
Signal Frequency (TBSDATA) 10.00 10.00 25.00 25.00 31.25 31.25 50.00 50.00 125.00 125.00
Output Rate (TBSCLK)
Output Rate Selection (RATE)
Interpolation Selection (INTP) 0x18 0x31 0x09 0x13 0x07 0x0F 0x04 0x09 0x01 0x03
Table Configurations Using On-Chip Data
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CS5376A
Registers
Name SPI1CTRL SPI1CMD SPI1DAT1 SPI1DAT2 Addr. Type Bits Control Command Data Data Description
Digital Filter Registers
Name CONFIG RESERVED GPCFG0 GPCFG1 SPI2CTRL SPI2CMD SPI2DAT RESERVED FILTCFG GAIN1 GAIN2 GAIN3 GAIN4 OFFSET1 OFFSET2 OFFSET3 OFFSET4 TIMEBRK TBSCFG TBSGAIN SYSTEM1 SYSTEM2 VERSION SELFTEST Addr. 01-0D 13-1F Type Bits Description Hardware Configuration Reserved GPIO[7:0] Direction, Pull-up Enable, Data GPIO[11:8] Direction, Pull-up Enable, Data Control Command Data Reserved Digital Filter Configuration Gain Correction Channel Gain Correction Channel Gain Correction Channel Gain Correction Channel Offset Correction Channel Offset Correction Channel Offset Correction Channel Offset Correction Channel Time Break Delay Test Stream Configuration Test Stream Gain User Defined System Register User Defined System Register Hardware Version Self-Test Result Code
Table Digital Filter Registers
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CS5376A
CHARACTERISTICS SPECIFICATIONS
characteristics specifications guaranteed over Specified Operating Conditions. Typical performance characteristics specifications derived from measurements taken nominal supply voltages 25°C. GND, GND1, GND2 voltages with respect
SPECIFIED OPERATING CONDITIONS
Parameter Logic Core Power Supply Microcontroller Interface Power Supply Modulator Interface Power Supply Ambient Operating Temperature Industrial (-IQ) Symbol VDD1 VDD2 2.85 3.135 3.135 5.25 5.25 5.25 Unit
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supplies Logic Core Microcontroller Interface Modulator Interface (Note (Note (Note Symbol VDD1 VDD2 IOUT VIND TSTG -0.3 -0.3 -0.3 -0.5 VDD+0.5 Units
Input Current, Except Supplies Input Current, Power Supplies Output Current Power Dissipation Digital Input Voltages Ambient Operating Temperature (Power Applied) Storage Temperature Range
Transient currents will cause latch-up.
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CS5376A
THERMAL CHARACTERISTICS
Parameter Allowable Junction Temperature Junction Ambient Thermal Impedance Ambient Operating Temperature (Power Applied) Symbol Unit
DIGITAL CHARACTERISTICS
Parameter High-Level Input Drive Voltage Low-Level Input Drive Voltage High-Level Output Drive Voltage Low-Level Output Drive Voltage Rise Times, Digital Inputs Fall Times, Digital Inputs Rise Times, Digital Outputs Fall Times, Digital Outputs Input Leakage Current 3-State Leakage Current Digital Input Capacitance Digital Output Capacitance (Note Iout Iout Symbol tRISE tFALL tRISE tFALL COUT Unit
Notes: leakage pins with pull-up resistors (TRST, TMS, TDI, SSI, GPIO, MOSI, SCK1) ±250
rise fallo
rise
llin
VDDV
POWER CONSUMPTION
Parameter Operational Power Consumption 1.024 Digital Filter Clock 2.048 Digital Filter Clock 4.096 Digital Filter Clock 8.192 Digital Filter Clock 16.384 Digital Filter Clock Standby Power Consumption Digital Filter Clock, Filter Stopped PWRS PWR1 PWR2 PWR4 PWR8 PWR16 Symbol Unit
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CS5376A
SWITCHING CHARACTERISTICS
Interface Timing (External Master)
MOSI
SCK1 SCLK
Figure MOSI Write Timing Slave Mode
MISO
SCK1 SCLK
Figure MISO Read Timing Slave Mode
Parameter MOSI Write Timing Enable Valid Latch Clock Data Set-up Time Prior SCK1 Rising Data Hold Time After SCK1 Rising SCK1 High Time SCK1 Time SCK1 Falling Prior Disable MISO Read Timing SCK1 Falling Data SCK1 High Time SCK1 Time Rising MISO Hi-Z
Symbol
Unit
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CS5376A
SWITCHING CHARACTERISTICS
Serial Data Port Port)
SDRDY SDCLK
SDDAT SDTKI SDTKO
Figure Port Read Timing
Parameter SDTKI SDRDY Falling Edge SDTKI High Time Width SDRDY Falling Edge SDCLK Falling Edge Data Setup Time Prior SDCLK Rising Data Hold Time After SDCLK Rising SDCLK High Time SDCLK Time SDCLK Rising SDRDY Rising Data Hold Time After SDRDY Rising SDRDY High SDTKO Rising Edge SDTKO High Time
Symbol
1000
Unit
DS612F3
CS5376A
SWITCHING CHARACTERISTICS
CLK, SYNC, MCLK, MSYNC, MDATAx
SYNC
MCLK
MSYNC tmsd MDATAx
tmsh
tmsd Data1 Data2
Note: SYNC input latched MCLK rising edge. MSYNC output triggered MCLK falling edge.
fMCLK 2.048 1.024
tmsd TMCLK tmsh TMCLK
tmsd tmsh
tmsd tmsh
Figure SYNC, MCLK, MSYNC, MDATA Interface Timing
Parameter Master Clock Frequency Master Clock Duty Cycle Master Clock Rise Time Master Clock Fall Time Master Clock Jitter Synchronization after SYNC rising MSYNC Setup Time MCLK rising MCLK rising Valid MDATA MSYNC falling MCLK rising (Note (Note
Symbol tRISE tFALL SYNC tmsr tmdv tmsf
32.768
Unit
Notes: Master clock frequencies above below 32.768 will affect generated clock frequencies. Sampling synchronization between multiple CS5376A devices receiving identical SYNC signals.
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CS5376A
SWITCHING CHARACTERISTICS
Test Stream (TBS)
TBSCLK TBSDATA
MCLK
Note: Example timing shown output rate programmable delays.
Figure Output Clock Data Timing
Parameter Clock Timing Clock Period Clock High Time Clock Time Data Output Timing Data Rate Data Rising Clock Rising Setup Time Clock Rising Data Falling Hold Time (Note (Note
Symbol
3.906
Unit kbps
TBSCLK phase delayed increments. timing diagram shows TBSCLK delay. TBSDATA delayed from full periods. timing diagram shows TBSDATA delay.
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CS5376A
Geophone Hydrophone Sensor
CS3301 CS3302
CS5371 CS5372
odulator
System Telem etry
Geophone Hydrophone Sensor
CS3301 CS3302
CS5376A
µController Configuration EEPROM
Digital Filter
Geophone Hydrophone Sensor
CS3301 CS3302
CS5371 CS5372
odulator
Comm unication Interface
Geophone Hydrophone Sensor
CS3301 CS3302
CS4373A
itch SwUX itch
Test
Figure Multi-Channel System Block Diagram
SYSTEM DESIGN WITH CS5376A
Figure illustrates simplified block diagram CS5376A multi-channel measurement system. four differential sensors connected through CS3301/02 differential amplifiers CS5371/72 modulators, where analog digital conversion occurs. Each modulators 1-bit output connects CS5376A MDATA input, where oversampled data decimated filtered 24-bit output samples programmed output rate. These output samples buffered 8-deep data FIFO passed system telemetry command. System self tests performed connecting CS5376A test stream (TBS) generator CS4373A test DAC. Analog tests drive differential signals from CS4373A test into multiplexed inputs CS3301/02 amplifiers diDS612F3
rectly sensors through external analog switches. Digital loopback tests internally connect digital output directly CS5376A modulator inputs.
Power Supplies
multi-channel system shown Figure typically operates from ±2.5 analog power supply digital power supply. CS5376A logic core powered from minimize power consumption, required.
Reset Control
System reset required only CS5376A device, standard active signal that generated power supply monitor microcontroller. Other system devices default powerdown state when CS5376A reset.
CS5376A
Clock Generation
single 32.768 low-jitter clock input, which generated from VCXO based PLL, required drive CS5376A device. Clock inputs other system devices driven clock outputs from CS5376A.
Data Collection
Data collected from CS5376A through Serial Data port port). Automatically upon request, depending SDTKI connected, port initiates serial transactions transfer 32-bit data from output FIFO system telemetry. output FIFO eight data locations permit latency data collection.
Synchronization
Digital filter phase analog sample timing four modulators connected CS5376A synchronized rising edge SYNC pin. synchronization signal received identically CS5376A devices measurement network, synchronous sampling across network guaranteed.
Integrated peripherals
Test Stream (TBS) digital signal generator built into CS5376A produces 1-bit sine wave impulse function. This digital test stream connected CS4373A test create high quality analog test signals internally looped back CS5376A MDATA inputs test digital filter data collection circuitry. Time Break Timing information recorded during data collection strobing TIMEB pin. dedicated flag sample status bits, high indicate over which measurement timing event occurred. General Purpose (GPIO) Twelve general purpose pins available CS5376A system control. Each input output, high low, with internal pullup enabled disabled. CS3301/02, CS5371/72 CS4373A devices Figure configured simple settings controlled through CS5376A GPIO pins. Serial Peripheral Interface (SPI secondary master mode serial port communicate with external serial peripherals. JTAG Port Boundary scan JTAG IEEE 1149.1 compliant.
System Configuration
Through serial port, filter coefficients digital filter register settings either programmed microcontroller automatically loaded from external EEPROM after reset. System configuration only required CS5376A device, other devices configured CS5376A General Purpose pins. registers digital filter, SYSTEM1 SYSTEM2 (0x2C, 0x2D), provided user defined system information. These general purpose registers that will hold 24-bit data values written them.
Digital Filter Operation
After analog digital conversion occurs modulators, oversampled 1-bit data read into CS5376A through MDATA pins. digital filter then processes data through enabled filter stages, decimating 24-bit words programmed output word rate. final 24-bit samples concatenated with 8-bit status words placed into output FIFO.
DS612F3
CS5376A
TRST TBSCLK TBSDATA VDD2 MCLK/2 MCLK MSYNC MDATA4 MFLAG4
VDD1 Ring Ring Ring VDD2 Ring
SDTKI SDTKO SDCLK SDRDY SDDAT SYNC TIMEB BOOT RESET VDD1 GND1 SINT MOSI MISO
CS5376A
SCK1 GPIO11:EECS GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GND2 GPIO5 GPIO4:CS4 GPIO3:CS3 GPIO2:CS2 GPIO1:CS1
Figure Power Supply Block Diagram
POWER SUPPLIES
CS5376A three sets power supply inputs. sets supply power pins device (VDD1, VDD2), third supplies power logic core (VD). power supplies determine maximum input output voltages when interfacing peripherals, logic core power supply largely determines power consumption CS5376A.
GPIO6 GPIO11:EECS SSO, SCK1, SSI, MISO, MOSI, SINT, RESET, BOOT, TIMEB, CLK, SYNC SDDAT, SDRDY, SDCLK, SDTKO, SDTKI
Descriptions
VDD1, GND1 Pins 54,53 Sets interface voltage microcontroller system telemetry. driven with voltages from VDD1 powers pins 41-64:
TRST, TMS, TCK, TDI,
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MDATA3 MFLAG3 MDATA2 MFLAG2 MDATA1 MFLAG1 GND2 VDD2 SCK2 GPIO0:CS0
VDD2, GND2 Pins Sets interface voltage modulators, test DAC, serial peripherals. driven with voltages from VDD2 powers pins 8-37:
TBSCLK, TBSDATA MCLK/2, MCLK, MSYNC MDATA1 MDATA4 MFLAG1 MFLAG4 SI4, SCK2 GPIO0:CS0 GPIO5
CS5376A
Pins Sets operational voltage CS5376A logic core. driven with voltages from supply minimizes total power consumption. (X7R, C0G), tantalum, other good quality dielectric type.
Power Consumption
Power consumption CS5376A depends primarily power supply voltage logic core (VD) programmed digital filter clock rate. Digital filter clock rates selected based required output word rate explained "Digital Filter Initialization" page
Bypass Capacitors
Each power supply should bypassed with parallel 0.01 caps, single cap, placed close possible CS5376A. Bypass capacitors should ceramic
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CS5376A
RESET
Self-Tests
BOOT
SELFTEST Register
EEPROM Boot
µController Boot
Figure Reset Control Block Diagram
RESET CONTROL
CS5376A reset signal active low. When released, series self-tests performed device either actively boots from external EEPROM enters idle state waiting microcontroller configuration. combined into SELFTEST register (0x2F), with 0x0AAAAA indicating passed. Self-tests require complete, after which configuration commands serviced.
Boot Configurations Descriptions
RESET Reset input, active low. BOOT Boot mode select, latched following RESET rising edge. BOOT EEPROM boot BOOT Microcontroller boot logic state BOOT after reset determines CS5376A actively reads configuration information from EEPROM enters idle state waiting microcontroller write configuration commands. EEPROM Boot When BOOT high after reset, CS5376A actively reads data from external serial EEPROM then begins operation specified configuration. Configuration commands data encoded EEPROM specified `Configuration EEPROM' section this data sheet, starting page Microcontroller Boot When BOOT after reset, CS5376A enters idle state waiting microcontroller write configuration commands initialize filter operation. Configuration commands data written specified `Configuration Microcontroller' section this data sheet, starting page
Reset Self-Tests
After RESET released before booting, series digital filter self-tests run. Results
Self-Test Type Program Data Program Data Execution Unit Pass Code 0x00000A 0x0000A0 0x000A00 0x00A000 0x0A0000 Fail Code 0x00000F 0x0000F0 0x000F00 0x00F000 0x0F0000
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CS5376A
Clock Divider MCLK Generator
Internal Clocks MCLK Output
DSPCFG Register
Figure Clock Generation Block Diagram
CLOCK GENERATION
CS5376A requires 32.768 master clock input, which used generate internal digital filter clocks external modulator clocks. ensure recovered clocks have identical phase, system designs should phase/frequency detector architecture.
Description
Clock input, nominal frequency 32.768 MHz.
Master Clock Jitter Skew
Care must taken minimize jitter skew received master clock both parameters affect measurement performance. Jitter master clock causes jitter generated modulator clocks, resulting sample timing errors increased noise. Skew master clock from node node creates sample timing offset, resulting systematic measurement errors reconstructed signal.
Synchronous Clocking
guarantee synchronous measurements throughout sensor network, CS5376A master clock should distributed arrive nodes phase. 32.768 master clock either directly distributed through system telemetry, reconstructed locally using VCXO based PLL.
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CS5376A
SYNC MSYNC Generator
Digital Filter
Test Stream
MSEN
MSYNC Output
TSYNC
Figure Synchronization Block Diagram
SYNCHRONIZATION
CS5376A dedicated SYNC input that aligns internal digital filter phase generates external signal synchronizing modulator analog sampling. providing simultaneous rising edges SYNC pins multiple CS5376A devices, synchronous sampling across network guaranteed. phase. Filter convolutions restart, next output word available full sample period later. Repetitive synchronization supported when SYNC events occur exactly selected output word rate. this case, re-synchronization occurs start convolution cycle when digital filter state machine already reset.
Description
SYNC Synchronization input, rising edge triggered.
Modulator Synchronization
external MSYNC signal phase aligns modulator analog sampling when connected CS5371/72 MSYNC input. This ensures synchronous analog sampling relative MCLK. Repetitive synchronization modulators supported when SYNC events occur exactly selected output word rate. this case, synchronization will occur start analog sampling.
MSYNC Generation
SYNC signal rising edge used generate retimed synchronization signal, MSYNC. MSYNC signal reinitializes internal digital filter phase driven onto MSYNC output phase align modulator analog sampling. MSEN digital filter CONFIG register (0x00) enables MSYNC generation. "Modulator Interface" page more information about MSYNC.
Test Stream Synchronization
When test stream generator enabled, MSYNC signal reset internal data pointer. This restarts test stream from first data point establish known output signal phase. TSYNC digital filter TBSCFG register (0x2A) enables synchronization test stream MSYNC. When TSYNC disabled, test stream phase affected MSYNC.
Digital Filter Synchronization
internal MSYNC signal resets digital filter state machine establish known digital filter
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CS5376A
HOLD
GPIO11:EECS SCK1
CS5376A
MISO MOSI
AT25640
Figure EEPROM Configuration Block Diagram
CONFIGURATION EEPROM
After reset, CS5376A reads state BOOT determine source configuration commands. BOOT high, CS5376A initiates serial transactions through port read configuration information from external EEPROM. Figure read configuration commands data. 8-bit opcodes 16-bit addresses combined read back 8-bit configuration commands 24-bit configuration data. System design should include connection configuration EEPROM in-circuit reprogramming. CS5376A pins high impedance when inactive support external connections serial bus.
Descriptions
Pins required EEPROM boot listed here, other pins inactive. GPIO11:EECS EEPROM chip select output, active low. SCK1 Serial clock output, nominally 1.024 MHz. MOSI Serial data output pin. Valid rising edge SCK1, transition falling edge. MISO Serial data input pin. Valid rising edge SCK1, transition falling edge.
EEPROM Organization
boot EEPROM holds 8-bit commands 24-bit data required initialize CS5376A into operational state. Configuration information starts memory location 0x10, with addresses 0x00 0x0F free manufacturing header information. first serial transaction reads 1-byte command from memory location 0x10 then, depending command type, reads multiple 3-byte data words complete command. Command data reads continue until `Filter Start' command recognized. maximum number bytes that written single configuration approximately
EEPROM Hardware Interface
When booting from EEPROM CS5376A port actively performs serial transactions, shown
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CS5376A
Instruction Read 0x03
Opcode
Address ADDR[15:0]
Definition Read data beginning address given ADDR.
Read from EEPROM
READ 0x03 BYTE ADDR ADDR ADDR
MOSI
MISO
DATA1 DATA2 DATA3 BYTE BYTE DATA
EECS
Cycle
SCK1
MOSI
MISO
EECS
Figure EEPROM Read Transactions
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CS5376A
Write Register 0x01 This EEPROM command writes data value specified digital filter register. Digital filter registers control hardware peripherals filtering functions. "Digital Filter Registers" page definitions digital filter registers.
0000h 0010h
Header 8-bit Command 24-bit Data 8-bit Command 24-bit Data
EEPROM Manufacturing Information EEPROM Command Data Values
Sample Command:
Write digital filter register 0x00 with data value 0x070431. Then write 0x20 with data 0x000240. Write Coefficients 0x02 This EEPROM command writes custom coefficients FIR1 FIR2 filters. first data words number FIR1 FIR2 coefficients written. remaining data words concatenated FIR1 FIR2 coefficients. maximum coefficients written each filter, though available digital filter computation cycles will limit their practical size. "FIR Filter" page more information about filter coefficients.
1FFFh
Figure Kbyte EEPROM Memory Organization
KByte Kbit), which includes command overhead:
Memory Requirement
Bytes
Digital Filter Registers (22) Coefficients (255+255) Coefficients (3+5) Test Stream Data (1024) `Filter Start' Command Total Bytes
1537 3076 4793
Sample Command:
Write FIR1 coefficients 0x00022E, 0x000771 then FIR2 coefficients 0xFFFFB9, 0xFFFE8D.
Table Maximum EEPROM Configuration
Supported serial configuration EEPROMs mode (0,0) compatible, 16-bit addresses, 8bit data, larger than KByte KBit). ATMEL AT25640, AT25128, similar serial EEPROMs recommended.
EEPROM Configuration Commands
summary available EEPROM commands shown Table
Write Coefficients 0x03 This EEPROM command writes custom coefficients stage filter. architecture number coefficients fixed, eight data words containing coefficient values always immediately follow command byte. coefficient write order a11, b10, b11, a21, a22, b20, b21, b22. "IIR Filter" page more information about filter coefficients.
DS612F3
CS5376A
Sample Command:
Write IIR1 coefficients 0x84BC9D, 0x7DA1B1, 0x825E4F, IIR2 coefficients 0x83694F, 0x3CAD5F, 0x3E5104, 0x835DF8, 0x3E5104. Write Coefficients 0x04 This EEPROM command selects on-chip coefficients FIR1, FIR2, order, order filters digital filter. data word required select which internal coefficient sets use. "Filter Coefficient Selection" page information about selecting on-chip coefficient sets.
Sample Command:
Select IIR1 IIR2 low-cut coefficients, with FIR1 FIR2 linear phase highcut coefficients. Data word 0x002200. Write Data 0x05 This EEPROM command writes custom data test stream (TBS) generator. This command, along with ability program test stream generator interpolation clock rate, create custom frequency test signals. first data word sets number data written remaining data words data values. "Test Stream Generator" page information about using custom test stream data sets.
Name WRITE REGISTER WRITE COEFFICIENTS
8-bit
DATA 24-bit DATA FIR1 FIR2 (FIR COEF) COEF (TBS DATA) Operation
Description
Write Digital Filter Register Write Custom Coefficients
WRITE COEFFICIENTS
Write Custom Coefficients
WRITE COEFFICIENTS WRITE DATA WRITE FILTER START
On-Chip Coefficients Write Custom Test Stream Data On-Chip Data Start Digital Filter Operation
(DATA) indicates multiple words this type written.
Table EEPROM Boot Configuration Commands
DS612F3
CS5376A
Sample Command:
Write test stream data 0x000000, 0x0007DA, 0x000FB5, 0x00178F. Write Data 0x06 This EEPROM command selects on-chip test stream (TBS) data generator. data words required this EEPROM command. "Test Stream Generator" page more information about on-chip test stream data set.
Sample Command:
Filter Start 0x07 This EEPROM command initializes starts digital filter. Measurement data becomes available full sample period after this command received. data words required this EEPROM command.
Sample Command:
Example EEPROM Configuration
Table shows example EEPROM file minimal CS5376A configuration.
DS612F3
CS5376A
Addr
Data
Description header
Addr
Data
Description
Write TBSCFG Register
Write TBSGAIN Register
Write Coefficients
Filter Start
Write Data Write CONFIG Register
Write FILTCFG Register
Table Example EEPROM File
DS612F3
CS5376A
Digital Filter Command Interpreter
Registers
Logic
SCK1 MOSI MISO SINT
Figure Serial Peripheral Interface (SPI Block Diagram
CONFIGURATION MICROCONTROLLER
After reset, CS5376A reads state BOOT determine source configuration commands. BOOT low, CS5376A receives configuration commands from microcontroller.
Microcontroller Hardware Interface
When booting from microcontroller CS5376A port receives configuration commands configuration data through serial transactions, shown Figure 8-bit opcodes 8-bit addresses combined read write 24-bit configuration commands data. Microcontroller serial transactions require toggling CS5376A chip select writing serial clock SCK1 input. Serial data input CS5376A MOSI pin, output from CS5376A MISO pin.
Descriptions
Pins required microcontroller boot listed here, other pins inactive. Slave select input pin, active low. Serial chip select input from microcontroller. SCK1 Serial clock input pin. Serial clock input from microcontroller, maximum 4.096 MHz. MOSI Serial data input pin. Valid rising edge SCK1, transition falling edge. MISO Serial data output pin. Valid rising edge SCK1, transition falling edge. Open drain output requiring pull-up resistor. SINT Serial interrupt output pin, active low. active pulse output when ready next serial transaction.
Microcontroller Serial Transactions
Microcontroller configuration commands written digital filter through registers. 24-bit command 24-bit data words written registers single serial transaction. Some commands require additional data words through additional serial transactions complete. 9.3.1 opcodes microcontroller communicates with CS5376A port using standard 8-bit opcodes 8-bit address. standard `Read' `Write' opcodes listed Figure
DS612F3
CS5376A
Instruction Write Read
Opcode 0x02 0x03
Address ADDR[7:0] ADDR[7:0]
Definition Write registers beginning address ADDR. Read registers beginning address ADDR.
Microcontroller Write
MOSI
0x02
ADDR
Data1
Data2
DataN
MISO
Microcontroller Read from
MOSI
0x03
ADDR
MISO
Data1
Data2
DataN
Cycle
SCK1
MOSI
MISO
Figure Microcontroller Serial Transactions
DS612F3
CS5376A
9.3.2 registers registers shown Figure 24-bit registers mapped into 8-bit register space high, mid, bytes. "SPI Registers" page definitions registers. 9.3.3 transactions serial transaction registers starts with opcode, followed address, then some number data bytes written read starting that address. Typical serial write transactions require sending groups total bytes SPI1CMD SPI1DAT1 registers. Example 5-byte write transaction SPI1CMD Example 5-byte write transaction SPI1DAT1 Example 8-byte write transaction SPI1CMD Example 8-byte write transaction SPI1DAT1 Example 11-byte write transaction SPI1CMD Typical serial read transactions require groups bytes, split between writing into MOSI reading from MISO. 3-byte read transaction mid-byte SPI1CTRL MOSI: MISO: 5-byte read transaction SPI1DAT1 MOSI: MISO: 9.3.4 Multiple serial transactions Some configuration commands require multiple serial transactions complete. There must small delay between transactions CS5376A process incoming data. Three methods used ensure CS5376A ready receive next configuration command. Delay fixed period guarantee enough time command completed. Monitor SINT active pulse. This pulse output occurs once CS5376A completes processing current command. Verify status E2DREQ reading SPI1CTRL register. When low, CS5376A ready next command. 9.3.5 Polling E2DREQ transaction type that always performed matter delay from previous configuration command reading E2DREQ mid-byte SPI1CTRL register. 3-byte read transaction. MOSI: MISO: E2DREQ high MISO: E2DREQ
Name SPI1CTRL SPI1CMD SPI1DAT1 SPI1DAT2
Addr.
Type
Bits Control Command Data Data
Description
Figure Registers
DS612F3
CS5376A
E2DREQ reads high while configuration command being processed. When low, digital filter ready receive configuration command.
Sample Command:
Write digital filter register 0x00 with data value 0x070431. Then write 0x20 with data 0x000240. Delay monitor SINT, poll E2DREQ
Microcontroller Configuration Commands
summary available microcontroller configuration commands listed Table Write Register 0x01 This configuration command writes specified digital filter register. Digital filter registers control hardware peripherals filtering functions. "Digital Filter Registers" page definitions digital filter registers.
Delay monitor SINT, poll E2DREQ Read Register 0x02 This command reads specified digital filter register. register value requested first transaction, with register value copied SPI1DAT1 read subsequent transaction.
Sample Command:
Read digital filter registers 0x00 0x20.
Name WRITE REGISTER READ REGISTER WRITE COEFFICIENTS WRITE COEFFICIENTS
24-bit 000000 000001 000002 000003 000004
DAT1 24-bit [DATA] FIR1 (FIR COEF) COEF (TBS DATA)
DAT2 24-bit DATA FIR2 (FIR COEF) (TBS DATA)
Description Operation Write Digital Filter Register Read Digital Filter Register Write Custom Coefficients Write Custom Coefficients
WRITE COEFFICIENTS WRITE DATA WRITE FILTER START FILTER STOP
000005 000006 000007 000008 000009
On-Chip Coefficients Write Custom Test Stream Data On-Chip Data Start Digital Filter Operation Stop Digital Filter Operation
[DATA] indicates data word returned from digital filter. (DATA) indicates multiple words this type written.
Table Microcontroller Boot Configuration Commands
DS612F3
CS5376A
Delay monitor SINT, poll E2DREQ MOSI: MISO: Delay monitor SINT, poll E2DREQ MOSI: MISO: Write Coefficients 0x03 This command writes custom coefficients FIR1 FIR2 filters. first data words number FIR1 FIR2 coefficients written. remaining data words concatenated FIR1 FIR2 coefficients. maximum coefficients written each filter, though available digital filter computation cycles will limit their practical size. "FIR Filter" page more information about filter coefficients.
Sample Command:
Write IIR1 coefficients 0x84BC9D, 0x7DA1B1, 0x825E4F, IIR2 coefficients 0x83694F, 0x3CAD5F, 0x3E5104, 0x835DF8, 0x3E5104. Delay monitor SINT, poll E2DREQ Delay monitor SINT, poll E2DREQ Delay monitor SINT, poll E2DREQ Delay monitor SINT, poll E2DREQ Write Coefficients 0x05 This configuration command selects on-chip coefficients FIR1, FIR2, order, order filters digital filter. data word required select which internal coefficient sets use. "Filter Coefficient Selection" page information about selecting on-chip coefficient sets.
Sample Command:
Write FIR1 coefficients 0x00022E, 0x000771 then FIR2 coefficients 0xFFFFB9, 0xFFFE8D. Delay monitor SINT, poll E2DREQ Delay monitor SINT, poll E2DREQ Delay monitor SINT, poll E2DREQ Write Coefficients 0x04 This command writes custom coefficients stage filter. architecture number coefficients fixed, eight coefficient values immediately follow this command. coefficient write order a11, b10, b11, a21, a22, b20, b21, b22. "IIR Filter" page more information about filter coefficients.
Sample Command:
Select IIR1 IIR2 low-cut coefficients, with FIR1 FIR2 linear phase highcut coefficients. Data word 0x002200. Delay monitor SINT, poll E2DREQ Write Data 0x06 This command writes custom data test stream (TBS) generator. This command, along with ability program test stream generator interpolation clock rate, create custom frequency test signals. first data word sets number data written remaining data words data values. "Test Stream Generator"
DS612F3
CS5376A
page information about using custom test stream data sets. Filter Start 0x08 This command initializes starts digital filter. Measurement data becomes available full sample period after this command issued. data words required this configuration command.
Sample Command:
Write test stream data 0x000000, 0x0007DA, 0x000FB5, 0x00178F. Delay monitor SINT, poll E2DREQ Delay monitor SINT, poll E2DREQ Delay monitor SINT, poll E2DREQ Write Data 0x07 This command selects on-chip test stream (TBS) data generator. data words required this configuration command. "Test Stream Generator" page information about on-chip test stream data set.
Sample Command:
Delay monitor SINT, poll E2DREQ Filter Stop 0x09 This command disables digital filter. Measurement data output stops immediately after this command issued. data words required this configuration command.
Sample Command:
Delay monitor SINT, poll E2DREQ
Sample Command:
Delay monitor SINT, poll E2DREQ
Example Microcontroller Configuration
Table shows example microcontroller transactions minimal CS5376A configuration.
DS612F3
CS5376A
Transaction
Data Delay 1ms, monitor SINT, poll E2DREQ Delay 1ms, monitor SINT, poll E2DREQ Delay 1ms, monitor SINT, poll E2DREQ Delay 1ms, monitor SINT, poll E2DREQ Delay 1ms, monitor SINT, poll E2DREQ Delay 1ms, monitor SINT, poll E2DREQ
Description Write coefficients
Write Data
Write CONFIG Register
Write FILTCFG Register
Write TBSCFG Register
Write TBSGAIN Register
Filter Start
Table Example Microcontroller Configuration
DS612F3
CS5376A
MCLK MCLK/2 MSYNC MDATA[4:1] MFLAG[4:1]
MCLK MSYNC Generate Input
SYNC
SINC Filter
Filters
Filter
Offset Gain Correction
Output High Speed Serial Data Port Port) Output Rate 4000
Figure Modulator Data Interface
10.MODULATOR INTERFACE
CS5376A performs digital filtering four modulators. Signals from modulators connected through modulator data interface (MDI).
10.2 Modulator Clock Generation
MCLK MCLK/2 outputs low-jitter, low-skew modulator clocks generated from 32.768 master clock. MCLK typically operates 2.048 unless analog low-power modes require 1.024 modulator clock. MCLK/2 always produces clock half selected MCLK rate. MCLK rate selected MCLK MCLK/2 outputs enabled bits digital filter CONFIG register (0x00). default MCLK MCLK/2 disabled driven low.
10.1 Descriptions
MCLK, MCLK/2 Pins Modulator clock outputs. Nominally 2.048 1.024 MHz. MSYNC Modulator synchronization signal output. Generated from SYNC input. MDATA1 MDATA4 Pins Modulator data inputs, nominally kbit/s. MFLAG1 MFLAG4 Pins Modulator flag inputs. Driven high when modulator unstable analog over-range signal.
10.3 Modulator Synchronization
MSYNC output signal follows input SYNC pin. MSYNC phase aligns modulator sampling instant guarantee synchronous analog sampling across measurement network. MSYNC enabled CONFIG register (0x00). default SYNC inputs cause MSYNC output.
DS612F3
CS5376A
10.4 Modulator Data Inputs
MDATA input expects 1-bit data rate. input rate selected CONFIG register (0x00). default, MDATA expected kHz. MDATA input one's density designed full scale positive full scale negative 14%, with absolute maximum over-range capability These inputs decimated filtered digital filter create 24bit samples output rate.
10.5 Modulator Flag Inputs
high MFLAG input signal indicates corresponding modulator become unstable analog over-range input signal. Once over-range signal reduced, modulator recovers stability MFLAG signal cleared. MFLAG inputs mapped status bits port, associated with each sample when written. "Serial Data Port" page more information MFLAG error bits port status byte.
DS612F3
CS5376A
Modulator Input
SINC Filter 64000
FIR1
FIR2
IIR1 Order
IIR2 Order
Offset Gain Correction
Output High Speed Serial Data Port Port) Output Rate 4000
Figure Digital Filter Stages
11.DIGITAL FILTER INITIALIZATION
CS5376A digital filter consists three multistage sections: three stage SINC filter, stage filter, stage filter. initialize digital filter, coefficient sets selected using configuration commands, FILTCFG register (0x20) written select output filter stage, output word rate, number enabled channels. digital filter clock rate selected writing CONFIG register (0x00). word, available coefficient sets each selection. Characteristics on-chip digital filter coefficients discussed `SINC Filter', `FIR Filter', `IIR Filter' sections this data sheet.
11.2 Filter Configuration Options
Digital filter parameters selected bits FILTCFG register (0x20), digital filter clock rate selected bits CONFIG register (0x00). 11.2.1 Output Filter Stage digital filter output data following stage filter chain. output filter stage selected FSEL bits FILTCFG register. Taking data from SINC FIR1 filter stages reduces overall decimation filter chain increases output rate, discussed following section. Taking data from FIR2, IIR1, IIR2, IIR3 results data selected rate.
11.1 Filter Coefficient Selection
Selection SINC filter coefficients required they selected automatically based programmed output word rate. Digital filter coefficients selected using `Write Coefficients' `Write Coefficients', `Write Coefficients' configuration commands. When writing coefficients from ROM, data word selects on-chip coefficient each filter stage. Figure shows format coefficient selection
DS612F3
CS5376A
Bits Selection
23:20 0000
19:16 0000
15:12 IIR2
11:8 IIR1
FIR2
FIR1
Bits 15:12 0000 0001 0010 0011 0100
IIR2 Coefficients 2000 1000
Bits 11:8 0000 0001 0010 0011 0100
IIR1 Coefficients 2000 1000
Bits 0000 0001
FIR1 Coefficients Linear Phase Minimum Phase
Bits 0000 0001
FIR2 Coefficients Linear Phase Minimum Phase
Figure Coefficient Selection Word
11.2.2 Output Word Rate CS5376A digital filter supports output word rates (OWRs) between 4000 SPS. output word rate selected bits FILTCFG register. When taking data directly from SINC filter, decimation FIR1 FIR2 stages bypassed actual output word rate multiplied factor eight compared with register selection. When taking data directly from FIR1, decimation FIR2 stage bypassed actual output word rate multiplied factor two. Data taken from FIR2, IIR1, IIR2, IIR3 filtering stages output selected rate. 11.2.3 Channel Enable Digital filtering performed simultaneously four modulators. number enabled channels selected bits FILTCFG register. Channels enabled sequentially. Selecting channel operation enables channel only, selecting channel operation enables channels
lecting three channel operation enables channels selecting four channel operation enables four channels. 11.2.4 Digital Filter Clock digital filter clock rate programmable between 16.384 bits CONFIG register. Computation Cycles minimum digital filter clock rate configuration depends computation cycles required complete digital filter convolutions selected output word rate. configurations work maximum digital filter clock, lower clock rates consume less power. Standby Mode CS5376A placed low-power standby mode sending `Filter Stop' configuration command programming digital filter clock kHz. this mode digital filter idles, consuming minimal power until re-enabled later configuration commands.
DS612F3
CS5376A
1-bit Input
order sinc1
order sinc2 stage1
order sinc2 stage2
order sinc2 stage3
order sinc2 stage4
order sinc3 stage1
order sinc3 stage2
order sinc3 stage3
order sinc3 stage4
order sinc3 stage5
order sinc3 stage6
24-bit Output
Figure SINC Filter Block Diagram
12.SINC FILTER
SINC filters primary purpose attenuate out-of-band noise components from modulators. While doing they decimate 1-bit data into lower frequency 24-bit data suitable filters. SINC filter three cascaded sections, SINC1, SINC2, SINC3, which each made smaller stages shown Figure selected output word rate FILTCFG register automatically determines coefficients decimation ratios selected SINC filters. Once SINC filter configuration set, enabled channels filtered decimated using identical hardware algorithm.
12.2 SINC2 Filter
second section SINC2, multi-stage, variable order, variable decimation SINC filter. Depending selected output word rate FILTCFG register, different cascaded SINC2 stages enabled, shown Table
12.3 SINC3 Filter
last section SINC3, flexible multi-stage variable order, variable decimation SINC filter. Depending selected output word rate FILTCFG register, different SINC3 stages enabled, shown Table
12.4 SINC Filter Synchronization 12.1 SINC1 Filter
first section SINC1, single stage order fixed decimate SINC filter. This SINC filter decimates incoming 1-bit stream from modulators down rate. SINC filter synchronized external system MSYNC signal, which generated from SYNC input. MSYNC signal sets reference time (time filter operations, SINC filter restarted phase align with this reference time.
DS612F3
CS5376A
SINC1 Single stage, fixed decimate order decimate coefficients SINC2 Multi-stage, variable decimation Stage Stage Stage Stage order order order order decimate decimate decimate decimate coefficients coefficients coefficients coefficients
SINC3 Multi-stage, variable decimation Stage Stage Stage Stage Stage Stage order order order order order order decimate decimate decimate decimate decimate decimate coefficients coefficients coefficients coefficients coefficients coefficients
Figure SINC Filter Stages
SINC filters
FIR2 Output Word Rate 4000 2000 1000 Setting SINC1 Decimation SINC2 Decimation SINC2 Stages SINC3 Decimation SINC3 Stages
0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000
2,3,4 1,2,3,4 2,3,4 1,2,3,4 1,2,3,4 2,3,4 1,2,3,4 2,3,4 1,2,3,4 1,2,3,4
3,4,5 3,4,5 3,4,5 2,3,4,5 3,4,5 2,3,4,5 2,3,4,5 2,3,4,5 1,2,3,4,5
Table SINC Filter Configurations
DS612F3
CS5376A
Filter Type SINC1 order decimate coefficients
System Function
Filter Coefficients 1190 1470 1750 2010 2226 2380 2460 2460 2380 2226 2010 1750 1470 1190
Filter Type SINC2 (Stage SINC2 (Stage order decimate coefficients
System Function
Filter Coefficients
SINC2 (Stage order decimate coefficients
SINC2 (Stage order decimate coefficients
Table SINC1 SINC2 Filter Coefficients
DS612F3
CS5376A
Filter Type SINC3 (Stage SINC3 (Stage SINC3 (Stage order decimate coefficients
System Function
Filter Coefficients
SINC3 (Stage order decimate coefficients
SINC3 (Stage order decimate coefficients
SINC3 (Stage order decimate coefficients
Table SINC3 Filter Coefficients
DS612F3
CS5376A
FIR1 Filter decimate
FIR2 Filter decimate
Figure Filter Block Diagram
13.FIR FILTER
finite impulse response (FIR) filter block consists cascaded stages, FIR1 FIR2. compensates SINC filter droop creates low-pass corner block aliased components input signal. On-chip linear phase minimum phase coefficients selected using configuration command, coefficients programmed custom filter response.
13.2 FIR2 Filter
FIR2 filter stage decimate architecture. creates low-pass brick wall filter block aliased components input signal. on-chip linear minimum phase coefficient sets 126-tap, with maximum programmable coefficients. coefficients normalized 24-bit two's complement full scale, 0x7FFFFF. characteristic equation FIR2 convolution input values, X(n), filter coefficients, h(k), produce output value, [h(k)*X(n-k)] [h(k+1)*X(n-(k+1))]
13.1 FIR1 Filter
FIR1 filter stage decimate four architecture. compensates SINC filter droop flattens magnitude response pass band. on-chip linear minimum phase coefficient sets 48-tap, with maximum programmable coefficients. coefficients normalized 24-bit two's complement full scale, 0x7FFFFF. characteristic equation FIR1 convolution input values, X(n), filter coefficients, h(k), produce output value, [h(k)*X(n-k)] [h(k+1)*X(n-(k+1))]
13.3 On-Chip Coefficients
sets on-chip linear phase minimum phase coefficients available FIR1 FIR2. Performance on-chip coefficient sets very good, with excellent ripple stop band characteristics described Figure Table Which on-chip coefficient selected data word following `Write Coefficients' configuration command. "Filter Coefficient Selection" page information about selecting on-chip coefficient sets.
DS612F3
CS5376A
13.4 Programmable Coefficients
maximum coefficients programmed into FIR1 FIR2 create custom filter response. total number coefficients filter fundamentally limited available computation cycles digital filter, which itself determined digital filter clock rate. Custom filter sets should normalize maximum coefficient value 24-bit two's complement full scale, 0x7FFFFF, scale other coefficients accordingly. maintain maximum internal dynamic range, CS5376A filter performs double precision calculations with automatic gain correction scale final output. Custom coefficients uploaded using `Write Coefficients' configuration command. "EEPROM Configuration Commands" page "Microcontroller Configuration Commands" page information about writing custom coefficients.
13.5 Filter Synchronization
FIR1 FIR2 filters synchronized external system MSYNC signal, which generated from SYNC input. MSYNC signal sets reference time (time filter operations, filters restarted phase align with this reference time.
DS612F3
CS5376A
FIR1 Single stage, fixed decimate Coefficient linear phase decimate coefficients Coefficient minimum phase decimate coefficients SINC droop compensation filter FIR2 Single stage, fixed decimate Coefficient linear phase decimate coefficients Coefficient minimum phase decimate coefficients Brick wall low-pass filter, flat
Combined SINC digital filter specifications Passband ripple less than 0.01 below Transition band frequency 42.89% Stopband attenuation greater than above
Figure Filter Stages
SINC filters
FIR2 Output Word Rate 4000 2000 1000 SINC Decimation 1280 1600 2560 3200 6400 12800 64000 FIR1 Decimation FIR2 Decimation Total Decimation 1024 1536 2048 2560 4096 5120 10240 12800 20480 25600 51200 102400 512000 Passband Ripple 0.0042 0.0045 0.0040 0.0041 0.0080 0.0064 0.0041 0.0046 0.0040 0.0040 0.0036 0.0040 0.0036 0.0036 0.0036 0.0029 Stopband Attenuation (dB) 130.38 130.38 130.42 130.42 130.45 130.43 130.43 130.42 130.43 130.43 130.43 132.98 130.43 130.43 130.43 134.31
Table Filter Characteristics
DS612F3
CS5376A
Individual filter stage group delay IIR)
Decimation Ratios SINC1 SINC2 Stage Stages Stages 2,3,4 Stages 1,2,3,4 SINC3 Stage Stage Stages Stages 3,4,5 Stages 2,3,4,5 Stages 1,2,3,4,5 FIR1 Coefficient Coefficient FIR2 Coefficient Coefficient 62.5 Figure 23.5 Figure 5,2,2 5,5,2,2 5,5,5,2,2 17,6,7 17,17,6,7 17,17,17,6,7 50.5 260.5 1310.5 2,2,2 2,2,2,2 5,6,7 5,5,6,7 19.0 40.0 Number Coefficients Group Delay (Filter Stage Input Rate) 17.5
Cumulative linear phase group delay IIR)
FIR2 Output Word Rate 4000 2000 1000 SINC Output Group Delay (SINC Filter Input Rate) 41.5 85.5 169.5 337.5 553.5 721.5 849.5 1425.5 1701.5 3401.5 4209.5 6801.5 8421.5 16841.5 33681.5 168081.5 FIR1 Output Group Delay (SINC Filter Input Rate) 417.5 837.5 1673.5 3345.5 5065.5 6737.5 8369.5 13457.5 16741.5 33481.5 41809.5 66961.5 83621.5 167241.5 334481.5 1672081.5 FIR2 Output Group Delay (SINC Filter Input Rate) 4417.5 8837.5 17673.5 35345.5 53065.5 70737.5 88369.5 141457.5 176741.5 353481.5 441809.5 706961.5 883621.5 1767241.5 3534481.5 17672081.5 FIR2 Output Group Delay (FIR2 Output Word Rate) 34.5117 34.5215 34.5186 34.5171 34.5479 34.5398 34.5193 34.5355 34.5198 34.5197 34.5164 34.5196 34.5165 34.5164 34.5164 34.5158
Table SINC Group Delay
DS612F3
CS5376A
Minimum phase group delay
FIR1 Minimum Phase Group Delay (Normalized frequency)
FIR2 Minimum Phase Group Delay (Normalized frequency)
Figure Minimum Phase Group Delay
DS612F3
CS5376A
Filter Type FIR1 (Coefficient pass, SINC compensation Linear phase decimate coefficients Filter Coefficients (normalized 24-bit) 1905 3834 5118 -14518 -39787 -67365 -69909 -19450 97434 258881 375562 332367 39864 -496361 -1084130 -1392827 -1053303 189436 2266428 4768946 7042723 8388607 3337 22258 88284 266742 655747 1371455 2502684 4031988 5783129 7396359 8388607 8325707 6988887 4531706 1507479 -1319126 -3207750 -3736028 -2980701 -1421498 237307 1373654 1711919 1322371
8388607 7042723 4768946 2266428 189436 -1053303 -1392827 -1084130 -496361 39864 332367 375562 258881 97434 -19450 -69909 -67365 -39787 -14518 5118 3834 1905 555919 -165441 -581479 -617500 -388985 -99112 114761 186557 141374 58582 -12664 -42821 -35055 -16792 7929 5926 2892 -1164 -538 -238
FIR1 (Coefficient pass, SINC compensation Minimum phase decimate coefficients
Table FIR1 Coefficients
DS612F3
CS5376A
Filter Type FIR2 (Coefficient pass, passband Linear phase decimate coefficients Filter Coefficients (normalized 24-bit)
-371 -870 -986 1786 2291 -2036 -943 2985 3784 -1458 -5808 -1007 7756 5935 -7135 -11691 3531 17500 4388 -20661 -15960 18930 29808 -9795 -42573 -7745 49994 33021 -47092 -62651 29702 90744 4436 -109189 -54172 109009 114154 -81993 -174452 22850 221211 68863 -238025 -187141 208018 318763 -116005 -443272 -49958 533334 298975 -553873 -642475 454990 1113788 -137179 -1854336 -766230 3875315 8388607 h100 h101 h102 h103 h104 h105 h106 h107 h108 h109 h110 h111 h112 h113 h114 h115 h116 h117 h118 h119 h120 h121 h122 h123 h124 h125 8388607 3875315 -766230 -1854336 -137179 1113788 454990 -642475 -553873 298975 533334 -49958 -443272 -116005 318763 208018 -187141 -238025 68863 221211 22850 -174452 -81993 114154 109009 -54172 -109189 4436 90744 29702 -62651 -47092 33021 49994 -7745 -42573 -9795 29808 18930 -15960 -20661 4388 17500 3531 -11691 -7135 5935 7756 -1007 -5808 -1458 3784 2985 -943 -2036 2291 1786 -986 -870 -371
Table FIR2 Linear Phase Coefficients
DS612F3
CS5376A
Filter Type FIR2 (Coefficient pass, passband Minimum phase decimate coefficients Filter Coefficients (normalized 24-bit)
4019 43275 235427 848528 2240207 4525758 7077833 8388607 6885673 2483461 -2538963 -4800543 -2761696 1426109 3624338 1820814 -1695825 -2885148 -605252 2135021 1974197 -630111 -2168177 -750147 1516192 1550127 -508445 -1686937 -437822 1308705 1069556 -657282 -1301014 -30654 1173754 579643 -803111 -895851 328399 962522 124678 -820948 -466657 545674 652827 -220448 -680495 -80886 578844 306445 -395302 -431004 181900 454403 15856 -395525 -166123 284099 253485 -152407 -277888 28526 250843 h100 h101 h102 h103 h104 h105 h106 h107 h108 h109 h110 h111 h112 h113 h114 h115 h116 h117 h118 h119 h120 h121 h122 h123 h124 h125 67863 -190800 -128546 114197 147750 -46352 -143269 -13290 114721 51933 -75952 -68746 38171 68492 -7856 -57526 -12540 41717 23334 -25516 -26409 11717 24246 -1620 -19248 -4610 13356 7526 -7887 -8016 3559 7023 -598 -5350 -1097 3579 1806 -2058 -1859 1558 -224 -1129 -152 -395 -290 -151
Table FIR2 Minimum Phase Coefficients
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Order IIR1 -a11
Order IIR2 -a21
Order IIR3 implemented running both IIR1 IIR2 stages
-a22
Figure Filter Block Diagram
14.IIR FILTER
infinite impulse response (IIR) filter block consists cascaded stages, IIR1 IIR2. creates high-pass corner block very low-frequency components input signal. On-chip IIR1 IIR2 coefficients selected using configuration command, coefficients programmed custom filter response. characteristic equations order include input value, output value, intermediate values, separated delay element (z-1). (-a11 b10) b11)
14.1 Architecture
architecture filter automatically determined when output filter stage selected FILTCFG register. Selecting order IIR1 filter bypasses order stage, while selecting order IIR2 filter bypasses order stage. Selection order IIR3 filter enables both order stages.
14.3 IIR2 Filter
order filter stage direct form filter with five coefficients: a21, a22, b20, b21, b22. Coefficients order inherently normalized two, should scaled 24-bit two's complement full scale, 0x7FFFFF. Normalization effectively divides order coefficients half relative input, requires modification characteristic equations. characteristic equations order include input value, output value, three intermediate values, each separated delay element (z-1). following
14.2 IIR1 Filter
order filter stage direct form filter with three coefficients: a11, b10, b11. Coefficients order inherently normalized one, should scaled 24-bit two's complement full scale, 0x7FFFFF.
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characteristic equations model operation order filter with unnormalized coefficients. (-a21 (-a22 b20) b21) b22) Internally, CS5376A uses normalized coefficients perform order filter calculation, which changes algorithm slightly. following characteristic equations model operation order filter when using normalized coefficients. (-a21 (-a22 W5)] [(W3 b20) b21) b22)] Which on-chip coefficient selected data word following `Write Coefficients' configuration command. "Filter Coefficient Selection" page information about selecting on-chip coefficient sets.
14.6 Programmable Coefficients
maximum coefficients programmed into IIR1 IIR2 create custom filter response. Custom filter sets should normalize coefficients 24-bit two's complement full scale, 0x7FFFFF. maintain maximum internal dynamic range, CS5376A filter performs double precision calculations with automatic gain correction scale final output. Custom coefficients uploaded using `Write Coefficients' configuration command. "EEPROM Configuration Commands" page "Microcontroller Configuration Commands" page information about writing custom coefficients.
14.4 IIR3 Filter
order filter implemented running both order order filter stages. modeled cascading characteristic equations order order stages.
14.7 Filter Synchronization
filter synchronized external system directly, only indirectly through synchronization SINC filters. Because filters have `infinite' memory, discontinuity input data stream from synchronization event require significant time settle out. exact settling time depends size discontinuity filter coefficient characteristics.
14.5 On-Chip Coefficients
Five sets on-chip coefficients available IIR1 IIR2, each providing high-pass Butterworth response different output word rates. Characteristics on-chip coefficient sets described Figure Table
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IIR1 Single stage, decimation order decimation, coefficients Coefficient Coefficient Coefficient Coefficient Coefficient high-pass, high-pass, high-pass, high-pass, high-pass, corner corner corner corner corner 0.15% 0.30% 0.60% 0.90% 1.20% 2000 SPS) 1000 SPS) SPS) SPS) SPS)
IIR2 Single stage, decimation order decimation, coefficients Coefficient Coefficient Coefficient Coefficient Coefficient high-pass, high-pass, high-pass, high-pass, high-pass, corner corner corner corner corner 0.15% 0.30% 0.60% 0.90% 1.20% 2000 SPS) 1000 SPS) SPS) SPS) SPS)
IIR3 stage, decimation order decimation, coefficients (Combined IIR1 IIR2 filter responses) Coefficient Coefficient Coefficient Coefficient Coefficient 0,0: 1,1: 2,2: 3,3: 4,4: high-pass, high-pass, high-pass, high-pass, high-pass, corner corner corner corner corner 0.20% 0.41% 0.82% 1.22% 1.63% 2000 SPS) 1000 SPS) SPS) SPS) SPS)
Figure Filter Stages
filters
IIR1 Coeff Selection IIR1 Corner Frequency 0.15% 0.30% 0.60% 0.90% 1.20% IIR2 Coeff Selection IIR2 Corner Frequency 0.15% 0.30% 0.60% 0.90% 1.20% IIR3 Coeff Selection IIR3 Corner Frequency 0.2041% 0.4074% 0.8152% 1.2222% 1.6293%
Table Filter Characteristics
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Filter Type IIR1 (Coefficient order, high pass Corner 0.15% coefficients IIR1 (Coefficient order, high pass Corner 0.30% coefficients IIR1 (Coefficient order, high pass Corner 0.60% coefficients IIR1 (Coefficient order, high pass Corner 0.90% coefficients IIR1 (Coefficient order, high pass Corner 1.20% coefficients
Filter Type IIR2 (Coefficient order, high pass Corner 0.15% coefficients
System Function
System Function
Filter Coefficients (normalized 24-bit) -8309916 8349262 -8349262
-8231957 8310282 -8310282
-8078179 8233393 -8233393
-7927166 8157887 -8157887
-7778820 8083714 -8083714
Filter Coefficients (normalized 24-bit) -8332704 4138771 4166445 -8332890 4166445
IIR2 (Coefficient order, high pass Corner 0.30% coefficients
-8276806 4083972 4138770 -8277540 4138770
IIR2 (Coefficient order, high pass Corner 0.60% coefficients
-8165041 3976543 4083972 -8167944 4083972
IIR2 (Coefficient Order, high pass Corner 0.90% coefficients
-8053350 3871939 4029898 -8059796 4029898
IIR2 (Coefficient order, high pass Corner 1.20% coefficients
-7941764 3770088 3976539 -7953078 3976539
Table Filter Coefficients
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Input
SINC Filter
Filters
Filter
Gain Correction
Offset Correction
Output High Speed Serial Data Port Port) Output Rate 4000
Offset Calibration
Figure Gain Offset Correction
15.GAIN OFFSET CORRECTION
CS5376A digital filter apply independent gain offset corrections data each measurement channel. Also, offset calibration algorithm automatically calculate offset correction values each channel. Gain correction values written GAINx registers (0x21-0x24), while offset correction values written OFFSETx registers (0x250x28). Gain offset corrections enabled USEGR USEOR bits FILTCFG register (0x20). When enabled, offset calibration algorithm will automatically calculate offset correction values each channel write them into OFFSETx registers. Offset calibration enabled writing ORCAL bits FILTCFG. nally calculated correction values written into GAINx registers (0x21-0x24). Gain correction values 24-bit two's complement with unity gain defined full scale, 0x7FFFFF. Gain correction always scales fractional value, never gain digital filter data greater than one. Output Value Data (GAIN 0x7FFFFF) Unity Gain: GAIN 0x7FFFFF Gain: GAIN 0x3FFFFF Zero Gain: GAIN 0x000000 Once GAIN registers written, USEGR FILTCFG register enables gain correction.
15.1 Gain Correction
Gain correction CS5376A normalizes sensor gains multi-sensor networks. requires exter-
15.2 Offset Correction
Offset correction CS5376A cancels bias measurement channel subtracting
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value OFFSETx registers (0x25-0x28) from digital filter output data word. Offset correction values 24-bit two's complement with maximum positive value 0x7FFFFF, maximum negative value 0x800000. applying offset correction causes final result exceed 24-bit two's complement maximum, output data will saturate that maximum value. Output Data Input Data Offset Correction Positive Output Value 0x7FFFFF Negative Output Value 0x800000 Once OFFSET registers written, USEOR FILTCFG register enables offset correction. more recent digital filter data. exponential weighting factor bits FILTCFG register, with larger exponent values producing smoother averaging function that requires longer settling time, smaller values producing noisier averaging function that requires shorter settling time. Typical exponential values range from 0x05 0x0F, depending available settling time. characteristic equations offset calibration algorithm include input value, output value, summation value, YSUM, sample index, exponential value, EXP. Y(n) X(n) [YSUM(n-1) EXP] YSUM(n) Y(n) YSUM(n-1) Offset Correction YSUM Once bits written, ORCAL FILTCFG register enable offset calibration. When enabled, updated offset correction values automatically written OFFSETx registers. When offset calibration algorithm fully settled, ORCAL cleared maintain final values OFFSETx registers.
15.3 Offset Calibration
offset calibration algorithm CS5376A automatically calculate offset correction values. When using offset calibration algorithm, background noise data should used basis calculating offset value each measurement channel. offset calibration algorithm exponential averaging function that places increased weight
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System Telemetry
Token Data Ready Clock Data Token
CS5376A
SDTKI SDRDY SDCLK SDDAT SDTKO
Figure Serial Data Port Block Diagram
16.SERIAL DATA PORT
Once digital filtering complete, each 24-bit output sample combined with 8-bit status byte. These 32-bit data words written 8-deep FIFO buffer then transmitted communications channel through high speed serial data port port).
16.2 Port Data Format
Serial data transactions transfer 32-bit words. Each word consists 8-bit status byte followed 24-bit output sample. status byte, shown Figure MFLAG bit, channel bits, time break bit, FIFO overflow bit.
MFLAG MFLAG MFLAG when MFLAG signal received MFLAG1-MFLAG4 pins. When received, that channel MFLAG next output word. "Modulator Interface" page more information about MFLAG. Channel Bits CH[1:0] Channel bits indicate from which conversion channel data word from. channel number, CH[1:0], zero based.
16.1 Descriptions
SDTKI Token input, requests port transaction. SDRDY Data ready output signal, active low. Open drain output requiring pull-up resistor. SDCLK Serial clock input. SDDAT Serial data output. Data valid rising edge SDCLK, transition falling edge. SDTKO Token output, ends port transaction. Passes through SDTKI signal when data available port output FIFO.
CH[1:0] Channel CH[1:0] Channel CH[1:0] Channel CH[1:0] Channel
Time Break
time break marks timing reference based rising edge into TIMEB pin. After programmed delay, status byte output sample channels. TIME61
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Status
Word Data
Word bits
Word
Word
Status
Data
MFLAG
CH[1]
CH[0]
Modulator Modulator Error
Channel Channel Channel Channel
Time Break Time Break
FIFO FIFO Overflow
Figure Port Data Format
digital filter register (0x29) programs sample delay output. "Time Break Controller" page more information about time break.
FIFO Overflow FIFO overflow indicates error condition port data FIFO, digital filter data overwrites FIFO location containing data which been sent.
16.3 Port Transactions
port operate modes depending SDTKI connected: request mode where data output when requested communications channel, continuous mode where data output immediately when ready.
16.3.1 Request Mode initiate port transactions request, SDTKI connected active high polling signal from communications channel. rising edge into SDTKI when data available port FIFO causes CS5376A initiate port transaction driving SDRDY low. data available port FIFO, SDTKI signal passed through SDTKO output.
sticky, meaning persists indefinitely once set. Clearing requires sending `Filter Stop' `Filter Start' configuration commands reinitialize data FIFO.
Conversion Data Word lower 24-bits port output data word conversion sample specified channel. Conversion data 24-bit two's complement format.
Once port transaction initiated, serial clocks into SDCLK cause data output SDDAT, shown Figure When available
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SDTKI
SDTKO
SDRDY
SDCLK
SDDAT
Figure Port Transaction
data read from port data FIFO, SDRDY released SDTKO pulsed high
16.3.2 Continuous Mode have CS5376A automatically initiate port transactions whenever data becomes available, connect SDTKI slower clock source such MCLK/2. first rising edge into SDTKI after data becomes available port FIFO
causes CS5376A initiate port transaction driving SDRDY low. data available port FIFO, SDTKI signal passed through SDTKO output. Once port transaction initiated, serial clocks into SDCLK cause data output SDDAT, shown Figure When available data read from port data FIFO, SDRDY released SDTKO pulsed high
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Digital Filter Data 24-bit TBSGAIN Register 24-bit Digital Modulator 1-bit TBSDATA TBSCLK Clock Generation TBSCFG Register
Figure Test Stream Generator Block Diagram
17.TEST STREAM GENERATOR
CS5376A test stream (TBS) generator creates sine wave impulse stream data drive external test DAC. digital output also internally connected MDATA inputs loopback testing digital filter. defined minimum maximum one's density.
17.3 Configuration
Configuration options generator through TBSCFG register (0x2A). Gain scaling generator output TBSGAIN register (0x2B).
Interpolation Factor INTP[7:0] Selects many times interpolator uses data point when generating output stream. Interpolation zero based represents greater than programmed register value. Operational Mode TMODE Selects between sine wave impulse output mode. Clock Rate RATE[2:0] Selects TBSDATA TBSCLK output rate. Synchronization TSYNC Enables synchronization output phase MSYNC signal. Clock Delay CDLY[2:0] Programs fractional delay TBSCLK with clock period resolution.
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17.1 Descriptions
TBSDATA Test stream 1-bit data output. TBSCLK Test stream clock output. used CS4373A test DAC.
17.2 Architecture
test stream generator consists data interpolator digital modulator. receives periodic 24-bit data from digital filter create 1-bit data output TBSDATA pin. also creates clock signal data rate, output TBSCLK pin. input data from digital filter scaled TBSGAIN register (0x2B). Maximum stable amplitude 0x04FFFF, with 0x04B8F2 approximately full scale CS4373A test DAC. full scale 1-bit output from generator
CS5376A
Test Stream Characteristic Equation:
(Signal Freq) Data) (Interpolation Output Rate
Example: (31.25 (1024) (0x07
Signal Frequency (TBSDATA)
Output Rate (TBSCLK)
Output Rate Selection (RATE)
Interpolation Selection (INTP)
10.00 10.00 25.00 25.00 31.25 31.25 50.00 50.00 125.00 125.00
0x18 0x31 0x09 0x13 0x07 0x0F 0x04 0x09 0x01 0x03
Table Configurations Using On-chip Data
Loopback LOOP Enables digital loopback from output MDATA inputs. Enables test stream generator. Data Delay DDLY[5:0] Programs full period delays TBSDATA, maximum bits. Gain TBSGAIN[23:0] Scales amplitude sine wave output generated impulse. Maximum 0x04FFFF, nominal 0x04B8F2.
chip sine wave data suitable most tests, though custom data required support custom signal frequencies. "EEPROM Configuration Commands" page "Microcontroller Configuration Commands" page information about programming data.
Data on-chip 24-bit 1024 point digital sine wave stored CS5376A. When selected `Write Data' configuration command, generator produce test signal frequencies listed Table Additional discrete test frequencies output rates programmed with on-chip data varying interpolation factor output rate.
17.4 Data Source
Data create test signals loaded into digital filter memory configuration commands.
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Test Stream Impulse Characteristics:
Interpolation Selection (INTP) Output Rate Selection (RATE) Pulse Width from CS4373A Gain Scale Factor (TBSGAIN) Pulse Height from CS4373A
0xFF 0xFF 0xFF 0x7F 0x7F 0x7F
0x04B8F2 0x04B8F2 0x04B8F2 0x04B8F2 0x04B8F2 0x04B8F2
Table Impulse Characteristics
Custom Data required test frequency cannot generated using on-chip test stream data, custom data written into CS5376A. number data points write, maximum 1024, depends required test signal frequency, output rate, available interpolation factors. Custom data sets must continuous ends; i.e. when copied end-to-end data must produce smooth curve.
17.6 Impulse Output
TMODE TBSCFG high, generator operates impulse mode. this mode, value TBSGAIN sets amplitude generated impulse. Impulse amplitude period calculated shown Table create impulse from generator, TBSGAIN register should maximum 0x0078E5, INTP bits TBSCFG should also maximum 0xFF. RATE bits should produce data correct rate test DAC. rising edge TIMEB triggers impulse output. When impulse mode enabled TIMEB input received, generator uses negated TBSGAIN register repetitive input value. When rising edge recognized TIMEB pin, single positive TBSGAIN value written generator create impulse.
17.5 Sine Wave Output
When TMODE TBSCFG register low, generator operates sine wave mode. this mode, sine wave data from digital filter memory used create sine wave test signal that drive test DAC. Sine wave frequency output data rate calculated shown characteristic equation Table sine wave maximum one's density output from generator TBSGAIN register. TBSGAIN programmed maximum 0x04FFFF, with generator unstable higher amplitudes. CS4373A test DAC, gain value 0x04B8F2 produces approximately full scale sine wave output differential).
17.7 Loopback Testing
Included part CS5376A test stream generator feedback path digital filter MDATA inputs. This loopback mode provides fully digital signal path test generator, digital filter, data collection interface. Digital
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loopback testing expects data MDATA inputs. mismatch generator full scale output MDATA full scale input results amplitude mismatch when testing loopback mode. generator outputs maximum one's density, while MDATA inputs expect maximum one's density from modulator, resulting measured full scale error -3.6
17.8 Synchronization
When TSYNC TBSCFG register, MSYNC signal resets sine wave data pointer phase aligns signal output. Once digital filter settled, CS5376A devices receiving SYNC signal will have identical signal phase. "Synchronization" page more information about SYNC MSYNC signals. TSYNC clear, MSYNC effect data pointer change output phase will occur during synchronization.
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TIMEB
TIMEBRK Delay Counter
Flag Port Status Byte
Figure Time Break Block Diagram
18.TIME BREAK CONTROLLER
time break signal used mark timing events that occur during measurement. external signal sets flag status byte output sample mark when external event occurred. rising edge input TIMEB causes timing reference flag port status byte. When set, flag appears only output sample status byte enabled channels. flag output delayed programming sample delay value into TIMEBRK digital filter register.
18.3 Time Break Delay
TIMEBRK register (0x29) sets sample delay between received rising edge TIMEB writing flag into port status byte. programmable sample counter compensate group delay through digital filters. When proper group delay value programmed into TIMEBRK register, flag will status byte measurement sample taken when timing reference signal received.
18.3.1 Step Input Group Delay simple method empirically measure step response group delay CS5376A measurement channel time break signal both timing reference input analog step input.
18.1 Description
TIMEB Time break input pin, rising edge triggered.
18.2 Time Break Operation
externally generated timing reference signal applied TIMEB initiates internal sample counter. After number output samples have passed, programmed TIMEBRK digital filter register (0x29), flag status byte port output word enabled channels. flag automatically cleared subsequent data words, appears only output sample each channel.
When rising edge received TIMEB with delay programmed into TIMEBRK register, flag next port status byte. same rising edge step input analog channel, propagating through digital filter appear rising edge measurement data. comparing timing status flag output rising edge measurement data, measurement channel group delay determined.
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GP_PULL output from Data GP_DATA
Pull Logic
GPIO/CS
GP_DIR
Figure GPIO Bi-directional Structure
19.GENERAL PURPOSE
General Purpose (GPIO) block provides general purpose pins interface with external hardware. sponding GPIO should initialized output mode logical produce chip select falling edge.
19.1 Descriptions
GPIO[4:0]:CS[4:0] Pins Standard GPIO pins also used chip selects.
19.3 GPIO Registers
When used standard GPIO pins, settings programmed GPCFG0 GPCFG1 registers. GP_DIR bits input/output mode, GP_PULL bits enable/disable internal pull-up resistor, GP_DATA bits output data value. After reset, GPIO pins default inputs with pull-up resistors enabled.
GPIO[5:10] Pins
Standard GPIO pins.
GPIO11:EECS
Standard GPIO also used chip select when booting from external EEPROM.
19.4 GPIO Input Mode
When reading value from GP_DATA bits, returned data reports current state pins. externally driven high reads logical externally driven reads logical When GPIO used input, pull-up resistor should disabled save power isn't required.
19.2 GPIO Architecture
Each GPIO configured input output, high low, with weak (~200 internal pull-up resistor enabled disabled. Several GPIO pins also double chip selects serial ports. Figure shows structure bi-directional GPIO with chip select functionality. When CS5376A used master, either when booting from EEPROM using performing master mode transactions using chip select signals from logically AND-ed with GPIO data bit. correDS612F3
19.5 GPIO Output Mode
When GPIO programmed output with data value driven internal pull-up resistor automatically disabled. When programmed output with data value driven high pull-up resistor inconsequential.
CS5376A
GPIO used open-drain output setting data value enabling pull-up, using GP_DIR direction bits control value. This open-drain output configuration uses internal pull-up resistor hold high when GP_DIR input, drives when GP_DIR output.
19.5.1 GPIO Reads Output Mode When reading GPIO pins GP_DATA register value always reports current state pins,
value written output mode does necessarily read back same value. output mode written logical CS5376A attempts drive high. external device forces low, read value reflects state returns logical Similarly, output written logical forced high externally, read value reflects state returns logical both cases CS5376A contention with external device resulting increased power consumption.
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SCKFS[2:0] SCKPO SCKPH Digital Filter SPI2EN[4:1] RCH[1:0]
logic
SCK2
GPIO Block
CS[4:0]
Select logic
Figure Serial Peripheral Interface (SPI Block Diagram
20.SERIAL PERIPHERAL INTERFACE
Serial Peripheral Interface (SPI port master mode port designed interface with serial peripherals. writing SPI2 digital filter registers, multiple serial slave devices controlled through CS5376A. selected bits SPI2CTRL digital filter register. chip select outputs multiplexed with GPIO pins, which cannot perform both functions simultaneously. When used chip select, GPIO output must programmed high permit chip select operate active signal. "General Purpose I/O" page information about programming GPIO pins. interface transfers data from registers slave serial device back through bi-directional 8-bit shift register. Serial transactions automatic once control, command, data values written into digital filter registers.
20.1 Descriptions
CS[4:0] Pins Serial chip selects. Multiplexed with GPIO pins. SCK2 Serial clock output, common channels. Serial data output, common channels. SI[4:1] Pins Serial data inputs.
20.3 Registers
transactions initiated first writing command, address, data values SPI2CMD SPI2DAT digital filter registers, then writing SPI2CTRL register D2SREQ bit. D2SREQ initiates serial transaction using programmed SPI2CTRL configuration.
20.2 Architecture
interface multiple chip selects serial data inputs, common serial clock serial data output. Which chip select serial input particular slave serial transaction
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20.3.1 Control Register hardware configured SPI2CTRL digital filter register (0x10).
ports four modes, with mode mode most commonly used. Supported modes are: Mode (0,0): SCKPO SCKPH Mode (0,1): SCKPO SCKPH Mode (1,0): SCKPO SCKPH Mode (1,1): SCKPO SCKPH
Wired-Or Mode pins operate modes depending bit. default push-pull configuration drives output signals both high low. Wired-Or mode only drives low, relying weak internal pull-up resistor pull output high. Wired-Or mode permits multiple serial controllers access same without contention. Initiating Serial Transactions D2SREQ Writing D2SREQ starts serial transaction. When complete, D2SREQ automatically cleared hardware. Status Error Bits D2SOP, SWEF, Three bits SPI2CTRL register report status error information.
Bits this register select serial input chip select used transaction, total number bytes transaction, initiate serial transaction, report status information about transaction. Other bits SPI2CTRL hardware configuration options such serial clock rate, mode, state internal pull-up resistors.
Chip Select Enable CS[4:0]
chip select during transaction selected CS0, CS1, CS2, CS3, bits. Multiple chip selects enabled send transaction more than serial peripheral.
Serial Input Select SPI2EN[4:1], RCH[1:0] Which serial input will receive data selected using SPI2EN bits bits. SPI2EN bits enable serial input, while bits select transaction.
channel's SPI2EN should always enabled, even when transactions expect receive data from slave device.
Transaction Bytes DNUM[2:0] DNUM bits specify total number bytes transfer during serial transaction, including command address bytes. DNUM zero based represents greater than number programmed. Serial Clock Rate SCKFS[2:0] serial clock rate output from SCK2 selected SCKFS bits. Serial clock rates range from 4.096 MHz. Mode SCKPO, SCKPH serial mode used transaction depends SCKPO SCKPH bits. port sup-
D2SOP when port busy performing transaction. automatically cleared when transaction completed. SWEF request initiate transaction occurs during current transaction. This flag latched must cleared manually. indicate port timed requested transaction. This flag latched must cleared manually.
20.3.2 Command Register SPI2CMD register (0x11) 16-bit digital filter register with high byte designated command byte designated address. high byte holds 8-bit `write' `read' opcode, shown Figure byte holds 8-bit serial address.
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During transaction, bits SPI2CMD output first, with data SPI2DAT written read following.
20.3.3 Data Register SPI2DAT register (0x12) 24-bit digital filter register containing three data bytes. Data SPI2DAT always aligned, with 1-byte data written received using byte, 2-byte data written received using middle bytes, 3-byte data written received using three bytes.
dard write commands they written into SPI2CMD SPI2DAT required.
Read Transactions Read transactions start writing `read' (0x03) opcode 8-bit source address SPI2CMD register. Writing D2SREQ SPI2CTRL register initiates transaction based SPI2CTRL configuration, with data value automatically received into SPI2DAT register.
Data SPI2DAT written read after writing command address bytes from SPI2CMD register.
20.4 Transactions
port operates master perform write read transactions with serial slave peripherals. exact format transactions depends mode, selected using SCKPO SCKPH bits SPI2CTRL register.
Write Transactions Write transactions start writing `write' (0x02) opcode 8-bit destination address into SPI2CMD register output data value SPI2DAT register. Writing D2SREQ SPI2CTRL register initiates transaction based SPI2CTRL configuration.
read transaction outputs bytes from SPI2CMD register receive bytes into SPI2DAT register. Read transactions minimum bytes (DNUM maximum bytes (DNUM port uses DNUM bits SPI2CTRL register determine total number bytes send receive during read transaction. Read transactions required standard commands. serial peripherals non-standard read commands they written SPI2CMD register, long they conform format bytes with bytes
Modes mode port selected SPI2CTRL register using SCKPO SCKPH bits. most commonly used modes mode mode both which define serial clock with data valid rising edges transitioning falling edges.
write transaction outputs bytes from SPI2CMD register followed bytes from SPI2DAT register. Write transactions therefore minimum byte (DNUM maximum bytes (DNUM port uses DNUM bits SPI2CTRL register determine total number bytes send during write transaction. Write transactions required standard commands. serial peripherals non-stan-
mode SCK2 serial clock defined initially state. Output data valid immediately after chip select goes low, first rising edge SCK2 latches valid data. mode SCK2 serial clock defined initially high state. Output data invalid until initial falling edge SCK2, first rising edge SCK2 latches valid data.
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Instruction Write Read 0x02 0x03
Opcode
Address SPI2CMD[7:0] SPI2CMD[7:0]
Definition Write serial peripheral beginning address given SPI2CMD[7:0]. Read serial peripheral beginning address given SPI2CMD[7:0].
Write External Slave
SPI2CMD[15:8] SPI2CMD[7:0] SPI2DAT
0x02
ADDR
Data1
Data2
Data3
Read from External Slave
SPI2CMD[15:8] SPI2CMD[7:0]
0x03
ADDR
Data1
Data2
Data3
SPI2DAT
Figure Master Mode Transactions
modes work similarly modes with serial clock defined have data valid falling edges transitioning rising edges.
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Transaction with SCKPH=0
Cycle SCK2 SCK2
SCKPO
SCKPO
Slave devices only drive after being selected responding read command.
Transaction with SCKPH=1
Cycle SCK2 SCK2
SCKPO
SCKPO
Slave devices only drive after being selected responding read command.
Figure Transaction Details
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TRST Controller
Boundary Scan Cells
Figure JTAG Block Diagram
21.BOUNDARY SCAN JTAG
CS5376A includes IEEE 1149.1 boundary scan JTAG port test interconnections. Refer IEEE 1149.1 specification more information about boundary scan testing.
21.2 JTAG Architecture
JTAG test circuitry consists test access port (TAP) controller boundary scan cells connected each pin. boundary scan cells linked together create scan chain around CS5376A.
21.2.1 JTAG Reset required IEEE 1149.1 specification, JTAG TRST signal independent CS5376A RESET signal. systems using JTAG port, TRST should connected ground. systems using JTAG port, TRST RESET should independently driven provide reset capability during boundry scan. 21.2.2 Controller test access port (TAP) controller manages commands data through boundary scan chain. supports four JTAG instructions contains IDCODE listed Table
21.1 Descriptions
TRST Reset input test access port (TAP) controller boundary scan cells, active low. Connect disable JTAG port. Serial input select JTAG test mode. Clock input controller. Serial input scan chain controller. Serial output from scan chain controller.
controller also implements JTAG state assignments from IEEE 1149.1 specification, which sequenced using TCK.
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21.2.3 Boundary Scan Cells CS5376A JTAG test port provides access device pins internal boundary scan cells. When JTAG port disabled, boundary scan cells transparent affect CS5376A operation. When JTAG port enabled, boundary scan cells write read each independent CS5376A operation.
JTAG Instructions BYPASS EXTEST IDCODE SAMPLE PRELOAD
Encoding
JTAG IDCODE Components Revision Device Manufacturer CS5376A IDCODE
Encoding 0x10000000 0x05376000 0x000000C9 0x153760C9
Boundary scan cells serially linked create scan chain around CS5376A controlled controller. Table lists scan cell mapping CS5376A.
Table JTAG Instructions IDCODE
DS612F3
CS5376A
TBSCLK TBSDATA MCLK/2 MCLK MSYNC MDATA4 MFLAG4 MDATA3 MFLAG3 MDATA2 MFLAG2 MDATA1 MFLAG1 SCK2 GPIO0
Function data data data data data data data data data data data data data data data data data data data data data data data output enable pullup
GPIO3
Function data data output enable pullup
GPIO11
Function data data output enable pullup data output enable
GPIO4
data data output enable pullup
SCK1
data data output enable pullup data data data output enable pullup
GPIO5
data data output enable pullup
GPIO6
data data output enable pullup
MISO
GPIO7
data data output enable pullup
MOSI
data data output enable pullup
GPIO8
data data output enable pullup
SINT RESET BOOT TIMEB SYNC SDDAT SDRDY SDCLK SDTKO SDTKI
data data data data data data data output enable data data data data
GPIO9
data data output enable pullup
GPIO1
data data output enable pullup
GPIO10
data data output enable pullup
GPIO2
data data output enable pullup
Table JTAG Scan Cell Mapping
DS612F3
CS5376A
22.DEVICE REVISION HISTORY
CS5376A compatible upgrade CS5376. part family three revisions:
CS5376 CS5376 CS5376A Modified Coefficient Selection Method Changed coefficient selection routines (SPI EEPROM) require data word. Previously data word required, only command byte. data word parsed select FIR1, FIR2, IIR1, IIR2 coefficient sets. Modified Data Selection Method Changed test stream selection routine (SPI EEPROM) require data word. Previously data word required, only command byte. data word scales test stream data user selected amplitude. Modified port strobe SINT port pulses SINT whenever data received. used microcontroller trigger additional data writes. Eliminates need poll e2dreq bit. Fixed continuous synchronization operation
part number change CS5376A reflects additional functionality built into device.
22.1 Changes from CS5376 CS5376
Sinc Filter, SINC3 Added sinc filter, SINC3, between previous sinc filters FIR1. Will permit higher decimation rates seismology applications. used 0.25 output rates maintain backward compatibility. Added FIR1 Coefficients Included improved FIR1 filter compensate sinc filter droop. Previous filter stop band frequency components -100 removed FIR2 brick wall filter. Required stop band attenuation minimum. Previous FIR1 filter coefficients still included maintain backwards compatibility. Added Coefficients Included IIR1 IIR2 filter coefficients configurations sets IIR1, sets IIR2). Previous coefficient removed. Modified Output Word Rate Selection Changed settings FILTCFG register used select output word rate. Re-numbered include output rates. Other settings same backward compatibility.
synchronization operation modified permit continuous re-sync. port FIFO longer reset SYNC interrupt.
Corrected EEPROM loader EEPROM loader fixed. preamble write required constants into memory longer required.
22.2 Changes from CS5376 CS5376A
Fixed synchronization repeatability Identical synchronization signals previously caused different impulse responses from multiple devices. Synchronization repeatable.
DS612F3
CS5376A
Modified SINC2 filter correct gain timing errors Removed gain scale factor from 'Write ROM' command
Corrected SINC2 decimate gain error which affected 4000 operation. Also modified SINC2 decimate output timing match output other SINC2 rates. Previous SINC2 decimate output sample later than expected.
Corrected gain error output rate SINC architecture modified correct gain error SINC2 decimate moving decimate stage into SINC3. Modified SINC3 filter bandwidth rates.
data previously scaled during configuration data word following 'Write ROM' command. Added TBSGAIN register (0x2B, replacing WD_CFG) that scales amplitude modified during normal operation.
Removed watchdog timer watchdog timer removed. Replaced WD_CFG register (0x2B) with TBSGAIN register. GPIO11 tri-state when EEPROM boot completed
Newly supported output word rates 200, 125, 100, SPS. Older bandwidth rates 120, were removed. changes 4000, 2000, 1000, 500, 333, rates backwards compatibility CS5376 revision A/B.
Added minimum phase coefficients Minimum phase FIR1 coefficient FIR2 coefficient newly available selections EEPROM 'Write Coefficients' command. Corrected IIR2/IIR3 channels When selecting IIR2 IIR3 output, data from channels were corrupted. IIR2 IIR3 operate correctly these channels. Corrected IIR2 coefficient offset IIR2 coefficient sets perfectly cancel coefficient b20, b21, mismatch. IIR2 coefficients correct this offset error.
After stand-alone boot from EEPROM, GPIO11 (acting EEPROM chip select) previously driven high. This tri-states with internal pull-up hold high.
Modified Test Stream (TBS) disable loopback when disabled.
loopback mode enabled, external MDATA inputs were disconnected from SINC filter even disabled. when disabled, loopback mode automatically disabled also.
Added Test Stream (TBS) impulse mode.
operate sine wave impulse mode, depending TBSCFG register. When impulse mode enabled (TBSCFG rising edge TIMEB causes output impulse bitstream. When sine wave mode enabled (TBSCFG operation identical CS5376 revision A/B.
DS612F3
CS5376A
Added Test Stream (TBS) synchronization sine wave mode.
sine wave phase will reset TBSCFG register (TBSCFG rising edge received SYNC pin. When TBSCFG (TBSCFG phase unaffected SYNC input similar CS5376 revision A/B.
Modified Time Break delay function. timing delay between receiving rising
edge TIMEB asserting TIMEB flag output word status bits corrected. CS5376 revision value TIMEBREAK register (0x29) disabled TIMEB status write, value status current output word. Now, value sets TIMEB status current output word, value delays until following word.
DS612F3
CS5376A
23.REGISTER SUMMARY 23.1 Registers
CS5376A registers interface serial port digital filter.
Name Addr. Type Bits Description
SPI1CTRLH SPI1CTRLM SPI1CTRLL SPI1CMDH SPI1CMDM SPI1CMDL SPI1DAT1H SPI1DAT1M SPI1DAT1L SPI1DAT2H SPI1DAT2M SPI1DAT2L
Control Register, High Byte Control Register, Middle Byte Control Register, Byte Command, High Byte Command, Middle Byte Command, Byte Data High Byte Data Middle Byte Data Byte Data High Byte Data Middle Byte Data Byte
DS612F3
CS5376A
23.1.1 SPI1CTRL 0x00, 0x01, 0x02
Figure Control Register SPI1CTRL
(MSB)
-R/W
-R/W1
-R/W
-R/W
-R/W
-R/W
-R/W
-R/W
Address: 0x00 0x01 0x02
SMODF
-R/W
EMOP
SWEF
-R/W
-R/W
E2DREQ
defined; read Readable Writable Readable Writable
(LSB)
-R/W
-R/W
-R/W
-R/W
-R/W
-R/W
-R/W
-R/W
Bits bottom rows reset condition
definitions:
23:16 -reserved SMODF mode fault flag reserved External master operation progress flag write collision error flag reserved -reserved
14:13 EMOP
SWEF
10:9
E2DREQ External master digital filter request flag
DS612F3
CS5376A
23.1.2 SPI1CMD 0x03, 0x04, 0x05
Figure Command Register SPI1CMD
(MSB)
S1CMD23
S1CMD22
S1CMD21
S1CMD20
S1CMD19
S1CMD18
S1CMD17
S1CMD16
Address: 0x03 0x04 0x05
S1CMD15
S1CMD14
S1CMD13
S1CMD12
S1CMD11
S1CMD10
S1CMD9
S1CMD8
defined; read Readable Writable Readable Writable
(LSB)
S1CMD7
S1CMD6
S1CMD5
S1CMD4
S1CMD3
S1CMD2
S1CMD1
S1CMD0
Bits bottom rows reset condition
definitions:
23:16 S1CMD[23:16] Command High Byte 15:8 S1CMD[15:8] Command Middle Byte 15:8 S1CMD[7:0] Command Byte
DS612F3
CS5376A
23.1.3 SPI1DAT1 0x06, 0x07, 0x08
Figure Data Register SPI1DAT1
(MSB)
S1DAT23
S1DAT22
S1DAT21
S1DAT20
S1DAT19
S1DAT18
S1DAT17
S1DAT16
Address: 0x06 0x07 0x08
S1DAT15
S1DAT14
S1DAT13
S1DAT12
S1DAT11
S1DAT10
S1DAT9
S1DAT8
defined; read Readable Writable Readable Writable
(LSB)
S1DAT7
S1DAT6
S1DAT5
S1DAT4
S1DAT3
S1DAT2
S1DAT1
S1DAT0
Bits bottom rows reset condition
definitions:
23:16 S1DAT[23:16] Data High Byte 15:8 S1DAT[15:8] Data Middle Byte 15:8 S1DAT[7:0] Data Byte
DS612F3
CS5376A
23.1.4 SPI1DAT2 0x09, 0x0A, 0x0B
Figure Data Register SPI1DAT2
(MSB)
S1DAT23
S1DAT22
S1DAT21
S1DAT20
S1DAT19
S1DAT18
S1DAT17
S1DAT16
Address: 0x09 0x0A 0x0B
S1DAT15
S1DAT14
S1DAT13
S1DAT12
S1DAT11
S1DAT10
S1DAT9
S1DAT8
defined; read Readable Writable Readable Writable
(LSB)
S1DAT7
S1DAT6
S1DAT5
S1DAT4
S1DAT3
S1DAT2
S1DAT1
S1DAT0
Bits bottom rows reset condition
definitions:
23:16 S1DAT[23:16] Data High Byte 15:8 S1DAT[15:8] Data Middle Byte 15:8 S1DAT[7:0] Data Byte
DS612F3
CS5376A
23.2 Digital Filter Registers
CS5376A digital filter registers control hardware peripherals filtering functions.
Name Addr. Type Bits Description
CONFIG RESERVED GPCFG0 GPCFG1 SPI2CTRL SPI2CMD SPI2DAT RESERVED FILTCFG GAIN1 GAIN2 GAIN3 GAIN4 OFFSET1 OFFSET2 OFFSET3 OFFSET4 TIMEBRK TBSCFG TBSGAIN SYSTEM1 SYSTEM2 VERSION SELFTEST
01-0D 13-1F
Hardware Configuration Reserved GPIO[7:0] Direction, Pull-Up Enable, Data GPIO[11:8] Direction, Pull-Up Enable, Data SPI2 Control SPI2 Command SPI2 Data Reserved Digital Filter Configuration Gain Correction Channel Gain Correction Channel Gain Correction Channel Gain Correction Channel Offset Correction Channel Offset Correction Channel Offset Correction Channel Offset Correction Channel Time Break Delay Test Stream Configuration Test Stream Gain User Defined System Register User Defined System Register Hardware Version Self-Test Result Code
DS612F3
CS5376A
23.2.1 CONFIG 0x00
Figure Hardware Configuration Register CONFIG
(MSB)23
-R/W
-R/W
-R/W
-R/W
-R/W
DFS2
DFS1
DFS0
Address: 0x00
-R/W
-R/W
-R/W
-R/W
-R/W
MCKFS2
MCKFS1
MCKFS0
defined; read Readable Writable Readable Writable
(LSB)0
Bits bottom rows reset condition
-R/W
-R/W
MCKEN2
MCKEN
MDIFS
-R/W
BOOT
MSEN
definitions:
23:19 -18:16 [2:0] reserved Digital filter frequency select 111: 16.384 110: 8.192 101: 4.096 100: 2.048 011: 1.024 010: 001: 000: 15:11 -10:8 MCKFS [2:0] reserved -MCKEN2 reserved MCLK/2 output enable Enabled Disabled MCLK output enable Enabled Disabled MDATA input frequency select reserved Boot source indicator Booted from EEPROM Booted from Micro MSYNC enable MSYNC generated MSYNC remains
MCLK frequency select 111: reserved 110: reserved 101: 4.096 100: 2.048 011: 1.024 010: 001: reserved 000: reserved
MCKEN
MDIFS
-BOOT
MSEN
DS612F3
CS5376A
23.2.2 GPCFG0 0x0E
Figure GPIO Configuration Register GPCFG0
(MSB)
GP_DIR7
GP_DIR6
GP_DIR5
GP_DIR4
GP_DIR3
GP_DIR2
GP_DIR1
GP_DIR0
Address: 0x0E
GP_PULL7
GP_PULL6
GP_PULL5
GP_PULL4
GP_PULL3
GP_PULL2
GP_PULL1
GP_PULL0
defined; read Readable Writable Readable Writable
GP_DATA7
GP_DATA6
GP_DATA5
GP_DATA4
GP_DATA3
GP_DATA2
GP_DATA1
(LSB)
GP_DATA0
Bits bottom rows reset condition
definitions:
23:16 GP_DIR [7:0] GPIO direction Output Input 15:8 GP_PULL GPIO pullup resistor [7:0] Enabled Disabled GP_DATA GPIO data value [7:0]
Note: GPIO[4:0] also used chip selects CS[4:0].
DS612F3
CS5376A
23.2.3 GPCFG1 0x0F
Figure GPIO Configuration Register GPCFG1
(MSB)
GP_DIR11
GP_DIR10
GP_DIR9
GP_DIR8
-R/W
-R/W
-R/W
-R/W
Address: 0x0F
GP_PULL11
GP_PULL10
GP_PULL9
GP_PULL8
-R/W
-R/W
-R/W
-R/W
defined; read Readable Writable Readable Writable
GP_DATA11
GP_DATA10
GP_DATA9
(LSB)
GP_DATA8
Bits bottom rows reset cond
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