Platform Flash In-System Programmable Configuration PROMS DS123 (
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Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.9) 2006
Features
In-System Programmable PROMs Configuration Xilinx FPGAs Low-Power Advanced CMOS FLASH Process Endurance 20,000 Program/Erase Cycles Operation over Full Industrial Temperature Range (-40°C +85°C) IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support Programming, Prototyping, Testing JTAG Command Initiation Standard FPGA Configuration Cascadable Storing Longer Multiple Bitstreams Dedicated Boundary-Scan (JTAG) Power Supply (VCCJ) Pins Compatible with Voltage Levels Ranging From 1.5V 3.3V Design Support Using Xilinx Alliance Foundation Series Software Packages XCF01S/XCF02S/XCF04S
3.3V supply voltage Serial FPGA configuration interface MHz) Available small-footprint VO20 VOG20 packages. 1.8V supply voltage Serial parallel FPGA configuration interface MHz) Available small-footprint VO48, VOG48, FS48, FSG48 packages Design revision technology enables storing accessing multiple design revisions configuration Built-in data decompressor compatible with Xilinx advanced compression technology
XCF08P/XCF16P/XCF32P
Table Platform Flash PROM Features
Device Density VCCINT VCCO Range VCCJ Range Packages Program In-system JTAG Serial Config. Parallel Config. Design Revisioning Compression
XCF01S XCF02S XCF04S XCF08P XCF16P XCF32P
Mbit Mbit Mbit Mbit Mbit Mbit
3.3V 3.3V 3.3V 1.8V 1.8V 1.8V
1.8V 3.3V 2.5V 3.3V 1.8V 3.3V 2.5V 3.3V 1.8V 3.3V 2.5V 3.3V 1.5V 3.3V 2.5V 3.3V 1.5V 3.3V 2.5V 3.3V 1.5V 3.3V 2.5V 3.3V
VO20/VOG20 VO20/VOG20 VO20/VOG20 VO48/VOG48 FS48/FSG48 VO48/VOG48 FS48/FSG48 VO48/VOG48 FS48/FSG48
Description
Xilinx introduces Platform Flash series in-system programmable configuration PROMs. Available Megabit (Mbit) densities, these PROMs provide easy-to-use, cost-effective, reprogrammable method storing large Xilinx FPGA configuration bitstreams. Platform Flash PROM series includes both 3.3V XCFxxS PROM 1.8V XCFxxP PROM. XCFxxS version includes 4-Mbit, 2-Mbit, 1-Mbit PROMs that support Master Serial Slave Serial FPGA configuration modes (Figure page XCFxxP version includes 32-Mbit, 16-Mbit, 8-Mbit PROMs that support Master Serial, Slave Serial, Master SelectMAP, Slave SelectMAP FPGA configuration modes (Figure page summary Platform Flash PROM family members supported features shown Table
2003-2006 Xilinx, Inc. rights reserved. Xilinx trademarks, registered trademarks, patents, disclaimers listed PowerPC trademark IBM, Inc. other trademarks property their respective owners. specifications subject change without notice.
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Platform Flash In-System Programmable Configuration PROMS
OE/RESET
Control JTAG Interface
Data
Memory
Address Data
Serial Interface
DATA (D0) Serial Mode
ds123_01_30603
Figure XCFxxS Platform Flash PROM Block Diagram
EN_EXT_SEL
OE/RESET
BUSY
Decompressor
CLKOUT
Control JTAG Interface
Data Address
Memory
Data
Serial Parallel Interface
DATA (D0) (Serial/Parallel Mode) D[1:7] (Parallel Mode)
REV_SEL [1:0]
ds123_19_122105
Figure XCFxxP Platform Flash PROM Block Diagram When FPGA Master Serial mode, generates configuration clock that drives PROM. With High, short access time after enabled, data available PROM DATA (D0) that connected FPGA pin. data available short access time after each rising clock edge. FPGA generates appropriate number clock pulses complete configuration. When FPGA Slave Serial mode, PROM FPGA both clocked external clock source, optionally, XCFxxP PROM only, PROM used drive FPGA's configuration clock. XCFxxP version Platform Flash PROM also supports Master SelectMAP Slave SelectMAP Slave Parallel) FPGA configuration modes. When FPGA Master SelectMAP mode, FPGA generates configuration clock that drives PROM. When FPGA Slave SelectMAP Mode, either external oscillator generates configuration clock that drives PROM FPGA, optionally, XCFxxP PROM used drive FPGA's configuration clock. With BUSY High, after enabled, data available
DS123 (v2.9) 2006
PROMs DATA (D0-D7) pins. data available short access time after each rising clock edge. data clocked into FPGA following rising edge CCLK. free-running oscillator used Slave Parallel /Slave SelecMAP mode. XCFxxP version Platform Flash PROM provides additional advanced features. built-in data decompressor supports utilizing compressed PROM files, design revisioning allows multiple design revisions stored single PROM stored across several PROMs. design revisioning, external pins internal control bits used select active design revision. Multiple Platform Flash PROM devices cascaded support larger configuration files required when targeting larger FPGA devices targeting multiple FPGAs daisy chained together. When utilizing advanced features XCFxxP Platform Flash PROM, such design revisioning, programming files which span cascaded PROM devices only created cascaded chains containing only XCFxxP PROMs. advanced XCFxxP features enabled, then cascaded chain include both XCFxxP XCFxxS PROMs.
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Platform Flash In-System Programmable Configuration PROMS
Platform Flash PROMs compatible with existing FPGA device families. reference list Xilinx FPGAs respective compatible Platform Flash PROMs given Table list Platform Flash PROMs their capacities given Table page Table Xilinx FPGAs Compatible Platform Flash PROMs
FPGA Virtex-5
XC5VLX30 XC5VLX50 XC5VLX85 XC5VLX110 XC5VLX220 XC5VLX330 Virtex-4 XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 Virtex-4 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 Virtex-4 XC4VSX25 XC4VSX35 XC4VSX55 Virtex-II XC2VPX20 XC2VPX70 Virtex-II XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VP100 1,305,376 3,006,496 4,485,408 8,214,560 11,589,920 15,868,192 19,021,344 26,098,976 34,292,768 XCF02S XCF04S XCF08P XCF08P XCF16P XCF16P XCF32P XCF32P XCF32P 8,214,560 26,098,976 XCF08P XCF32P 9,147,648 13,700,288 22,749,184 XCF16P XCF16P XCF32P 4,765,568 7,242,624 14,936,192 21,002,880 33,065,408 47,856,896 XCF08P XCF08P XCF16P XCF32P XCF32P XCF32P+XCF16P 4,765,568 7,819,904 12,259,712 17,717,632 23,291,008 30,711,680 40,347,008 51,367,808 XCF08P XCF08P XCF16P XCF32P XCF32P XCF32P XCF32P+XCF08P XCF32P+XCF32P 8,374,016 12,556,672 21,845,632 29,124,608 53,139,456 XCF08P XCF16P XCF32P XCF32P XCF32P+XCF32P
Table Xilinx FPGAs Compatible Platform Flash PROMs (Continued)
FPGA
Virtex-II XC2V40 XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000 Virtex-E XCV50E XCV100E XCV200E XCV300E XCV400E XCV405E XCV600E XCV812E XCV1000E XCV1600E XCV2000E XCV2600E XCV3200E Virtex XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 Spartan-3E XC3S100E XC3S250E XC3S500E 581,344 1,352,192 2,267,136 XCF01S XCF02S XCF04S 559,200 781,216 1,040,096 1,335,840 1,751,808 2,546,048 3,607,968 4,715,616 6,127,744 XCF01S XCF01S XCF01S XCF02S XCF02S XCF04S XCF04S XCF08P XCF08P 630,048 863,840 1,442,016 1,875,648 2,693,440 3,430,400 3,961,632 6,519,648 6,587,520 8,308,992 10,159,648 12,922,336 16,283,712 XCF01S XCF01S XCF02S XCF02S XCF04S XCF04S XCF04S XCF08P XCF08P XCF08P XCF16P XCF16P XCF16P 360,096 635,296 1,697,184 2,761,888 4,082,592 5,659,296 7,492,000 10,494,368 15,659,936 21,849,504 29,063,072 XCF01S XCF01S XCF02S XCF04S XCF04S XCF08P XCF08P XCF16P XCF16P XCF32P XCF32P
Configuration Bitstream
Platform Flash PROM
Configuration Bitstream
Platform Flash PROM
79,704,832 XCF32P+XCF32P+XCF16P
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Platform Flash In-System Programmable Configuration PROMS
Table Xilinx FPGAs Compatible Platform Flash PROMs (Continued)
FPGA
XC3S1200E XC3S1600E Spartan-3L XC3S1000L XC3S1500L XC3S5000L Spartan-3 XC3S50 XC3S200 XC3S400 XC3S1000 XC3S1500 XC3S2000 XC3S4000 XC3S5000 Spartan-IIE XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E Spartan-II XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200 Notes:
design revisioning other advanced feature support required, XCFxxP used alternative XCF01S, XCF02S, XCF04S. Assumes compression used. largest possible Virtex-II bitstream sizes specified. Refer Virtex-II User Guide information bitgen options which affect bitstream size.
Programming
In-System Programming
In-System Programmable PROMs programmed individually, more daisy-chained together programmed in-system standard 4-pin JTAG protocol shown Figure In-system programming offers quick efficient design iterations eliminates unnecessary package handling socketing devices. programming data sequence delivered device using either Xilinx iMPACT software Xilinx download cable, third-party JTAG development system, JTAG-compatible board tester, simple microprocessor interface that emulates JTAG instruction sequence. iMPACT software also outputs serial vector format (SVF) files with tools that accept format, including automatic test equipment. During in-system programming, output driven High. other outputs held high-impedance state held clamp levels during in-system programming. In-system programming fully supported across recommended operating voltage temperature ranges.
Configuration Bitstream
3,832,320 5,957,760 3,223,488 5,214,784 13,271,936 439,264 1,047,616 1,699,136 3,223,488 5,214,784 7,673,024 11,316,864 13,271,936 630,048 863,840 1,134,496 1,442,016 1,875,648 2,693,440 3,961,632 197,696 336,768 559,200 781,216 1,040,096 1,335,840
Platform Flash PROM
XCF04S XCF08P XCF04S XCF08P XCF16P XCF01S XCF01S XCF02S XCF04S XCF08P XCF08P XCF16P XCF16P XCF01S XCF01S XCF02S XCF02S XCF02S XCF04S XCF04S
XCF01S
XCF01S XCF01S XCF01S XCF01S XCF02S
DS026_02_082703
Figure JTAG In-System Programming Operation Solder Device Program Using Download Cable
OE/RESET
1/2/4 Mbit XCFxxS Platform Flash PROMs in-system programming algorithm results issuance internal device reset that causes OE/RESET pulse Low.
External Programming
Xilinx reprogrammable PROMs also programmed Xilinx MultiPRO Desktop Tool third-party device programmer. This provides added flexibility using pre-programmed devices with in-system programmable option future enhancements design changes.
Table Platform Flash PROM Capacity
Platform Flash PROM XCF01S XCF02S XCF04S Configuration Bits Platform Flash PROM Configuration Bits 8,388,608 16,777,216 33,554,432
1,048,576 XCF08P 2,097,152 XCF16P 4,194,304 XCF32P
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Platform Flash In-System Programmable Configuration PROMS operations. XCFxxS PROM, read protect security entire device, resetting read protect security requires erasing entire device. XCFxxP PROM read protect security individual design revisions, resetting read protect requires erasing particular design revision.
Reliability Endurance
Xilinx in-system programmable products provide guaranteed endurance level 20,000 in-system program/erase cycles minimum data retention years. Each device meets functional, performance, data retention specifications within this endurance limit.
Write Protection
Design Security
Xilinx in-system programmable Platform Flash PROM devices incorporate advanced data security features fully protect FPGA programming data against unauthorized reading JTAG. XCFxxP PROMs also programmed prevent inadvertent writing JTAG. Table Table show security settings available XCFxxS PROM XCFxxP PROM, respectively.
XCFxxP PROM device also allows user write protect lock) particular design revision prevent inadvertent erase program operations. Once set, write protect security individual design revision must reset (using UNLOCK command followed ISC_ERASE command) before erase program operation performed. Table XCFxxS Device Data Security Options
Read Protection
read protect security user prevent internal programming pattern from being read copied JTAG. Read protection does prevent write Table XCFxxP Design Revision Data Security Options
Read Protect
Reset (default) Reset (default)
Read Protect
Reset (default)
Read/Verify Inhibited
Program Inhibited
Erase Inhibited
Write Protect
Reset (default) Reset (default)
Read/Verify Inhibited
Program Inhibited
Erase Inhibited
IEEE 1149.1 Boundary-Scan (JTAG)
Platform Flash PROM family compatible with IEEE 1149.1 boundary-scan standard IEEE 1532 in-system configuration standard. Test Access Port (TAP) registers provided support required boundary scan instructions, well many optional instructions specified IEEE Std. 1149.1. addition, JTAG interface used implement in-system programming (ISP) facilitate configuration, erasure, verification operations Platform Flash PROM device. Table page lists required optional boundary-scan instructions supported Platform Flash PROMs. Refer IEEE Std. 1149.1 specification complete description boundary-scan architecture required optional instructions. Caution!
XCFxxP JTAG pause states fully compliant with JTAG 1149.1 specification. temporary pause JTAG shift operation required, then stop JTAG clock maintain JTAG within JTAG Shift-IR Shift-DR state. transition XCFxxP JTAG through JTAG Pause-IR Pause-DR state temporarily pause JTAG shift operation.
Instruction Register
Instruction Register (IR) Platform Flash PROM connected between during instruction scan sequence. preparation instruction scan sequence, instruction register parallel loaded with fixed instruction capture pattern. This pattern shifted onto (LSB first), while instruction shifted into instruction register from TDI.
XCFxxS Instruction Register bits wide)
Instruction Register (IR) XCFxxS PROM eight bits wide connected between during instruction scan sequence. detailed composition instruction capture pattern illustrated Table page instruction capture pattern shifted XCFxxS device includes IR[7:0]. IR[7:5] reserved bits logic Status field, IR[4], contains logic device currently In-System Configuration (ISC) mode; otherwise, contains logic Security field, IR[3], contains logic device been programmed with security option turned otherwise, contains
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Platform Flash In-System Programmable Configuration PROMS Erase/Program (ER/PROG) Error field, IR[6:5], contains when erase program operation success; otherwise when erase program operation fails. Erase/Program (ER/PROG) Status field, IR[4], contains logic when device busy performing erase programming operation; otherwise, contains logic Status field, IR[3], contains logic device currently In-System Configuration (ISC) mode; otherwise, contains logic DONE field, IR[2], contains logic sampled design revision been successfully programmed; otherwise, logic indicates incomplete programming. remaining bits IR[1:0] defined IEEE Std. 1149.1.
logic IR[2] unused, '0'. remaining bits IR[1:0] '01' defined IEEE Std. 1149.1.
XCFxxP Instruction Register bits wide)
Instruction Register (IR) XCFxxP PROM sixteen bits wide connected between during instruction scan sequence. detailed composition instruction capture pattern illustrated Table page instruction capture pattern shifted XCFxxP device includes IR[15:0]. IR[15:9] reserved bits logic Error field, IR[8:7], contains when operation success; otherwise when In-System Configuration (ISC) operation fails.
Table Platform Flash PROM Boundary Scan Instructions
Boundary-Scan Command Required Instructions
BYPASS SAMPLE/PRELOAD EXTEST Optional Instructions CLAMP HIGHZ IDCODE USERCODE 00FA 00FC 00FE 00FD Enables boundary-scan CLAMP operation Places outputs high-impedance state simultaneously Enables shifting 32-bit IDCODE Enables shifting 32-bit USERCODE FFFF 0001 0000 Enables BYPASS Enables boundary-scan SAMPLE/PRELOAD operation Enables boundary-scan EXTEST operation
XCFxxS IR[7:0] (hex)
XCFxxP IR[15:0] (hex)
Instruction Description
Platform Flash PROM Specific Instructions
Initiates FPGA configuration pulsing once. (For XCFxxP this command also resets selected design revision based either external REV_SEL[1:0] pins internal design revision selection bits.)
CONFIG
00EE
Notes:
more information "Initiating FPGA Configuration," page
Table XCFxxS Instruction Capture Values Loaded into part Instruction Scan Sequence
IR[7:5]
Reserved
IR[4]
Status
IR[3]
Security
IR[2]
IR[1:0]
Table XCFxxP Instruction Capture Values Loaded into part Instruction Scan Sequence
IR[15:9]
Reserved
IR[8:7]
Error
IR[6:5]
ER/PROG Error
IR[4]
ER/PROG Status
IR[3]
Status
IR[2]
DONE
IR[1:0]
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Platform Flash In-System Programmable Configuration PROMS
Boundary Scan Register
boundary-scan register used control observe state device pins during EXTEST, SAMPLE/PRELOAD, CLAMP instructions. Each output Platform Flash PROM register stages which contribute boundary-scan register, while each input only register stage. bidirectional pins have total three register stages which contribute boundary-scan register. each output pin, register stage nearest controls observes output state, second stage closest controls observes High-Z enable state output pin. each input pin, single register stage controls observes input state pin. bidirectional combines three bits, input stage first, followed output stage finally output enable stage bit. output enable stage closest TDO. XCFxxS/XCFxxP Names Descriptions Tables "Pinouts Descriptions," page section boundary-scan order connected device pins, appropriate BSDL file complete boundary-scan order description under "attribute BOUNDARY_REGISTER" section BSDL file. assigned boundary-scan cell boundary-scan register, register closest TDO. IDCODE register following binary format:
where version number PROM family code specific Platform Flash PROM product Xilinx manufacturer's IDCODE register always read logic defined IEEE Std. 1149.1.
USERCODE Register
USERCODE instruction gives access 32-bit user programmable scratch typically used supply information about device's programmed contents. using USERCODE instruction, user-programmable identification code shifted examination. This code loaded into USERCODE register during programming Platform Flash PROM. device blank loaded during programming, USERCODE register contains FFFFFFFFh.
Customer Code Register
XCFxxP Platform Flash PROM, addition USERCODE, unique 32-byte Customer Code assigned each design revision enabled PROM. Customer Code during programming, typically used supply information about design revision contents. private JTAG instruction required read Customer Code. PROM blank, Customer Code selected design revision loaded during programming, particular design revision erased, Customer Code will contain ones.
Identification Registers
IDCODE Register
IDCODE fixed, vendor-assigned value that used electrically identify manufacturer type device being addressed. IDCODE register bits wide. IDCODE register shifted examination using IDCODE instruction. IDCODE available other system component JTAG. Table lists IDCODE register values Platform Flash PROMs. Table IDCODES Assigned Platform Flash PROMs
Device
XCF01S XCF02S XCF04S XCF08P XCF16P XCF32P Notes:
IDCODE field represents device's revision code hex) vary.
Platform Flash PROM Characteristics
Platform Flash PROM family performs both in-system programming IEEE 1149.1 boundary-scan (JTAG) testing single 4-wire Test Access Port (TAP). This simplifies system designs allows standard Automatic Test Equipment perform both functions. characteristics Platform Flash PROM described follows.
IDCODE (hex)
<v>5044093 <v>5045093 <v>5046093 <v>5057093 <v>5058093 <v>5059093
Timing
Figure page shows timing relationships signals. These timing characteristics identical both boundary-scan operations.
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Platform Flash In-System Programmable Configuration PROMS
TCKMIN
TMSS TMSH
TDIS TDIH
TDOV
DS026_04_020300
Figure Test Access Port Timing
Parameters
Table shows timing parameters waveforms shown Figure Table Test Access Port Timing Parameters
Symbol
TCKMIN TMSS TMSH TDIS TDIH TDOV
Description
minimum clock period when VCCJ 2.5V 3.3V setup time when VCCJ 2.5V 3.3V hold time when VCCJ 2.5V 3.3V setup time when VCCJ 2.5V 3.3V hold time when VCCJ 2.5V 3.3V valid delay when VCCJ 2.5V 3.3V
Units
Additional Features XCFxxP
Internal Oscillator
8/16/32 Mbit XCFxxP Platform Flash PROMs include optional internal oscillator which used drive CLKOUT DATA pins FPGA configuration interface. internal oscillator enabled when programming PROM, oscillator either default frequency slower frequency ("XCFxxP PROM Configuration Master with Internal Oscillator Clock Source," page 33).
CLKOUT signal enabled during programming, active when OE/RESET High. rising edge transition, OE/RESET High PROM terminal count been reached, then CLKOUT remains active additional eights clock cycles before being disabled. OE/RESET falling edge transition, CLKOUT immediately disabled. When disabled, CLKOUT into high-impedance state should pulled High externally provide known state. When cascading Platform Flash PROMs with CLKOUT enabled, after completing it's data transfer, first PROM disables CLKOUT drives enabling next PROM PROM chain. next PROM will begin driving CLKOUT signal once that PROM enabled data available transfer. During high-speed parallel configuration without compression, FPGA drives BUSY signal configuration interface. When BUSY asserted High, PROMs internal address counter stops incrementing, current data value held data outputs. While BUSY High, PROM will continue driving CLKOUT signal FPGA, clocking FPGA's configuration logic.
CLKOUT
8/16/32 Mbit XCFxxP Platform Flash PROMs include programmable option enable CLKOUT signal which allows PROM provide source synchronous clock aligned data configuration interface. CLKOUT signal derived from clock sources: input internal oscillator. input clock source selected during PROM programming sequence. Output data available rising edge CLKOUT.
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Platform Flash In-System Programmable Configuration PROMS single 32-Mbit PROM contains four 8-Mbit memory blocks, therefore store four separate design revisions: 32-Mbit design revision, 16-Mbit design revisions, three 8-Mbit design revisions, four 8-Mbit design revisions, Because 8-Mbit minimum size requirement each revision, single 16-Mbit PROM only store separate design revisions: 16-Mbit design revision, 8-Mbit design revision, 8-Mbit design revisions. single 8-Mbit PROM store only 8-Mbit design revision.
When FPGA deasserts BUSY, indicating that ready receive additional configuration data, PROM will begin driving data onto configuration interface.
Decompression
8/16/32 Mbit XCFxxP Platform Flash PROMs include built-in data decompressor compatible with Xilinx advanced compression technology. Compressed Platform Flash PROM files created from target FPGA bitstream(s) using iMPACT software. Only Slave Serial Slave SelectMAP (parallel) configuration modes supported FPGA configuration when using XCFxxP PROM programmed with compressed bitstream. Compression rates will vary depending several factors, including target device family target design contents. decompression option enabled during PROM programming sequence. PROM decompresses stored data before driving both clock data onto FPGA's configuration interface. Decompression enabled, then Platform Flash clock output (CLKOUT) must used clock signal configuration interface, driving target FPGA's configuration clock input (CCLK). Either PROM's input internal oscillator must selected source CLKOUT. target FPGA connected PROM must operate slave configuration chain, with configuration mode Slave Serial mode Slave SelectMap (parallel) mode. When decompression enabled, CLKOUT signal becomes controlled clock output with reduced maximum frequency. When decompressed data ready, CLKOUT into high-Z state must pulled High externally provide known state. BUSY input automatically disabled when decompression enabled.
Larger design revisions split over several cascaded PROMs. example, 32-Mbit PROMs store four separate design revisions: 64-Mbit design revision, 32-Mbit design revisions, three 16-Mbit design revisions, four 16-Mbit design revisions, When cascading 16-Mbit PROM 8-Mbit PROM, there Mbits available space, therefore three separate design revisions stored: 24-Mbit design revision, 8-Mbit design revisions, three 8-Mbit design revisions. Figure page basic examples multiple revisions stored. design revision partitioning handled automatically during file generation iMPACT. During PROM file creation, each design revision assigned revision number: Revision '00' Revision '01' Revision '10' Revision '11' After programming Platform Flash PROM with design revisions, particular design revision selected using external REV_SEL[1:0] pins using internal programmable design revision control bits. EN_EXT_SEL determines external pins internal bits used select design revision. When EN_EXT_SEL Low, design revision selection controlled external Revision Select pins, REV_SEL[1:0]. When EN_EXT_SEL High, design revision selection controlled internal programmable Revision Select control bits. During power design revision selection inputs (pins control bits) sampled internally. After power design revision selection inputs sampled again when following events occur: rising edge falling edge OE/RESET (when Low) rising edge (when Low) When reconfiguration initiated using JTAG CONFIG instruction.
Design Revisioning
Design Revisioning allows user create four unique design revisions single PROM stored across multiple cascaded PROMs. Design Revisioning supported 8/16/32 Mbit XCFxxP Platform Flash PROMs both serial parallel modes. Design Revisioning used with compressed PROM files, also when CLKOUT feature enabled. PROM programming files along with revision information files (.cfi) created using iMPACT software. .cfi file required enable design revision programming iMPACT. single design revision composed from 8-Mbit memory blocks. single design revision contains less than Mbits data, then remaining space padded with ones. larger design revision span several 8-Mbit memory blocks, space remaining last 8-Mbit memory block padded with ones.
data from selected design revision then presented FPGA configuration interface.
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Platform Flash In-System Programmable Configuration PROMS
PROM Mbits)
PROM Mbits)
PROM
PROM Mbits)
PROM
Mbits) Mbits) Mbits) Mbits) Mbits) Mbits) Mbits) Mbits) Mbits)
Design Revisions
Design Revisions
Design Revisions
Design Revision
Design Revision storage examples single XCF32P PROM PROM Mbits) PROM Mbits) Mbits) Mbits) Mbits) Mbits) PROM PROM Mbits) Mbits) PROM
PROM Mbits)
PROM
PROM
PROM
PROM
Mbits) Mbits)
Mbits)
Mbits)
Mbits)
Design Revisions
Design Revisions
Design Revisions
Design Revision
ds123_20_102103
Design Revision storage examples spanning XCF32P PROMs
Figure Design Revision Storage Examples
PROM FPGA Configuration Mode Connections Summary
FPGA's I/O, logical functions, internal interconnections established configuration data contained FPGA's bitstream. bitstream loaded into FPGA either automatically upon power command, depending state FPGA's mode pins. Xilinx Platform Flash PROMs designed download directly FPGA configuration interface. FPGA configuration modes which supported XCFxxS Platform Flash PROMs include: Master Serial Slave Serial. FPGA configuration modes which supported XCFxxP Platform Flash PROMs include: Master Serial, Slave Serial, Master SelectMAP, Slave SelectMAP. Below short summary supported FPGA configuration modes. respective FPGA data sheet device configuration details, including which configuration modes supported targeted FPGA device.
FPGA Master Serial Mode
Master Serial mode, FPGA automatically loads configuration bitstream bit-serial form from external memory synchronized configuration clock (CCLK) generated FPGA. Upon power-up reconfiguration, FPGA's mode select pins used select Master Serial configuration mode. Master Serial Mode provides simple configuration interface. Only serial data line, clock line, control lines (INIT DONE) required configure FPGA. Data from PROM read sequentially single data line (DIN), accessed PROM's internal address counter which incremented every valid rising edge CCLK. serial bitstream data must FPGA's input short time before each rising edge FPGA's internally generated CCLK signal. Typically, wide range frequencies selected FPGA's internally generated CCLK which always starts
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Platform Flash In-System Programmable Configuration PROMS output PROM drives input next PROM daisy chain any). OE/RESET pins PROMs connected INIT_B INIT) pins FPGA devices. This connection assures that PROM address counter reset before start (re)configuration. PROM input driven from DONE pin. input first only) PROM driven DONE output target FPGA devices, provided that DONE permanently grounded. also permanently tied Low, this keeps DATA output active causes unnecessary active supply current ("DC Characteristics Over Operating Conditions," page 26). PROM typically connected FPGA's PROG_B PROGRAM) input. XCFxxP only, bidirectional pin. XCFxxP connected FPGA's PROG_B PROGRAM) input, then should tied High.
slow default frequency. FPGA's bitstream contains configuration bits which switch CCLK higher frequency remainder Master Serial configuration sequence. desired CCLK frequency selected during bitstream generation. Connecting FPGA device configuration PROM Master Serial Configuration Mode (Figure page 14): DATA output PROM(s) drive input lead FPGA device. Master FPGA CCLK output drives input(s) PROM(s) output PROM drives input next PROM daisy chain any). OE/RESET pins PROMs connected INIT_B pins FPGA devices. This connection assures that PROM address counter reset before start (re)configuration. PROM input driven from DONE pin. input first only) PROM driven DONE output target FPGA devices, provided that DONE permanently grounded. also permanently tied Low, this keeps DATA output active causes unnecessary active supply current ("DC Characteristics Over Operating Conditions," page 26). PROM typically connected FPGA's PROG_B PROGRAM) input. XCFxxP only, bidirectional pin. XCFxxP connected FPGA's PROG_B PROGRAM) input, then should tied High.
Serial Daisy Chain
Multiple FPGAs daisy-chained serial configuration from single source. After particular FPGA been configured, data next device routed internally FPGA's DOUT pin. Typically data DOUT changes falling edge CCLK, although some devices DOUT changes rising edge CCLK. Consult respective device data sheets detailed information particular FPGA device. clocking daisy-chained configuration, either first FPGA chain Master Serial, generating CCLK, with remaining devices Slave Serial (Figure page 16), FPGA devices Slave Serial externally generated clock used drive FPGA's configuration interface (Figure page Figure page 20).
FPGA Slave Serial Mode
Slave Serial mode, FPGA loads configuration bitstream bit-serial form from external memory synchronized externally supplied clock. Upon power-up reconfiguration, FPGA's mode select pins used select Slave Serial configuration mode. Slave Serial Mode provides simple configuration interface. Only serial data line, clock line, control lines (INIT DONE) required configure FPGA. Data from PROM read sequentially single data line (DIN), accessed PROM's internal address counter which incremented every valid rising edge CCLK. serial bitstream data must FPGA's input short time before each rising edge externally provided CCLK. Connecting FPGA device configuration PROM Slave Serial Configuration Mode (Figure page 15): DATA output PROM(s) drive input lead FPGA device. PROM CLKOUT (for XCFxxP only) external clock source drives FPGA's CCLK input.
FPGA Master SelectMAP (Parallel) Mode (XCFxxP PROM Only)
Master SelectMAP mode, byte-wide data written into FPGA, typically with BUSY flag controlling flow data, synchronized configuration clock (CCLK) generated FPGA. Upon power-up reconfiguration, FPGA's mode select pins used select Master SelectMAP configuration mode. configuration interface typically requires parallel data bus, clock line, control lines (INIT DONE). addition, FPGA's Chip Select, Write, BUSY pins must correctly controlled enable SelectMAP configuration. configuration data read from PROM byte byte pins [D0.D7], accessed PROM's internal address counter which incremented every valid rising edge CCLK. bitstream data must FPGA's [D0.D7] input pins short time before each rising edge FPGA's
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Platform Flash In-System Programmable Configuration PROMS
internally generated CCLK signal. BUSY asserted (High) FPGA, configuration data must held until BUSY goes Low. external data source external pull-down resistors must used enable FPGA's active Chip Select CS_B) Write (WRITE RDWR_B) signals enable FPGA's SelectMAP configuration process. Master SelectMAP configuration interface clocked FPGA's internal oscillator. Typically, wide range frequencies selected internally generated CCLK which always starts slow default frequency. FPGA's bitstream contains configuration bits which switch CCLK higher frequency remainder Master SelectMAP configuration sequence. desired CCLK frequency selected during bitstream generation. After configuration, pins SelectMAP port used additional user I/O. Alternatively, port retained using persist option. Connecting FPGA device configuration PROM Master SelectMAP (Parallel) Configuration Mode (Figure page 17): DATA outputs PROM(s) drive [D0.D7] input lead FPGA device. Master FPGA CCLK output drives input(s) PROM(s) output PROM drives input next PROM daisy chain any). OE/RESET pins PROMs connected INIT_B pins FPGA devices. This connection assures that PROM address counter reset before start (re)configuration. PROM input driven from DONE pin. input first only) PROM driven DONE output target FPGA devices, provided that DONE permanently grounded. also permanently tied Low, this keeps DATA output active causes unnecessary active supply current ("DC Characteristics Over Operating Conditions," page 26). high-frequency parallel configuration, BUSY pins PROMs connected FPGA's BUSY output. This connection assures that next data transition PROM delayed until FPGA ready next configuration data byte. PROM typically connected FPGA's PROG_B PROGRAM) input. XCFxxP only, bidirectional pin. XCFxxP connected FPGA's PROG_B PROGRAM) input, then should tied High.
FPGA Slave SelectMAP (Parallel) Mode (XCFxxP PROM Only)
Slave SelectMAP mode, byte-wide data written into FPGA, typically with BUSY flag controlling flow data, synchronized externally supplied configuration clock (CCLK). Upon power-up reconfiguration, FPGA's mode select pins used select Slave SelectMAP configuration mode. configuration interface typically requires parallel data bus, clock line, control lines (INIT DONE). addition, FPGA's Chip Select, Write, BUSY pins must correctly controlled enable SelectMAP configuration. configuration data read from PROM byte byte pins [D0.D7], accessed PROM's internal address counter which incremented every valid rising edge CCLK. bitstream data must FPGA's [D0.D7] input pins short time before each rising edge provided CCLK. BUSY asserted (High) FPGA, configuration data must held until BUSY goes Low. external data source external pull-down resistors must used enable FPGA's active Chip Select CS_B) Write (WRITE RDWR_B) signals enable FPGA's SelectMAP configuration process. After configuration, pins SelectMAP port used additional user I/O. Alternatively, port retained using persist option. Connecting FPGA device configuration PROM Slave SelectMAP (Parallel) Configuration Mode (Figure page 18): DATA outputs PROM(s) drives [D0.D7] inputs lead FPGA device. PROM CLKOUT (for XCFxxP only) external clock source drives FPGA's CCLK input. output PROM drives input next PROM daisy chain any). OE/RESET pins PROMs connected INIT_B pins FPGA devices. This connection assures that PROM address counter reset before start (re)configuration. PROM input driven from DONE pin. input first only) PROM driven DONE output target FPGA devices, provided that DONE permanently grounded. also permanently tied Low, this keeps DATA output active causes unnecessary active supply current ("DC Characteristics Over Operating Conditions," page 26). high-frequency parallel configuration, BUSY pins PROMs connected FPGA's BUSY output. This connection assures that next data transition PROM delayed until FPGA ready next configuration data byte.
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Platform Flash In-System Programmable Configuration PROMS PROMs chain interconnected. After last data from first PROM read, first PROM asserts output drives outputs high-impedance state. second PROM recognizes level input immediately enables outputs. After configuration complete, address counters cascaded PROMs reset PROM OE/RESET goes goes High. When utilizing advanced features XCFxxP Platform Flash PROM, including clock output (CLKOUT) option, decompression option, design revisioning, programming files which span cascaded PROM devices only created cascaded chains containing only XCFxxP PROMs. advanced features used, then cascaded PROM chains contain both XCFxxP XCFxxS PROMs.
PROM typically connected FPGA's PROG_B PROGRAM) input. XCFxxP only, bidirectional pin. XCFxxP connected FPGA's PROG_B PROGRAM) input, then should tied High.
FPGA SelectMAP (Parallel) Device Chaining (XCFxxP PROM Only)
Multiple Virtex-II FPGAs configured using SelectMAP mode, made start simultaneously. configure multiple devices this way, wire individual CCLK, DONE, INIT, Data ([D0.D7]), Write (WRITE RDWR_B), BUSY pins devices parallel. devices configured with same bitstream, readback being used, CCLK frequency selected does require BUSY signal, CS_B pins connected common line devices configured simultaneously (Figure page 18). With additional control logic, individual devices loaded separately asserting CS_B each device turn then enabling appropriate configuration data. PROM also store individual bitstreams each FPGA SelectMAP configuration separate design revisions. When design revisioning utilized, additional control logic used select appropriate bitstream asserting EN_EXT_SEL pin, using REV_SEL[1:0] pins select required bitstream, while asserting CS_B FPGA bitstream targeting (Figure page 21). clocking parallel configuration chain, either first FPGA chain Master SelectMAP, generating CCLK, with remaining devices Slave SelectMAP, FPGA devices Slave SelectMAP externally generated clock used drive configuration interface. Again, respective device data sheets should consulted detailed information particular FPGA device, including which configuration modes supported targeted FPGA device.
Initiating FPGA Configuration
options initiating FPGA configuration Platform Flash PROM include: Automatic configuration power Applying external PROG_B PROGRAM) pulse Applying JTAG CONFIG instruction
Following FPGA's power-on sequence assertion PROG_B PROGRAM) FPGA's configuration memory cleared, configuration mode selected, FPGA ready accept configuration bitstream. FPGA's PROG_B controlled external source, alternatively, Platform Flash PROMs incorporate that tied FPGA's PROG_B pin. Executing CONFIG instruction through JTAG pulses output once 300-500 resetting FPGA initiating configuration. iMPACT software issue JTAG CONFIG command initiate FPGA configuration setting "Load FPGA" option. When using XCFxxP Platform Flash PROM with design revisioning enabled, should always connected PROG_B PROGRAM) FPGA ensure that current design revision selection sampled when FPGA reset. XCFxxP PROM samples current design revision selection from external REV_SEL pins internal programmable Revision Select bits rising edge When JTAG CONFIG command executed, XCFxxP will sample design revision selection before initiating FPGA configuration sequence. When using XCFxxP Platform Flash PROM without design revisioning, connected FPGA PROG_B PROGRAM) pin, then XCFxxP must tied High.
Cascading Configuration PROMs
When configuring multiple FPGAs serial daisy chain, configuring multiple FPGAs SelectMAP parallel chain, configuring single FPGA requiring larger configuration bitstream, cascaded PROMs provide additional memory (Figure page Figure page Figure page Figure page 21). Multiple Platform Flash PROMs concatenated using output drive input downstream device. clock signal data outputs Platform Flash
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Platform Flash In-System Programmable Configuration PROMS
Configuration PROM FPGA Device Interface Connection Diagrams
VCCO
VCCJ VCCO VCCINT
VCCINT VCCO(2) VCCJ
MODE PINS
CCLK
Platform Flash PROM
OE/RESET
Xilinx FPGA Master Serial
CCLK DONE DOUT INIT_B PROG_B
DONE INIT_B PROG_B
.OPTIONAL Slave FPGAs with identical configurations
CCLK DONE INIT_B PROG_B
.OPTIONAL Daisy-chained Slave FPGAs with different configurations
Notes: Mode connections DONE pull-up value, refer appropriate FPGA data sheet. compatible voltages, refer appropriate data sheet. XCFxxS output pin. XCFxxP bidirectional pin. XCFxxP, connected PROGB, then must tied VCCO pull-up resistor.
ds123_11_122105
Figure Configuring Master Serial Mode
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Platform Flash In-System Programmable Configuration PROMS
VCCO External Oscillator
VCCJ VCCO VCCINT
VCCINT
VCCO VCCJ
MODE PINS
CCLK
Platform Flash PROM
Xilinx FPGA Slave Serial
CCLK DONE DOUT INIT_B PROG_B
DONE INIT_B PROG_B
.OPTIONAL Slave FPGAs with identical configurations
OE/RESET
CCLK DONE INIT_B PROG_B
.OPTIONAL Daisy-chained Slave FPGAs with different configurations
Notes: Mode connections DONE pull-up value, refer appropriate FPGA data sheet. compatible voltages, refer appropriate data sheet. Slave Serial mode, configuration interface clocked external oscillator, optionally-for XCFxxP Platform Flash PROM only-the CLKOUT signal used drive FPGA's configuration clock (CCLK). XCFxxP PROM's CLKOUT signal used, then CLKOUT must tied 4.7K resistor pulled VCCO. XCFxxS output pin. XCFxxP bidirectional pin. XCFxxP, connected PROGB, then must tied VCCO pull-up resistor.
ds123_12_122105
Figure Configuring Slave Serial Mode
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Platform Flash In-System Programmable Configuration PROMS
VCCJ VCCO VCCINT
VCCJ VCCO VCCINT
VCCO(2)
VCCINT VCCO(2) VCCJ
VCCINT VCCO(2) VCCJ
MODE PINS
MODE PINS(1)
DOUT
Platform Flash PROM Cascaded PROM (PROM
OE/RESET
Platform Flash PROM First PROM (PROM
OE/RESET
Xilinx FPGA Master Serial
CCLK DONE INIT_B PROG_B
Xilinx FPGA Slave Serial
CCLK DONE INIT_B PROG_B
Notes: Mode connections DONE pull-up value, refer appropriate FPGA data sheet. compatible voltages, refer appropriate data sheet. XCFxxS output pin. XCFxxP bidirectional pin. XCFxxP, connected PROGB, then must tied VCCO pull-up resistor.
ds123_13_122105
Figure Configuring Multiple Devices Master/Slave Serial Mode
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Platform Flash In-System Programmable Configuration PROMS
VCCO(2)
VCCJ VCCO VCCINT
VCCINT VCCO(2) VCCJ
D[0:7]
D[0:7]
MODE PINS
I/O(3)
RDWR_B CS_B
XCFxxP Platform Flash PROM
OE/RESET BUSY
Xilinx FPGA Master SelectMAP
CCLK DONE
D[0:7] INIT_B PROG_B BUSY(4) CCLK DONE INIT_B PROG_B BUSY
.OPTIONAL Slave FPGAs with identical configurations
Notes: Mode connections DONE pull-up value, refer appropriate FPGA data sheet. compatible voltages, refer appropriate data sheet. CS_B RDWR_B WRITE) must either driven pulled down exernally. option shown. BUSY only available with XCFxxP Platform Flash PROM, connection only required highfrequency SelectMAP mode configuration. BUSY requirements, refer appropriate FPGA data sheet. XCFxxP bidirectional pin. XCFxxP, connected PROGB, then must tied VCCO pull-up resistor.
ds123_14_122105
Figure Configuring Master SelectMAP Mode
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Platform Flash In-System Programmable Configuration PROMS
VCCO External Oscillator
VCCJ VCCO VCCINT
VCCINT VCCO VCCJ
D[0:7]
D[0:7]
MODE PINS
RDWR_B CS_B
XCFxxP Platform Flash PROM
Xilinx FPGA Slave SelectMAP
CCLK DONE
OE/RESET BUSY
D[0:7] INIT_B PROG_B BUSY(4) CCLK DONE INIT_B PROG_B BUSY
.OPTIONAL Slave FPGAs with identical configurations
Notes: Mode connections DONE pull-up value, refer appropriate FPGA data sheet. compatible voltages, refer appropriate data sheet. CS_B RDWR_B WRITE) must either driven pulled down externally. option shown. BUSY only available with XCFxxP Platform Flash PROM, connection only required highfrequency SelectMAP mode configuration. BUSY requirements, refer appropriate FPGA data sheet. Slave SelectMAP mode, configuration interface clocked external oscillator, optionally, CLKOUT signal used drive FPGA's configuration clock (CCLK). XCFxxP PROM's CLKOUT signal used, then CLKOUT must tied resistor pulled VCCO. XCFxxP bidirectional pin. XCFxxP, connected PROGB, then must tied VCCO pull-up resistor.
ds123_15_122105
Figure Configuring Slave SelectMAP Mode
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Platform Flash In-System Programmable Configuration PROMS
VCCJ VCCO VCCINT
VCCJ VCCO VCCINT
VCCO(2)
VCCINT VCCO VCCJ
D[0:7]
VCCINT VCCO VCCJ
D[0:7]
D[0:7]
MODE PINS
D[0:7] I/O(3)
MODE PINS
I/O(3) RDWR_B CS_B
RDWR_B CS_B
XCFxxP Platform Flash PROM Cascaded PROM (PROM
XCFxxP Platform Flash PROM First PROM (PROM
Xilinx FPGA Master SelectMAP
CCLK DONE INIT_B PROG_B BUSY
Xilinx FPGA Slave SelectMAP
CCLK DONE INIT_B PROG_B BUSY
OE/RESET BUSY(4)
OE/RESET BUSY
Notes: Mode connections DONE pull-up value, refer appropriate FPGA data sheet. compatible voltages, refer appropriate data sheet. CS_B RDWR_B WRITE) must either driven pulled down exernally. option shown. BUSY only available with XCFxxP Platform Flash PROM, connection only required highfrequency SelectMAP mode configuration. BUSY requirements, refer appropriate FPGA data sheet. XCFxxP bidirectional pin. XCFxxP, connected PROGB, then must tied VCCO pull-up resistor.
ds123_16_122105
Figure Configuring Multiple Devices with Identical Patterns Master/Slave SelectMAP Mode
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Platform Flash In-System Programmable Configuration PROMS
VCCJ VCCO VCCINT
VCCJ VCCO VCCINT
VCCO
External Oscillator
VCCINT VCCO
VCCINT VCCO VCCJ
MODE PINS(1) DOUT
MODE PINS
VCCJ(2)
XCFxxP Platform Flash PROM Cascaded PROM (PROM
XCFxxP Platform Flash PROM First PROM (PROM
Xilinx FPGA Slave Serial
CCLK DONE INIT_B PROG_B
Xilinx FPGA Slave Serial
CCLK DONE INIT_B PROG_B
OE/RESET
OE/RESET
EN_EXT_SEL REV_SEL[1:0]
EN_EXT_SEL REV_SEL[1:0]
EN_EXT_SEL Design Revision Control Logic REV_SEL[1:0] DONE PROG_B Notes Mode connections DONE pull-up value, refer appropriate FPGA data sheet. compatible voltages, refer appropriate data sheet. Slave Serial mode, configuration interface clocked external oscillator, optionally CLKOUT signal used drive FPGA's configuration clock (CCLK). XCFxxP PROM's CLKOUT signal used, then CLKOUT must tied resistor pulled VCCO. XCFxxP bidirectional pin. XCFxxP, connected PROGB, then
must tied VCCO pull-up resistor.
ds123_17_122105
Figure Configuring Multiple Devices with Design Revisioning Slave Serial Mode
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Platform Flash In-System Programmable Configuration PROMS
VCCJ
VCCO VCCINT
VCCJ
VCCO VCCINT
VCCO
External Oscillator
VCCINT VCCO VCCJ
D[0:7]
VCCINT VCCO VCCJ
D[0:7]
D[0:7]
MODE PINS
D[0:7]
MODE PINS
RDWR_B CS_B
RDWR_B CS_B
XCFxxP Platform Flash PROM Cascaded PROM (PROM
XCFxxP Platform Flash PROM First PROM (PROM
CLK(5)
Xilinx FPGA Slave SelectMAP
CCLK DONE INIT_B PROG_B BUSY(4)
Xilinx FPGA Slave SelectMAP
CCLK DONE INIT_B PROG_B BUSY(4)
OE/RESET BUSY
OE/RESET
BUSY
EN_EXT_SEL REV_SEL[1:0]
EN_EXT_SEL REV_SEL[1:0]
EN_EXT_SEL Design Revision Control Logic REV_SEL[1:0] DONE PROG_B CS_B[1:0]
Notes: Mode connections DONE pull-up value, refer appropriate FPGA data sheet. compatible voltages, refer appropriate data sheet. RDWR_B WRITE) must either driven pulled down exernally. option shown. BUSY only available with XCFxxP Platform Flash PROM, connection only required high frequency SelectMAP mode configuration. BUSY requirements, refer appropriate FPGA data sheet. Slave SelectMAP mode, configuration interface clocked external oscillator, optionally CLKOUT signal used drive FPGA's configuration clock (CCLK). XCFxxP PROM's CLKOUT signal used, then must tied 4.7K resistor pulled VCCO. XCFxxP bidirectional pin. XCFxxP, connected PROGB, then must tied VCCO pull-up resistor
ds123_18_122105
Figure Configuring Multiple Devices with Design Revisioning Slave SelectMAP Mode
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Platform Flash In-System Programmable Configuration PROMS
Reset Power-On Reset Activation
power device requires VCCINT power supply monotonically rise nominal operating voltage within specified VCCINT rise time. power supply cannot meet this requirement, then device might perform power-on reset properly. During power-up sequence, OE/RESET held PROM. Once required supplies have reached their respective (Power Reset) thresholds, OE/RESET release delayed (TOER minimum) allow more margin power supplies stabilize before initiating configuration. OE/RESET connected external 4.7k pull-up resistor also target FPGA's INIT pin. systems utilizing slow-rising power supplies, additional power monitoring circuit used delay target configuration until system power reaches minimum operating voltages holding OE/RESET Low. When OE/RESET released, FPGA's INIT pulled High allowing FPGA's configuration sequence begin. power drops below power-down threshold (VCCPD), PROM resets OE/RESET again held until after threshold reached. OE/RESET polarity programmable. These power-up requirements shown graphically Figure page fully powered Platform Flash PROM, reset occurs whenever OE/RESET asserted (Low) deasserted (High). address counter reset, driven High, remaining outputs placed high-impedance state. Notes: XCFxxS PROM only requires VCCINT rise above threshold before releasing OE/RESET. XCFxxP PROM requires both VCCINT rise above threshold VCCO reach recommended operating voltage level before releasing OE/RESET.
VCCINT
Recommended Operating Range Delay Restart Configuration
ramp
ramp
VCCPOR VCCPD
slow-ramping VCCINT supply still below minimum operating voltage when OE/RESET released. this case, configuration sequence must delayed until both VCCINT VCCO have reached their recommended operating conditions.
TIME (ms) TRST
ds123_21_103103
Figure Platform Flash PROM Power-Up Requirements
Input Voltage Tolerance Power Sequencing
I/Os each re-programmable Platform Flash PROM fully 3.3V-tolerant. This allows CMOS signals connect directly inputs without damage. core power supply (VCCINT), JTAG power supply (VCCJ), output power supply (VCCO), external CMOS signals applied order. Additionally, XCFxxS PROM only, when VCCO supplied 2.5V 3.3V VCCINT supplied 3.3V, I/Os 5V-tolerant. This allows CMOS signals connect directly inputs powered XCFxxS PROM without damage. Failure power PROM correctly while supplying input signal result damage XCFxxS device.
Standby Mode
PROM enters low-power standby mode whenever deasserted (High). standby mode, address counter reset, driven High, remaining outputs placed high-impedance state regardless state OE/RESET input. device remain low-power standby mode, JTAG pins TMS, TDI, must pulled Low, must stopped (High Low). When using FPGA DONE signal drive PROM High reduce standby power after configuration, external pull-up resistor should used. Typically
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Platform Flash In-System Programmable Configuration PROMS external buffer should used drive circuit ensure valid transitions PROM's pin. low-power standby mode required PROM, then should connected ground.
pull-up resistor used, refer appropriate FPGA data sheet recommended DONE pull-up value. DONE circuit connected indicate FPGA configuration complete, also connected PROM enable low-power standby mode, then Table Truth Table XCFxxS PROM Control Inputs
Control Inputs OE/RESET
High Notes:
don't care. Terminal Count highest address value.
High
Internal Address
address increment address don't change Held reset Held reset
Outputs DATA
Active High-Z High-Z High-Z
High High High
Active Reduced Active Standby
Table Truth Table XCFxxP PROM Control Inputs
Control Inputs OE/RESET BUSY(5) Internal Address
address address High High increment
Outputs DATA
Active High-Z High-Z Active Unchanged Active High-Z High-Z
High High High High High High
CLKOUT
Active High-Z High-Z Active Active High-Z High-Z
Active Reduced Reduced Active Active Active Standby
address address don't change Else address don't change
High High Notes:
High
High
High
Unchanged Reset Held Held reset reset
don't care. Terminal Count highest address value. XCFxxP with Design Revisioning enabled, address (last address selected design revision). XCFxxP with Design Revisioning enabled, Reset address reset beginning address selected bank. Design Revisioning enabled, then Reset address reset address BUSY input only enabled when XCFxxP programmed parallel data output decompression enabled.
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Electrical Characteristics
Absolute Maximum Ratings
Symbol
VCCINT VCCO VCCJ TSTG Notes:
Maximum undershoot below must limited either 0.5V whichever easier achieve. During transitions, device pins undershoot -2.0V overshoot +7.0V, provided this over- undershoot lasts less then with forcing current being limited Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those listed under Operating Conditions implied. Exposure Absolute Maximum Ratings conditions extended periods time adversely affects device reliability. soldering guidelines, information "Packaging Thermal Characteristics" www.xilinx.com.
Description
Internal supply voltage relative supply voltage relative JTAG supply voltage relative Input voltage with respect VCCO 2.5V VCCO 2.5V Voltage applied High-Z output VCCO 2.5V VCCO 2.5V Storage temperature (ambient) Junction temperature
XCF01S, XCF02S, XCF04S
-0.5 +4.0 -0.5 +4.0 -0.5 +4.0 -0.5 +3.6 -0.5 +5.5 -0.5 +3.6 -0.5 +5.5 +150 +125
XCF08P, XCF16P, XCF32P
-0.5 +2.7 -0.5 +4.0 -0.5 +4.0 -0.5 +3.6 -0.5 +3.6 -0.5 +3.6 -0.5 +3.6 +150 +125
Units
Supply Voltage Requirements Power-On Reset Power-Down
Symbol
TVCC VCCPOR TOER VCCPD TRST Notes:
VCCINT, VCCO, VCCJ supplies applied order. power device requires VCCINT power supply monotonically rise nominal operating voltage within specified TVCC rise time. power supply cannot meet this requirement, then device might perform power-on-reset properly. Figure page VCCINT VCCO supplies reach their respective recommended operating conditions before OE/RESET released, then configuration data from PROM will available recommended threshold levels. configuration sequence must delayed until both VCCINT VCCO have reached their recommended operating conditions.
Description
VCCINT rise time from nominal voltage threshold VCCINT supply OE/RESET release delay following Power-down threshold VCCINT supply Time required trigger device reset when VCCINT supply drops below maximum VCCPD threshold
XCF01S, XCF02S, XCF04S
XCF08P, XCF16P, XCF32P
Units
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Platform Flash In-System Programmable Configuration PROMS
Recommended Operating Conditions
Symbol
VCCINT VCCO Supply voltage output drivers
Description
Internal voltage supply 3.3V Operation 2.5V Operation 1.8V Operation 1.5V Operation
XCF01S, XCF02S, XCF04S
VCCO
XCF08P, XCF16P, XCF32P
1.65 VCCO
VCCO VCCO
VCCO VCCO
Units
VCCJ
Supply voltage JTAG output drivers
3.3V Operation 2.5V Operation 3.3V Operation
Low-level input voltage
2.5V Operation 1.8V Operation 1.5V Operation
3.3V Operation High-level input 2.5V Operation voltage 1.8V Operation 1.5V Operation time(1)
Notes:
Input signal transition Output voltage
Operating ambient temperature
Input signal transition time measured between VCCO VCCO
Quality Reliability Characteristics
Symbol
VESD Data retention Program/erase cycles (Endurance) Electrostatic discharge (ESD)
Description
20,000 2,000
Units
Years Cycles Volts
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Platform Flash In-System Programmable Configuration PROMS
Characteristics Over Operating Conditions
XCF01S, XCF02S, XCF04S Test Conditions -500 Note Note Note Note VCCJ
VCCINT VCCO VCCO VCCINT VCCO VCCO
Symbol
Description
XCF08P, XCF16P, XCF32P Test Conditions -500 Note Note Note Note VCCJ
VCCINT VCCO VCCO VCCINT VCCO VCCO VCCINT VCCO VCCO VCCINT VCCO VCCO
Units
VCCO VCCO
VCCO VCCO
High-level output voltage 3.3V outputs High-level output voltage 2.5V outputs High-level output voltage 1.8V outputs High-level output voltage 1.5V outputs Low-level output voltage 3.3V outputs Low-level output voltage 2.5V outputs Low-level output voltage 1.8V outputs Low-level output voltage 1.5V outputs ICCINT ICCO ICCJ ICCINTS ICCOS ICCJS IILJ Internal voltage supply current, active mode Output driver supply current, active serial mode Output driver supply current, active parallel mode JTAG supply current, active mode Internal voltage supply current, standby mode Output driver supply current, standby mode JTAG supply current, standby mode JTAG pins TMS, TDI, pull-up current
Input leakage current
Input output High-Z leakage current
IILP
Source current through internal pull-ups EN_EXT_SEL, REV_SEL0, REV_SEL1
IIHP
Sink current through internal pull-down BUSY
-100
COUT Notes:
Input capacitance Output capacitance
Output driver supply current specification based load conditions. TDI/TMS/TCK non-static (active). High, Low, TMS/TDI/TCK static.
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Platform Flash In-System Programmable Configuration PROMS
Electrical Characteristics
Characteristics Over Operating Conditions
XCFxxS XCFxxP PROM Configuration Slave with Input Clock Source
TSCE THCE TCYC THOE
OE/RESET
BUSY (optional) DATA
TCAC
THCF
EN_EXT_SEL
TSXT
THXT
TSXT
THXT
REV_SEL[1:0]
TSRV
THRV
TSRV
THRV
ds123_22_122905
Symbol
Description
XCF01S, XCF02S, XCF04S
XCF08P, XCF16P, XCF32P
Units
THCF
hold time guarantee design revision selection sampled when VCCO 3.3V 2.5V(9) hold time guarantee design revision selection sampled when VCCO 1.8V(9) data delay when VCCO 3.3V 2.5V(8)
data delay when VCCO 1.8V(8) OE/RESET data delay when VCCO 3.3V 2.5V
OE/RESET data delay when VCCO 1.8V data delay when VCCO 3.3V 2.5V
data delay when VCCO 1.8V data delay when VCCO 3.3V 2.5V
TCAC
data delay when VCCO 1.8V Data hold from OE/RESET, CLK, when VCCO 3.3V 2.5V(8) Data hold from OE/RESET, CLK, when VCCO 1.8V(8)
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Platform Flash In-System Programmable Configuration PROMS
Symbol
Description
OE/RESET data float delay when VCCO 3.3V 2.5V OE/RESET data float delay when VCCO 1.8V Clock period (serial mode) when VCCO 3.3V 2.5V
XCF01S, XCF02S, XCF04S
counting)
XCF08P, XCF16P, XCF32P
2000 2000 2000 2000
Units
TCYC
Clock period (serial mode) when VCCO 1.8V Clock period (parallel mode) when VCCO 3.3V 2.5V
Clock period (parallel mode) when VCCO 1.8V time(3) when VCCO 3.3V 2.5V
time(3) when VCCO 1.8V High time(3) when VCCO 3.3V 2.5V
High time when VCCO 1.8V setup time (guarantees proper when VCCO 3.3V 2.5V
TSCE
setup time (guarantees proper counting) when VCCO 1.8V hold time (guarantees counters reset)(5) when VCCO 3.3V 2.5V hold time (guarantees counters reset)(5) when VCCO 1.8V OE/RESET hold time (guarantees counters reset)(6) when VCCO 3.3V 2.5V OE/RESET hold time (guarantees counters reset)(6) when VCCO 1.8V BUSY setup time when VCCO 3.3V 2.5V(8) BUSY setup time when VCCO 1.8V(8)
THCE
THOE
BUSY hold time when VCCO 3.3V 2.5V(8) BUSY hold time when VCCO 1.8V(8)
TSXT
EN_EXT_SEL setup time OE/RESET when VCCO 3.3V 2.5V(8) EN_EXT_SEL setup time OE/RESET when VCCO 1.8V(8) EN_EXT_SEL hold time from OE/RESET when VCCO 3.3V 2.5V(8) EN_EXT_SEL hold time from OE/RESET when VCCO 1.8V(8) REV_SEL setup time OE/RESET when VCCO 3.3V 2.5V(8) REV_SEL setup time OE/RESET when VCCO 1.8V(8)
THXT
TSRV
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Platform Flash In-System Programmable Configuration PROMS
Symbol
Description
XCF01S, XCF02S, XCF04S
XCF08P, XCF16P, XCF32P
Units
THRV
REV_SEL hold time from OE/RESET when VCCO 3.3V 2.5V(8) REV_SEL hold time from OE/RESET when VCCO 1.8V(8)
Notes:
test load XCF01S/XCF02S/XCF04S; XCF08P/XCF16P/XCF32P. Float delays measured with loads. Transition measured ±200 from steady-state active levels. parameters measured with 0.0V 3.0V. THCE High THOE This minimum possible TCYC. Actual TCYC TCAC FPGA Data setup time. Example: With XCF32P serial mode with VCCO 3.3V, FPGA data setup time then actual TCYC Guaranteed design; tested. EN_EXT_SEL, REV_SEL[1:0], BUSY inputs XCFxxP PROM only. When JTAG CONFIG command issued, PROM will drive least THCF minimum.
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Platform Flash In-System Programmable Configuration PROMS
XCFxxP PROM Configuration Master with Input Clock Source
THCE THOE TCYCO
OE/RESET
TCLKO
CLKOUT
TCECC TOECC CCDD TCOH TDDC TCECF TOECF
BUSY (optional) DATA
TCFCC THCF
TEOH
EN_EXT_SEL
TSXT
THXT
TSXT
THXT
REV_SEL[1:0]
TSRV
THRV
TSRV
THRV
Note: CLKOUT cycles output after rising edge, before CLKOUT tristates, OE/RESET remains high, terminal count been reached.
ds123_25_122905
Symbol
Description
hold time guarantee design revision selection sampled when VCCO 3.3V 2.5V(11) hold time guarantee design revision selection sampled when VCCO 1.8V(11) data delay when VCCO 3.3V 2.5V data delay when VCCO 1.8V OE/RESET data OE/RESET data data data delay delay delay delay when VCCO 3.3V 2.5V when VCCO 1.8V
XCF08P, XCF16P, XCF32P
Units
THCF
TEOH TOECF TCECF
when VCCO 3.3V 2.5V when VCCO 1.8V
Data hold from OE/RESET, when VCCO 3.3V 2.5V Data hold from OE/RESET, when VCCO 1.8V OE/RESET data float OE/RESET data float OE/RESET CLKOUT float OE/RESET CLKOUT float CLKOUT float CLKOUT float delay(2) delay(2) delay delay when VCCO 3.3V 2.5V when VCCO 1.8V
delay(2) delay(2)
when VCCO 3.3V 2.5V when VCCO 1.8V
when VCCO 3.3V 2.5V when VCCO 1.8V
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Platform Flash In-System Programmable Configuration PROMS
Symbol
Clock TCYCO Clock Clock Clock THCE THOE period period period period
Description
(serial mode) when VCCO 3.3V 2.5V (serial mode) when VCCO 1.8V (parallel mode) when VCCO 3.3V 2.5V (parallel mode) when VCCO 1.8V when VCCO 3.3V 2.5V when VCCO 1.8V when VCCO 3.3V 2.5V when VCCO 1.8V reset)(5) reset)(5) when VCCO 3.3V 2.5V when VCCO 1.8V reset)(6) reset)(6) when VCCO 3.3V 2.5V when VCCO 1.8V
XCF08P, XCF16P, XCF32P
2000 2000 2000 2000
Units
cycles cycles cycles cycles
High High
time(3) time(3) time(3) time(3)
hold time (guarantees counters hold time (guarantees counters
OE/RESET hold time (guarantees counters OE/RESET hold time (guarantees counters
BUSY setup time CLKOUT when VCCO 3.3V 2.5V BUSY setup time CLKOUT when VCCO 1.8V BUSY hold time CLKOUT when VCCO 3.3V 2.5V BUSY hold time CLKOUT when VCCO 1.8V input CLKOUT output delay when VCCO 3.3V 2.5V input CLKOUT output delay when VCCO 1.8V input CLKOUT output delay when VCCO 3.3V 2.5V with decompression (12) input CLKOUT output delay when VCCO 1.8V with decompression (12) CLKOUT delay(8) when VCCO 3.3V 2.5V
TCLKO
TCECC
CLKOUT delay when VCCO 1.8V OE/RESET CLKOUT delay(8) when VCCO 3.3V 2.5V
TOECC OE/RESET CLKOUT delay(8) when VCCO 1.8V TCFCC TCCDD TDDC CLKOUT delay(8) when VCCO 3.3V 2.5V CLKOUT delay(8) when VCCO 1.8V 2.5V(9) decompression (9)(12) 1.8V(9) decompression (9)(12) CLKOUT data delay when VCCO 3.3V CLKOUT data delay when VCCO
decompression (12)
Data setup time CLKOUT when VCCO 3.3V 2.5V with Data setup time CLKOUT when VCCO 1.8V with Data hold from CLKOUT when VCCO 3.3V 2.5V Data hold from CLKOUT when VCCO 1.8V Data hold from CLKOUT when VCCO 3.3V 2.5V with Data hold from CLKOUT when VCCO 1.8V with
TCOH
decompression (12)
TSXT
EN_EXT_SEL setup time OE/RESET when VCCO 3.3V 2.5V EN_EXT_SEL setup time OE/RESET when VCCO 1.8V
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Platform Flash In-System Programmable Configuration PROMS
Symbol
Description
EN_EXT_SEL hold time from OE/RESET when VCCO 3.3V 2.5V EN_EXT_SEL hold time from OE/RESET when VCCO 1.8V REV_SEL setup time OE/RESET when VCCO 3.3V 2.5V REV_SEL setup time OE/RESET when VCCO 1.8V REV_SEL hold time from OE/RESET when VCCO 3.3V 2.5V REV_SEL hold time from OE/RESET when VCCO 1.8V
XCF08P, XCF16P, XCF32P
Units
THXT TSRV THRV Notes:
test load XCF01S/XCF02S/XCF04S; XCF08P/XCF16P/XCF32P. Float delays measured with loads.Transition measured ±200 from steady-state active levels. Guaranteed design, tested. parameters measured with 0.0V 3.0V. THCE High THOE This minimum possible TCYCO. Actual TCYCO TCCDD FPGA Data setup time. Example: With XCF32P serial mode with VCCO 3.3V, FPGA Data setup time then actual TCYCO delay before enabled CLKOUT signal begins clocking data device dependent clocking configuration. delay before CLKOUT enabled will increase decompression enabled. Slower frequency option required meet FPGA data sheet setup time. When decompression enabled, CLKOUT signal becomes controlled clock output. When decompressed data available, CLKOUT will toggle source clock frequency (either selected internal clock frequency external input frequency). When decompressed data available, CLKOUT parked High. CLKOUT used, then must pulled High externally using 4.7k pull-up VCCO. When JTAG CONFIG command issued, PROM will drive least THCF minimum.
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Platform Flash In-System Programmable Configuration PROMS
XCFxxP PROM Configuration Master with Internal Oscillator Clock Source
THCE THOE
OE/RESET
CLKOUT
TCEC TOEC TCDD TCOH TDDC TCECF TOECF
BUSY (optional) DATA
TCFC THCF
TEOH
EN_EXT_SEL
TSXT
THXT
TSXT
THXT
REV_SEL[1:0]
TSRV
THRV
TSRV
THRV
Note: CLKOUT cycles output after rising edge, before CLKOUT tristates, OE/RESET remains high, terminal count been reached.
ds123_26_122905
Symbol
Description
hold time guarantee design revision selection sampled when VCCO 3.3V 2.5V(12) hold time guarantee design revision selection sampled when VCCO 1.8V(12) data delay when VCCO 3.3V 2.5V data delay when VCCO 1.8V OE/RESET data OE/RESET data data data delay(5) delay(5) delay(6) delay(6) when VCCO 3.3V 2.5V when VCCO 1.8V
XCF08P, XCF16P, XCF32P
Units
THCF
TEOH TOECF TCECF THCE
when VCCO 3.3V 2.5V when VCCO 1.8V
Data hold from OE/RESET, when VCCO 3.3V 2.5V Data hold from OE/RESET, when VCCO 1.8V OE/RESET data float OE/RESET data float OE/RESET CLKOUT float OE/RESET CLKOUT float CLKOUT float CLKOUT float delay(2) delay(2) delay delay when VCCO 3.3V 2.5V when VCCO 1.8V
delay(2) delay(2)
when VCCO 3.3V 2.5V when VCCO 1.8V
when VCCO 3.3V 2.5V when VCCO 1.8V reset) reset) when VCCO 3.3V 2.5V when VCCO 1.8V
hold time (guarantees counters hold time (guarantees counters
2000 2000
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Platform Flash In-System Programmable Configuration PROMS
Symbol
Description
OE/RESET hold time (guarantees counters OE/RESET hold time (guarantees counters reset) reset) when VCCO 3.3V 2.5V when VCCO 1.8V
XCF08P, XCF16P, XCF32P
Units
THOE TCEC TOEC TCFC TCDD
2000 2000
BUSY setup time CLKOUT when VCCO 3.3V 2.5V BUSY setup time CLKOUT when VCCO 1.8V BUSY hold time CLKOUT when VCCO 3.3V 2.5V BUSY hold time CLKOUT when VCCO 1.8V CLKOUT CLKOUT delay(7) when VCCO 3.3V 2.5V VCCO 1.8V when VCCO 3.3V 2.5V when VCCO 1.8V delay(7) delay(7) delay when
OE/RESET CLKOUT OE/RESET CLKOUT CLKOUT CLKOUT
delay(7) when delay(7) when
VCCO 3.3V 2.5V VCCO 1.8V 2.5V(8) 1.8V(8)
CLKOUT data delay when VCCO 3.3V CLKOUT data delay when VCCO
decompression(11)
TDDC
Data setup time CLKOUT when VCCO 3.3V 2.5V with decompression (8)(11) Data setup time CLKOUT when VCCO 1.8V with decompression(8)(11) Data hold from CLKOUT when VCCO 3.3V 2.5V Data hold from CLKOUT when VCCO 1.8V Data hold from CLKOUT when VCCO 3.3V 2.5V with Data hold from CLKOUT when VCCO 1.8V with decompression(11)
TCOH
TSXT THXT TSRV THRV
EN_EXT_SEL setup time OE/RESET when VCCO 3.3V 2.5V EN_EXT_SEL setup time OE/RESET when VCCO 1.8V EN_EXT_SEL hold time from OE/RESET when VCCO 3.3V 2.5V EN_EXT_SEL hold time from OE/RESET when VCCO 1.8V REV_SEL setup time OE/RESET when VCCO 3.3V 2.5V REV_SEL setup time OE/RESET when VCCO 1.8V REV_SEL hold time from OE/RESET when VCCO 3.3V 2.5V REV_SEL hold time from OE/RESET when VCCO 1.8V CLKOUT default (fast) frequency(9) decompression(11) CLKOUT default (fast) frequency with
12.5
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Platform Flash In-System Programmable Configuration PROMS
Symbol
CLKOUT alternate (slower)
Description
frequency(10) decompression(11)
XCF08P, XCF16P, XCF32P
12.5
Units
Notes:
12.5
CLKOUT alternate (slower) frequency with
test load XCF01S/XCF02S/XCF04S; XCF08P/XCF16P/XCF32P. Float delays measured with loads. Transition measured ±200 from steady-state active levels. Guaranteed design, tested. parameters measured with 0.0V 3.0V. THCE High THOE delay before enabled CLKOUT signal begins clocking data device dependent clocking configuration. delay before CLKOUT enabled will increase decompression enabled. Slower frequency option required meet FPGA data sheet setup time. Typical CLKOUT default (fast) period MHz) Typical CLKOUT alternate (slower) period MHz) When decompression enabled, CLKOUT signal becomes controlled clock output. When decompressed data available, CLKOUT will toggle source clock frequency (either selected internal clock frequency external input frequency). When decompressed data available, CLKOUT parked High. CLKOUT used, then must pulled High externally using 4.7k pull-up VCCO. When JTAG CONFIG command issued, PROM will drive least THCF minimum.
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Platform Flash In-System Programmable Configuration PROMS
Characteristics Over Operating Conditions When Cascading
OE/RESET
CLKOUT (optional) DATA Last
TCDF TCODF TOCE TOOE
First
TOCK TCOCE
ds123_23_102203
Symbol
Description
output float delay (2,3) when VCCO 2.5V 3.3V output float delay (2,3) when VCCO 1.8V delay (3,5) delay (3,5) when VCCO 2.5V 3.3V when VCCO 1.8V
XCF01S, XCF02S, XCF04S
XCF08P, XCF16P, XCF32P
Units
TCDF
TOCK TOCE TOOE TCOCE
delay (3,6)
when VCCO 2.5V 3.3V
delay (3,6) when VCCO 1.8V OE/RESET delay when VCCO 2.5V 3.3V OE/RESET delay when VCCO 1.8V CLKOUT delay when VCCO 2.5V 3.3V CLKOUT delay when VCCO 1.8V CLKOUT output float delay when VCCO 2.5V 3.3V CLKOUT output float delay when VCCO 1.8V
TCODF
Notes: test load XCF01S/XCF02S/XCF04S; XCF08P/XCF16P/XCF32P. Float delays measured with loads. Transition measured ±200 from steady state active levels. Guaranteed design, tested. parameters measured with 0.0V 3.0V. cascaded PROMs, FPGA's dual-purpose configuration data pins persist configuration pins, minimum period increased based data propagation delays: TCYC minimum TOCK FPGA Data setup time. TCAC maximum TOCK cascaded PROMs, FPGA's dual-purpose configuration data pins become general pins after configuration; allow disable propagate cascaded PROMs avoid contention data lines following configuration, minimum period increased based data propagation delays: TCYC minimum TOCE TCAC maximum TOCK
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Platform Flash In-System Programmable Configuration PROMS
Pinouts Descriptions
XCFxxS Platform Flash PROM available VO20 VOG20 packages. XCFxxP Platform Flash PROM available VO48, VOG48, FS48, FSG48 packages. Notes:
VO20/VOG20 denotes 20-pin (TSSOP) Plastic Thin Shrink Small Outline Package VO48/VOG48 denotes 48-pin (TSOP) Plastic Thin Small Outline Package. FS48/FSG48 denotes 48-pin (TFBGA) Plastic Thin Fine Pitch Ball Grid Array (0.8 pitch).
XCFxxS Pinouts Descriptions
XCFxxS VO20/VOG20 Names Descriptions
Table provides list names descriptions XCFxxS 20-pin VO20/VOG20 package. Table XCFxxS Names Descriptions
Name
Boundary Scan Order
Boundary Scan Function
Data Output Enable Data Data Data Output Enable Data Data Output Enable Data Output Enable
Description
DATA output provide data configuring FPGA serial mode. output high-impedance state during ISPEN (when clamped). Configuration Clock Input. Each rising edge input increments internal address counter input selected, Low, OE/RESET High. Output Enable/Reset (Open-Drain I/O). When Low, this input holds address counter reset DATA output high-impedance state. This bidirectional open-drain that held while PROM completes internal power-on reset sequence. Polarity programmable. Chip Enable Input. When High, device into low-power standby mode, address counter reset, DATA pins high-impedance state. Configuration Pulse (Open-Drain Output). Allows JTAG CONFIG instruction initiate FPGA configuration without powering down FPGA. This open-drain output that pulsed JTAG CONFIG command. Chip Enable Output. Chip Enable Output (CEO) connected input next PROM chain. This output when OE/RESET input High, internal address counter been incremented beyond Terminal Count (TC) value. returns High when OE/RESET goes goes High. JTAG Mode Select Input. state rising edge determines state transitions Test Access Port (TAP) controller. internal resistive pull-up VCCJ provide logic device driven. JTAG Clock Input. This JTAG test clock. sequences controller JTAG test programming electronics. JTAG Serial Data Input. This serial input JTAG instruction data registers. internal resistive pull-up VCCJ provide logic device driven. JTAG Serial Data Output. This serial output JTAG instruction data registers. internal resistive pull-up VCCJ provide logic system driven. +3.3V Supply. Positive 3.3V supply voltage internal logic.
20-pin TSSOP (VO20/VOG20)
OE/RESET
Mode Select
Clock
Data
VCCINT
Data
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Platform Flash In-System Programmable Configuration PROMS
Table XCFxxS Names Descriptions
Name
VCCO
Boundary Scan Order
Boundary Scan Function
Description
+3.3V, 2.5V, 1.8V Supply. Positive 3.3V, 2.5V, 1.8V supply voltage connected output voltage drivers input buffers. +3.3V 2.5V JTAG Supply. Positive 3.3V, 2.5V, 1.8V supply voltage connected output voltage driver TCK, TMS, input buffers. Ground connect. (These pins must left unconnected.)
20-pin TSSOP (VO20/VOG20)
VCCJ
XCFxxS VO20/VOG20 Pinout Diagram
(DNC) OE/RESET (DNC) VCCJ VCCO VCCINT (DNC) (DNC) (DNC) (DNC)
ds123_02_071304
VO20/VOG20 View
Figure VO20/VOG20 Pinout Diagram (Top View) with Names
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Platform Flash In-System Programmable Configuration PROMS
XCFxxP Pinouts Descriptions
VXCFxxP O48/VOG48 FS48/FSG48 Names Descriptions
Table provides list names descriptions XCFxxP 48-pin VO48/VOG48 48-pin FS48/FSG48 packages. Table XCFxxP Names Descriptions (VO48/VOG48 FS48/FSG48)
Name Boundary Scan Order
Boundary Scan Function
Data Output Enable Data Output Enable Data
Description
48-pin TSOP (VO48/ VOG48)
48-pin TFBGA (FS48/ FSG48)
DATA output provide data configuring Output Enable FPGA serial mode. D0-D7 DATA output pins provide parallel data Data configuring Xilinx FPGA SelectMap (parallel) mode. Output Enable output high-impedance state during ISPEN (when clamped). Data D1-D7 outputs high-impedance state during Output Enable ISPEN (when clamped) when serial mode selected configuration. D1-D7 pins left unconnected Data when PROM used serial mode. Output Enable Data Output Enable Data Output Enable Data Configuration Clock Input. internal programmable control selects between internal oscillator input clock source control configuration sequence. Each rising edge input increments internal address counter input selected, Low, OE/RESET High, BUSY (parallel mode only), High.
OE/RESET
Output Enable/Reset (Open-Drain I/O). When Low, this input holds address counter reset Data DATA CLKOUT outputs placed high-impedance Output Enable state. This bidirectional open-drain that held while PROM completes internal power-on reset sequence. Polarity programmable. Data Chip Enable Input. When High, device into low-power standby mode, address counter reset, DATA CLKOUT outputs placed high-impedance state.
Data
Configuration Pulse (Open-Drain I/O). output, this allows JTAG CONFIG instruction initiate FPGA configuration without powering down FPGA. This open-drain signal that pulsed JTAG CONFIG Data command. input, rising edge current design revision selection sampled internal address Output Enable counter reset start address selected revision. unused, must pulled High using external pull-up VCCO.
Data
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Platform Flash In-System Programmable Configuration PROMS
Table XCFxxP Names Descriptions (VO48/VOG48 FS48/FSG48) (Continued)
Name Boundary Scan Order
Boundary Scan Function
Data
Description
48-pin TSOP (VO48/ VOG48)
48-pin TFBGA (FS48/ FSG48)
Chip Enable Output. Chip Enable Output (CEO) connected input next PROM chain. This output Output Enable when OE/RESET input High, internal address counter been incremented beyond Terminal Count (TC) value. returns High when OE/RESET goes goes High. Data Enable External Selection Input. When this Low, design revision selection controlled Revision Select pins. When this High, design revision selection controlled internal programmable Revision Select control bits. EN_EXT_SEL internal resistive pull-up VCCO provide logic device driven. Revision Select[1:0] Inputs. When EN_EXT_SEL Low, Revision Select pins used select design revision enabled, overriding internal programmable Revision Select control bits. Revision Select[1:0] inputs have internal resistive pull-up VCCO provide logic device pins driven. Busy Input. BUSY input enabled when parallel mode selected configuration. When BUSY High, internal address counter stops incrementing current data remains data pins. first rising edge after BUSY transitions from High Low, data next address driven data pins. When serial mode decompression enabled during device programming, BUSY input disabled. BUSY internal resistive pull-down provide logic device driven.
EN_EXT_SEL
REV_SEL0 REV_SEL1
Data Data
Data
BUSY
CLKOUT
Configuration Clock Output. internal Programmable control enables CLKOUT signal, which sourced from Output Enable either internal oscillator input pin. Each rising edge selected clock source increments internal address counter data available, Low, OE/RESET High. Output data available rising edge CLKOUT. CLKOUT disabled High OE/RESET Low. decompression enabled, CLKOUT parked High when decompressed data ready. When CLKOUT disabled, CLKOUT into high-Z state. CLKOUT used, then must pulled High externally using pull-up VCCO. Mode Select JTAG Mode Select Input. state rising edge determines state transitions Test Access Port (TAP) controller. internal resistive pull-up VCCJ provide logic device driven. JTAG Clock Input. This JTAG test clock. sequences controller JTAG test programming electronics. JTAG Serial Data Input. This serial input JTAG instruction data registers. internal resistive pull-up VCCJ provide logic device driven. JTAG Serial Data Output. This serial output JTAG instruction data registers. internal resistive pull-up VCCJ provide logic system driven. +1.8V Supply. Positive 1.8V supply voltage internal logic.
Data
Clock Data Data
VCCINT
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Platform Flash In-System Programmable Configuration PROMS
Table XCFxxP Names Descriptions (VO48/VOG48 FS48/FSG48) (Continued)
Name Boundary Scan Order Boundary Scan Function Description
+3.3V, 2.5V, 1.8V Supply. Positive 3.3V, 2.5V, 1.8V supply voltage connected output voltage drivers input buffers. +3.3V 2.5V JTAG Supply. Positive 3.3V, 2.5V, 1.8V supply voltage connected output voltage driver TCK, TMS, input buffers. Ground
48-pin TSOP (VO48/ VOG48)
48-pin TFBGA (FS48/ FSG48)
VCCO
VCCJ
Connect. (These pins must left unconnected.)
XCFxxP VO48/VOG48 Pinout Diagram
VCCINT BUSY VCCO CLKOUT OE/RESET VCCINT VCCJ VCCO VCCO VCCINT VCCO REV_SEL1 REV_SEL0 EN_EXT_SEL
VO48/VOG48 View
ds123_24_070505
Figure VO48/VOG48 Pinout Diagram (Top View) with Names
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Platform Flash In-System Programmable Configuration PROMS
XCFxxP FS48/FSG48 Names
Table XCFxxP Names (FS48/FSG48)
Number
XCFxxP FS48/FSG48 Pinout Diagram
Name
OE/RESET VCCINT VCCO BUSY CLKOUT VCCO VCCO
Number
Name
VCCINT
FS48/FSG48 View
ds121_01_071604
REV_SEL0 REV_SEL1 VCCO VCCINT VCCJ EN_EXT_SEL
Figure FS48/FSG48 Pinout Diagram (Top View)
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Platform Flash In-System Programmable Configuration PROMS
Ordering Information
XCF04S VO20
Device Number XCF01S XCF02S XCF04S Package Type VO20 20-pin TSSOP Package VOG20 20-pin TSSOP Package, Pb-free Operating Range/Processing -40°C +85°C)
XCF32P FS48
Device Number XCF08P XCF16P XCF32P Package Type VO48 48-pin TSOP Package VOG48 48-pin TSOP Package, Pb-free FS48 48-pin TFBGA Package FSG48 48-pin TFBGA Package, Pb-free Operating Range/Processing -40°C +85°C)
Valid Ordering Combinations
XCF01SVO20 XCF02SVO20 XCF04SVO20 XCF08PVO48 XCF16PVO48 XCF32PVO48 XCF08PFS48 XCF16PFS48 XCF32PFS48 XCF01SVOG20 XCF02SVOG20 XCF04SVOG20 XCF08PVOG48 XCF16PVOG48 XCF32PVOG48 XCF08PFSG48 XCF16PFSG48 XCF32PFSG48
Marking Information
XCF04S-V
Device Number XCF01S XCF02S XCF04S XCF08P XCF16P XCF32P Package Type 20-pin TSSOP Package (VO20) 20-pin TSSOP Package, Pb-free (VOG20) VO48 48-pin TSOP Package (VO48) VOG48 48-pin TSOP Package, Pb-free (VOG48) 48-pin TFBGA Package (FS48) FG48 48-pin TFBGA Package, Pb-free (FSG48) Operating Range/Processing -40°C +85°C)
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Revision History
following table shows revision history this document.
Date
04/29/03 06/03/03 11/05/03 11/18/03
Version
Xilinx Initial Release. Made edits pages. Major revision.
Revision
Pinout corrections follows: Table VO48 package, removed from VCCINT added VCCO. FS48 package, removed from VCCINT added VCCO. Table (FS48 package): changed name from VCCINT VCCO. changed name from DNC. Figure (VO48 package): changed name from VCCINT VCCO. Added specification (4.7k) recommended pull-up resistor OE/RESET section "Reset Power-On Reset Activation," page Added paragraph section "Standby Mode," page concerning pull-up resistor and/or buffer DONE pin. Section "Features," page Added package styles configuration speed limit itemized features. Section "Description," page following: Added state conditions BUSY descriptive text. Table page Updated Virtex-II configuration bitstream sizes. Section "Design Revisioning," page Rewritten. Section "PROM FPGA Configuration Mode Connections Summary," page following, five instances: Added instruction High tied FPGA's PROG_B (PROGRAM) input. Figure page through Figure page Added footnote indicating directionality each configuration. Section "I/O Input Voltage Tolerance Power Sequencing," page Rewritten. Table page Added column truth table, added additional document state Section "Absolute Maximum Ratings," page Revised devices. Section "Supply Voltage Requirements Power-On Reset Power-Down," page Revised footnote callout number TOER from Footnote Footnote (3). Added Footnote callout TVCC. Section "Recommended Operating Conditions," page Added Typical (Typ) parameter columns parameters VCCINT VCCO/VCCJ. Added 1.5V operation parameter VIH, devices. Revised Min, 2.5V operation, from 2.0V 1.7V. Added parameter parameters (Continued next page) Section Characteristics Over Operating Conditions," page Added parameter parameters parallel configuration mode, devices, ICCO Added Footnote Footnote with callouts Test Conditions column ICCJ, ICCINTS, ICCOS, ICCJS, define active standby mode requirements. Section Characteristics Over Operating Conditions," page Corrected description second TCAC parameter line show parameters 1.8V VCCO Revised Footnote indicate VCCO 3.3V. Applied Footnote second TCYC parameter line. Section Characteristics Over Operating Conditions When Cascading," page Revised Footnote (5)TCYC TCAC formulas. Table page Added additional state conditions description. Added function resetting internal address counter description.
12/15/03
05/07/04
05/07/04 (cont'd)
(cont'd)
DS123 (v2.9) 2006
www.xilinx.com
Platform Flash In-System Programmable Configuration PROMS
07/20/04
Added Pb-free package options VOG20, FSG48, VOG48. Figure page Figure page Corrected connection name FPGA DOUT (OPTIONAL Daisy-chained Slave FPGAs with different configurations) from DOUT DIN. Section "Absolute Maximum Ratings," page Removed parameter TSOL from table. (TSOL information found Package User Guide.) Table page Removed reference XC2VP125 FPGA. Table page Broke VCCO VCCJ into separate columns. Table page Added clarification code revision bits. Table page Deleted TCKMIN2 (bypass mode) renamed TCKMIN1 TCKMIN. Table "Recommended Operating Conditions," page Separated VCCO VCCJ parameters. Table Characteristics Over Operating Conditions," page Added most parameter values XCF08P, XCF16P, XCF32P devices. Added Footnote ICCO specifying no-load conditions. Table Characteristics Over Operating Conditions," page Added most parameter values XCF08P, XCF16P, XCF32P devices. Expanded Footnote include XCF08P, XCF16P, XCF32P devices. Added Footnote through (11) relating CLKOUT conditions various parameters. Added rows TCYC specifying parameters parallel mode. Added rows specifying parameters with decompression TCLKO, TCOH, TFF, TSF. Added TDDC (setup time with decompression). Table Characteristics Over Operating Conditions When Cascading," page Added most parameter values XCF08P, XCF16P, XCF32P devices. Separated Footnote into Footnotes specify different derivations TCYC, depending whether dual-purpose configuration pins persist configuration pins, become general pins after configuration.
10/18/04
03/14/05
Added Virtex-4 LX/FX/SX configuration data Table Corrected Virtex-II configuration data Table Corrected Virtex-II configuration data Table Added Spartan-3L configuration data Table Added Spartan-3E configuration data Table Paragraph added FPGA Master SelectMAP (Parallel) Mode (1), Page Changes Characteristics TOER changed, Page changed VOL, Page VCCO added test conditions IIL, IILP, IIHP,and IIH, Page Values modified IILP IIHP. Changes Characteristics modified 1.8V, Page rows added TCEC TOEC, Page Minor changes grammar punctuation. Added explanation "Preliminary" Electrical Characteristics.
07/11/05
Move from "Preliminary" "Product Specification" Corrections Virtex-4 configuration bitstream values Minor changes Figure page Figure page Figure page Figure page Change "Internal Oscillator," page description Change "CLKOUT," page description
DS123 (v2.9) 2006
www.xilinx.com
Platform Flash In-System Programmable Configuration PROMS
12/29/05
Update first paragraph "IEEE 1149.1 Boundary-Scan (JTAG)," page Added JTAG cautionary note Page Corrected logic values Erase/Program (ER/PROG) Status field, IR[4], listed under "XCFxxP Instruction Register bits wide)," page Sections "XCFxxS XCFxxP PROM Configuration Slave with Input Clock Source," page "XCFxxP PROM Configuration Master with Input Clock Source," page "XCFxxP PROM Configuration Master with Internal Oscillator Clock Source," page added Characteristics Over Operating Conditions," page Notes Figure page Figure page Figure page Figure page Figure page Figure page Figure page Figure page updated specify need pull-up resistor connected PROGB. Enhanced description under section "CLKOUT," page Enhanced description design revision sampling under section "Design Revisioning," page Figure Figure renamed Table page Table page respectively. tables, figures, table figure references renumber this point forward. Value "ICCINT," page updated from XCFxxP. Block diagram Figure page updated show clock source muxing route clocking functional blocks. Added Virtex-5 support Table page "VIL" maximum 2.5V operation "Recommended Operating Conditions," page updated match LVCMOS25 standard.
05/09/06
DS123 (v2.9) 2006
www.xilinx.com
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