16-Kb CMOS Serial EEPROM, Cascadable DEVICE DESCRIPTION CAT24C164

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16-Kb CMOS Serial EEPROM, Cascadable DEVICE DESCRIPTION CAT24C164

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CAT24C164
16-Kb CMOS Serial EEPROM, Cascadable DEVICE DESCRIPTION
CAT24C164 16-Kb CMOS cascadable Serial EEPROM device organized internally pages bytes each, total 2048x8 bits. device supports both Standard (100 kHz) well Fast (400 kHz) protocol. Data written providing starting address, then loading contiguous bytes into Page Write Buffer, then writing data non-volatile memory internal write cycle. Data read providing starting address then shifting data serially while automatically incrementing internal address count. External address pins make possible address eight CAT24C164 devices same bus.
Supports Standard Fast Protocol Supply Voltage Range 16-Byte Page Write Buffer Hardware Write Protection entire memory Schmitt Triggers Noise Suppression Filters
Inputs (SCL SDA).
power CMOS technology 1,000,000 program/erase cycles year data retention Industrial temperature range RoHS-compliant 8-lead PDIP, SOIC, TSSOP
8-pad TDFN packages.
Ordering Information details, page
CONFIGURATION
PDIP SOIC TSSOP TDFN (VP2)
FUNCTIONAL SYMBOL
CAT24C164
location please consult corresponding package drawing.
FUNCTIONS
Device Address Inputs Serial Data Input/Output Serial Clock Input Write Protect Input Power Supply Ground
Catalyst carries protocol under license from Philips Corporation.
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
Doc. 1118, Rev.
CAT24C164
ABSOLUTE MAXIMUM RATINGS(1) Storage Temperature Voltage with Respect Ground(2) RELIABILITY CHARACTERISTICS(3) Symbol NEND(4) Parameter Endurance Data Retention 1,000,000 Units Program/ Erase Cycles Years -65°C +150°C -0.5 +6.5
D.C. OPERATING CHARACTERISTICS -40°C 85°C, unless otherwise specified. Symbol ICCR ICCW VOL1 VOL2 Parameter Read Current Write Current Standby Current Leakage Input Voltage Input High Voltage Output Voltage Output Voltage Test Conditions Read, fSCL Write, fSCL Pins -0.5 Units
IMPEDANCE CHARACTERISTICS -40°C 85°C, unless otherwise specified. Symbol CIN(3) CIN(3) IWP(5) Parameter Capacitance Input Capacitance (other pins) Input Current Conditions VIH, VIH, VIH,
Note: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions outside those listed operational sections this specification implied. Exposure absolute maximum rating extended periods affect device performance reliability. input voltage should lower than -0.5 higher than During transitions, voltage undershoot less than -1.5 overshoot more than periods less than These parameters tested initially after design process change that affects parameter according appropriate AEC-Q100 JEDEC test methods. Page Mode, 25°C When driven, pulled down internally. improved noise immunity, internal pull-down relatively strong; therefore external driver must able supply pull-down current when attempting drive input HIGH. conserve power, input level exceeds trip point CMOS input buffer VCC), strong pull-down reverts weak current source.
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
Units
Doc. 1118, Rev.
CAT24C164
A.C. CHARACTERISTICS(1) -40°C 85°C. Standard Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tF(2) tSU:STO tBUF Ti(2) tSU:WP tHD:WP tPU(2,
Note: Test conditions according "A.C. Test Conditions" table. Tested initially after design process change that affects this parameter. delay between time stable device ready accept commands.
Fast Units
Parameter Clock Frequency START Condition Hold Time Period Clock High Period Clock START Condition Setup Time Data Hold Time Data Setup Time Rise Time Fall Time STOP Condition Setup Time Free Time Between STOP START Data Valid Data Hold Time Noise Pulse Filtered Inputs Setup Time Hold Time Write Cycle Time Power-up Ready Mode
1000
A.C. TEST CONDITIONS Input Levels Input Rise Fall Times Input Reference Levels Output Reference Levels Output Load
VCC, Current Source: (VCC (VCC
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
1118, Rev.
CAT24C164
POWER-ON RESET (POR)
CAT24C164 incorporates Power-On Reset (POR) circuitry which protects internal logic against powering wrong state. CAT24C164 device will power into Standby mode after exceeds trigger level will power down into Reset mode when drops below trigger level. This bi-directional feature protects device against `brown-out' failure following temporary loss power.
PROTOCOL
consists `wires', SDA. wires connected supply pull-up resistors. Master Slave devices connect 2wire their respective pins. transmitting device pulls down line `transmit' releases `transmit' `1'. Data transfer initiated only when busy (see A.C. Characteristics). During data transfer, line must remain stable while line HIGH. transition while HIGH will interpreted START STOP condition (Figure START condition precedes commands. consists HIGH transition while HIGH. START acts `wake-up' call receivers. Absent START, Slave will respond commands. STOP condition completes commands. consists HIGH transition while HIGH. Device Addressing Master begins transmission sending START condition. Master then sends address particular Slave device requesting. most significant 8-bit slave address fixed (see Figure next three significant bits (A2, device address bits define which device which part device Master accessing (The must compliment input signal). eight CAT24C164 devices individually addressed system. next three bits used three most significant bits data word address. last slave address specifies whether Read Write operation performed. When this Read operation selected, when Write operation selected. Acknowledge After processing Slave address, Slave responds with acknowledge (ACK) pulling down line during clock cycle (Figure Slave will also acknowledge address byte every data byte presented Write mode. Read mode Slave shifts data byte, then releases line during clock cycle. long Master acknowledges data, Slave will continue transmitting. Master terminates session acknowledging last data byte (NoACK) issuing STOP condition. timing illustrated Figure
DESCRIPTION
SCL: Serial Clock input accepts Serial Clock generated Master. SDA: Serial Data receives input data transmits data stored EEPROM. transmit mode, this open drain. Data acquired positive edge, delivered negative edge SCL. Address inputs device address when cascading multiple devices. When driven, these pins pulled internally. CAT24C164 made compatible with CAT24C16 tying leaving float. Write Protect input inhibits write operations, when pulled HIGH. When driven, this pulled internally.
FUNCTIONAL DESCRIPTION
CAT24C164 supports Inter-Integrated Circuit (I2C) data transmission protocol, which defines device that sends data transmitter device receiving data receiver. Data flow controlled Master device, which generates serial clock START STOP conditions. CAT24C164 acts Slave device. Master Slave alternate either transmitter receiver.
Doc. 1118, Rev.
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C164
Figure START/STOP Conditions
START CONDITION STOP CONDITION
Figure Slave Address Bits
CAT24C164
Figure Acknowledge Timing
RELEASE DELAY (TRANSMITTER) FROM MASTER RELEASE DELAY (RECEIVER)
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START DELAY tAA) SETUP tSU:DAT)
Figure Timing
tLOW tSU:STA tHD:STA
tHIGH tLOW
tHD:DAT
tSU:DAT
tSU:STO
tBUF
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1118, Rev.
CAT24C164
WRITE OPERATIONS
Byte Write Byte Write mode, Master sends START condition Slave address with zero Slave. After Slave generates acknowledge, Master sends byte address that written into address pointer CAT24C164. After receiving another acknowledge from Slave, Master transmits data byte written into addressed memory location. CAT24C164 device will acknowledge data byte Master generates STOP condition, which time device begins internal Write cycle nonvolatile memory (Figure While this internal cycle progress (tWR), output will tri-stated CAT24C164 will respond request from Master device (Figure Page Write CAT24C164 writes bytes data single write cycle, using Page Write operation (Figure Page Write operation initiated same manner Byte Write operation, however instead terminating after data byte transmitted, Master allowed send fifteen additional bytes. After each byte been transmitted CAT24C164 will respond with acknowledge internally increments four order address bits. high order bits that define page address remain unchanged. Master transmits more than sixteen bytes prior sending STOP condition, address counter `wraps around' beginning page previously transmitted data will overwritten. Once sixteen bytes received STOP condition been sent Master, internal Write cycle begins. this point received data written CAT24C164 single write cycle. Acknowledge Polling acknowledge (ACK) polling routine used take advantage typical write cycle time. Once stop condition issued indicate host's write operation, CAT24C164 initiates internal write cycle. polling initiated immediately. This involves issuing start condition followed slave address write operation. CAT24C164 still busy with write operation, NoACK will returned. CAT24C164 completed internal write operation, will returned host then proceed with next read write operation. Hardware Write Protection With held HIGH, entire memory protected against Write operations. left floating grounded, impact operation CAT24C164. state strobed last falling edge immediately preceding first data byte (Figure HIGH during strobe interval, CAT24C164 will acknowledge data byte Write request will rejected. Delivery State CAT24C164 shipped erased, i.e., bytes FFh.
Doc. 1118, Rev.
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C164
Figure Byte Write Sequence
ACTIVITY: MASTER SLAVE
SLAVE ADDRESS
ADDRESS BYTE
DATA BYTE
Figure Write Cycle Timing
Byte
STOP CONDITION START CONDITION ADDRESS
Figure Page Write Sequence
ACTIVITY: MASTER SLAVE
SLAVE ADDRESS
ADDRESS BYTE
DATA BYTE
DATA BYTE
DATA BYTE
Figure Timing
ADDRESS BYTE DATA BYTE
tSU:WP
tHD:WP
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
1118, Rev.
CAT24C164
READ OPERATIONS
Immediate Read Upon receiving Slave address with `1', CAT24C164 will interpret this request data residing current byte address memory. CAT24C164 will acknowledge Slave address, will immediately shift data residing current address, will then wait Master respond. Master does acknowledge data (NoACK) then follows with STOP condition (Figure CAT24C164 returns Standby mode. Selective Read Selective Read operations allow Master device select random memory location read operation. Master device first performs `dummy' write operation sending START condition, slave address byte address location wishes read. After CAT24C164 acknowledges byte address, Master device resends START condition slave address, this time with one. CAT24C164 then responds with acknowledge sends requested data byte. Master device does acknowledge data (NoACK) will generate STOP condition (Figure 10). Sequential Read during Read session, Master acknowledges data byte, then CAT24C164 will continue transmitting data residing subsequent locations until Master responds with NoACK, followed STOP (Figure 11). contrast Page Write, during Sequential Read address count will automatically increment then wrap-around memory (rather than page).
Doc. 1118, Rev.
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C164
Figure Immediate Read Sequence Timing
SLAVE ADDRESS
ACTIVITY: MASTER
SLAVE
DATA BYTE
DATA STOP
Figure Selective Read Sequence
ACTIVITY: MASTER
SLAVE ADDRESS
ADDRESS BYTE
SLAVE ADDRESS
SLAVE
DATA BYTE
Figure Sequential Read Sequence
ACTIVITY: MASTER SLAVE ADDRESS
SLAVE
DATA BYTE
DATA BYTE
DATA BYTE
DATA BYTE
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
1118, Rev.
CAT24C164
8-LEAD WIDE PLASTIC
SYMBOL
0.38 3.05 0.36 1.14 9.02 7.62 6.09 7.87 0.115
4.57 3.81 0.56 1.77 10.16 8.25 7.11 9.65 0.150
24C16_8-LEAD_DIP_(300P).eps
0.46
7.87 6.35 2.54 0.130
Notes: dimensions millimeters. Complies with JEDEC Standard MS001. Dimensioning tolerancing ANSI Y14.5M-1982
Doc. 1118, Rev.
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C164
8-LEAD WIDE SOIC
SYMBOL
0.10 1.35 0.33 0.19 4.80 5.80 3.80
0.25 1.75 0.51 0.25 5.00 6.20 4.00
1.27 0.25 0.40 0.50 1.27
24C16_8-LEAD_SOIC.eps
current Tape Reel information, download file from:
Notes: dimensions millimeters. Complies with JEDEC specification MS-012 dimensions.
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
1118, Rev.
CAT24C164
8-LEAD TSSOP
DETAIL
GAGE PLANE
IDENT. 0.25 SEATING PLANE DETAIL
SYMBOL
0.05 0.80 0.19 0.09 2.90 6.30 4.30 0.50 0.00
1.20 0.15 1.05 0.30 0.20 3.10 6.50 4.50 0.75 8.00
0.90
3.00 4.40 0.65 0.60
current Tape Reel information, download file from:
Notes: dimensions millimeters. Complies with JEDEC specification MO-153.
Doc. 1118, Rev.
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C164
8-PAD TDFN PACKAGE (VP2)
INDEX AREA
SYMBOL
0.70 0.00 0.45 0.20 1.90 1.30 2.90 1.20 0.20
0.75 0.02 0.55 0.20 0.25 2.00 1.40 3.00 1.30 0.50 0.30
0.80 0.05 0.65 0.30 2.10 1.50 3.10 1.40 0.40
current Tape Reel information, download file from:
TDFN2X3 (03).eps
Notes: dimensions millimeters. Complies with JEDEC specification MO-229.
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
1118, Rev.
CAT24C164
PACKAGE MARKING
8-Lead PDIP 8-Lead SOIC
24C164LI FYYWWG
24C164WI FYYWWG
Catalyst Semiconductor, Inc. Temperature Range Production Year Production Week Product Revision Lead Finish NiPdAu
Catalyst Semiconductor, Inc. Temperature Range Production Year Production Week Product Revision Lead Finish NiPdAu
8-Lead TSSOP
8-Pad TDFN
YMGF 24164I
Production Year Production Month Revision Temperature Range Lead Finish NiPdAu
Device Code NiPdAu Traceable Code Production Year Production Month
Notes: circle package marking indicates location TDFN package, Product Revision marking included Device Code (XX).
Doc. 1118, Rev.
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C164
EXAMPLE ORDERING INFORMATION
Prefix Device 24C164 Suffix
Company
Product Number 24C164
Temperature Range Industrial (-40°C +85°C)
Tape Reel 3000/Reel
VP2:
Notes:
Package PDIP SOIC, JEDEC TSSOP TDFN
Lead Finish NiPdAu
packages RoHS-compliant (Lead-free, Halogen-free). standard lead finish NiPdAu. device used above example CAT24C164YI-GT3 (TSSOP, Industrial Temperature, NiPdAu, Tape Reel). additional package temperature options, please contact your nearest Catalyst Semiconductor Sales office.
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
1118, Rev.
REVISION HISTORY
Date 08/11/06 Revision Comments Inital Release
Copyrights, Trademarks Patents Trademarks registered trademarks Catalyst Semiconductor include each following: MiniPot
Catalyst Semiconductor been issued U.S. foreign patents patent applications pending that protect products. CATALYST SEMICONDUCTOR MAKES WARRANTY, REPRESENTATION GUARANTEE, EXPRESS IMPLIED, REGARDING SUITABILITY PRODUCTS PARTICULAR PURPOSE, THAT PRODUCTS WILL INFRINGE INTELLECTUAL PROPERTY RIGHTS RIGHTS THIRD PARTIES WITH RESPECT PARTICULAR APPLICATION SPECIFICALLY DISCLAIMS LIABILITY ARISING SUCH APPLICATION, INCLUDING LIMITED CONSEQUENTIAL INCIDENTAL DAMAGES. Catalyst Semiconductor products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Catalyst Semiconductor product could create situation where personal injury death occur. Catalyst Semiconductor reserves right make changes discontinue product service described herein without notice. Products with data sheets labeled "Advance Information" "Preliminary" other products described herein production offered sale. Catalyst Semiconductor advises customers obtain current version relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications complete.
Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Santa Clara, 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com
Publication Revison: Issue date:
1118 08/11/06

16-Kb CMOS Serial EEPROM, Cascadable DEVICE DESCRIPTION CAT24C164

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