128-Kb CMOS Serial EEPROM DEVICE DESCRIPTION CAT24C128 128-Kb Ser

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128-Kb CMOS Serial EEPROM DEVICE DESCRIPTION CAT24C128 128-Kb Ser

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CAT24C128
128-Kb CMOS Serial EEPROM DEVICE DESCRIPTION
CAT24C128 128-Kb Serial CMOS EEPROM, internally organized pages bytes each, total 16,384 bytes bits each. features 64-byte page write buffer supports both Standard (100 kHz) well Fast (400 kHz) protocol. Write operations inhibited taking High (this protects entire memory).
Supports Standard Fast Protocol 1.8V 5.5V Supply Voltage Range 64-Byte Page Write Buffer Hardware Write Protection entire memory Schmitt Triggers Noise Suppression Filters
Inputs (SCL SDA).
power CMOS technology 1,000,000 program/erase cycles year data retention Industrial temperature range RoHS-compliant 8-lead PDIP, SOIC TSSOP
packages
Ordering Information details, page
CONFIGURATION
PDIP SOIC TSSOP
FUNCTIONAL SYMBOL
CAT24C128
location please consult corresponding package drawing.
FUNCTIONS
Device Address Inputs Serial Data Input/Output Serial Clock Input Write Protect Input Power Supply Ground
Catalyst carries protocol under license from Philips Corporation.
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
Doc. 1103, Rev.
CAT24C128
ABSOLUTE MAXIMUM RATINGS(1) Storage Temperature Voltage with Respect Ground(2) RELIABILITY CHARACTERISTICS(3) Symbol NEND(4) Parameter Endurance Data Retention 1,000,000 Units Program/ Erase Cycles Years -65°C +150°C -0.5 +6.5
D.C. OPERATING CHARACTERISTICS -40°C 85°C, unless otherwise specified. Symbol ICCR ICCW VOL1 VOL2 Parameter Read Current Write Current Standby Current Leakage Input Voltage Input High Voltage Output Voltage Output Voltage Test Conditions Read Write Pins -0.5 Units
IMPEDANCE CHARACTERISTICS -40°C 85°C, unless otherwise specified. Symbol CIN(3) CIN(3) IWP(5) Parameter Capacitance Input Capacitance (other pins) Input Current Conditions
Note: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions outside those listed operational sections this specification implied. Exposure absolute maximum rating extended periods affect device performance reliability. input voltage should lower than -0.5 higher than During transitions, voltage undershoot less than -1.5 overshoot more than periods less than These parameters tested initially after design process change that affects parameter according appropriate AEC-Q100 JEDEC test methods. Page Mode, 25°C When driven, pulled down internally. improved noise immunity, internal pull-down relatively strong; therefore external driver must able supply pull-down current when attempting drive input HIGH. conserve power, input level exceeds trip point CMOS input buffer VCC), strong pull-down reverts weak current source.
Units
Doc. 1103, Rev.
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C128
A.C. CHARACTERISTICS(1) -40°C 85°C. Standard Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tF(2) tSU:STO tBUF Ti(2) tSU:WP tHD:WP tPU(2,
Note: Test conditions according "A.C. Test Conditions" table. Tested initially after design process change that affects this paramete. delay between time stable device ready accept commands.
Fast Units
Parameter Clock Frequency START Condition Hold Time Period Clock High Period Clock START Condition Setup Time Data Hold Time Data Setup Time Rise Time Fall Time STOP Condition Setup Time Free Time Between STOP START Data Data Hold Time Noise Pulse Filtered Inputs Setup Time Hold Time Write Cycle Time Power-up Ready Mode
1000
A.C. TEST CONDITIONS Input Levels Input Rise Fall Times Input Reference Levels Output Reference Levels Output Load
VCC, Current Source: (VCC (VCC
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CAT24C128
POWER-ON RESET (POR)
CAT24C128 incorporates Power-On Reset (POR) circuitry which protects device against powering wrong state. CAT24C128 will power into Standby mode after exceeds trigger level will power down into Reset mode when drops below trigger level. This bi-directional feature protects device against `brown-out' failure following temporary loss power.
PROTOCOL
consists `wires', SDA. wires connected supply pull-up resistors. Master Slave devices connect 2wire their respective pins. transmitting device pulls down line `transmit' releases `transmit' `1'. Data transfer initiated only when busy (see A.C. Characteristics). During data transfer, line must remain stable while line HIGH. transition while HIGH will interpreted START STOP condition (Figure START condition precedes commands. consists HIGH transition while HIGH. START acts `wake-up' call receivers. Absent START, Slave will respond commands. STOP condition completes commands. consists HIGH transition while HIGH. Device Addressing Master initiates data transfer creating START condition bus. Master then broadcasts 8-bit serial Slave address. first bits Slave address 1010, normal Read/Write operations (Figure next bits, select possible Slave devices must match state external address pins. last bit, R/W, specifies whether Read Write operation performed. Acknowledge After processing Slave address, Slave responds with acknowledge (ACK) pulling down line during clock cycle (Figure Slave will also acknowledge address bytes every data byte presented Write mode. Read mode Slave shifts data byte, then releases line during clock cycle. long Master acknowledges data, Slave will continue transmitting. Master terminates session acknowledging last data byte (NoACK) issuing STOP condition. timing illustrated Figure
DESCRIPTION
SCL: Serial Clock input accepts Serial Clock generated Master. SDA: Serial Data receives input data transmits data stored EEPROM. transmit mode, this open drain. Data acquired positive edge, delivered negative edge SCL. Address pins accept device address. When driven, these pins pulled internally. Write Protect input inhibits write operations, when pulled HIGH. When driven, this pulled internally.
FUNCTIONAL DESCRIPTION
CAT24C128 supports Inter-Integrated Circuit (I2C) data transmission protocol, which defines device that sends data transmitter device receiving data receiver. Data flow controlled Master device, which generates serial clock START STOP conditions. CAT24C128 acts Slave device. Master Slave alternate either transmitter receiver. devices connected determined device address inputs
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2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C128
Figure START/STOP Conditions
START CONDITION STOP CONDITION
Figure Slave Address Bits
DEVICE ADDRESS
Figure Acknowledge Timing
RELEASE DELAY (TRANSMITTER) FROM MASTER RELEASE DELAY (RECEIVER)
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START DELAY tAA) SETUP tSU:DAT)
Figure Timing
tLOW tSU:STA tBUF tHD:STA tHD:DAT tSU:DAT tSU:STO tHIGH tLOW
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CAT24C128
WRITE OPERATIONS
Byte Write Upon receiving Slave address with `0', CAT24C128 will interpret next bytes address bytes These bytes used initialize internal address counter; most significant bits `don't care', next point available pages last point location within byte page. byte following address bytes will interpreted data. data will loaded into Page Write Buffer will eventually written memory address specified active address bits provided earlier. CAT24C128 will acknowledge Slave address, address bytes data byte. Master then starts internal Write cycle issuing STOP condition (Figure During internal Write cycle (tWR), output will tri-stated additional Read Write requests will ignored (Figure Page Write continuing load data into Page Write Buffer after data byte before issuing STOP condition, bytes written simultaneously during internal Write cycle (Figure more data bytes loaded than locations available page, then loading will continue from beginning page, i.e. page address latched address count automatically increments then wrapsaround page boundary. Previously loaded data thus overwritten data. What eventually written memory reflects latest Page Write Buffer contents. Only data loaded within most recent Page Write sequence will written memory. Acknowledge Polling ready/busy status CAT24C128 ascertained sending Read Write requests immediately following STOP condition that initiated internal Write cycle. long internal Write progress, CAT24C128 will acknowledge Slave address. Hardware Write Protection With held HIGH, entire memory protected against Write operations. left floating grounded, impact operation CAT24C128. state strobed last falling edge immediately preceding first data byte (Figure HIGH during strobe interval, CAT24C128 will acknowledge data byte Write request will rejected. Delivery State CAT24C128 shipped erased, i.e., bytes FFh.
Doc. 1103, Rev.
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C128
Figure Byte Write Sequence
ACTIVITY: MASTER SLAVE SLAVE ADDRESS ADDRESS BYTE a13-a8 ADDRESS BYTE a7-a0 DATA BYTE
Don't Care
Figure Write Cycle Timing
Byte
STOP CONDITION START CONDITION ADDRESS
Figure Page Write Sequence
ACTIVITY: MASTER SLAVE Don't Care ADDRESS BYTE a13-a8 ADDRESS BYTE a7-a0 DATA BYTE DATA BYTE DATA BYTE
SLAVE ADDRESS
Figure Timing
ADDRESS BYTE DATA BYTE
tSU:WP
tHD:WP
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CAT24C128
READ OPERATIONS
Immediate Read Upon receiving Slave address with `1', CAT24C128 will interpret this request data residing current byte address memory. CAT24C128 will acknowledge Slave address, will immediately shift data residing current address, will then wait Master respond. Master does acknowledge data (NoACK) then follows with STOP condition (Figure CAT24C128 returns Standby mode. Selective Read read data residing specific location, internal address counter must first initialized described under Byte Write. rather than following address bytes with data, Master instead follows with Immediate Read sequence, then CAT24C128 will active addres bits initialize internal address counter will shift data residing corresponding location. Master does acknowledge data (NoACK) then follows with STOP condition (Figure 10), CAT24C128 returns Standby mode. Sequential Read during Read session Master acknowledges data byte, then CAT24C128 will continue transmitting data residing subsequent locations until Master responds with NoACK, followed STOP (Figure 11). contrast Page Write, during Sequential Read address count will automatically increment then wrap-around memory (rather than page).
Doc. 1103, Rev.
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C128
Figure Immediate Read Sequence Timing
SLAVE ADDRESS
ACTIVITY: MASTER
SLAVE
DATA BYTE
DATA STOP
Figure Selective Read Sequence
ACTIVITY: MASTER
SLAVE ADDRESS
ADDRESS BYTE a13-a8
ADDRESS BYTE a7-a0
SLAVE ADDRESS
DATA BYTE
SLAVE
Don't Care
Figure Sequential Read Sequence
ACTIVITY: SLAVE ADDRESS
MASTER
SLAVE
DATA BYTE
DATA BYTE
DATA BYTE
DATA BYTE
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
1103, Rev.
CAT24C128
8-LEAD WIDE PLASTIC
SYMBOL
0.38 3.05 0.36 1.14 9.02 7.62 6.09 7.87 0.115
4.57 3.81 0.56 1.77 10.16 8.25 7.11 9.65 0.150
24C16_8-LEAD_DIP_(300P).eps
0.46
7.87 6.35 2.54 0.130
current Tape Reel information, download file from:
Notes: dimensions millimeters. Complies with JEDEC Standard MS001. Dimensioning tolerancing ANSI Y14.5M-1982
Doc. 1103, Rev.
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C128
8-LEAD WIDE SOIC
SYMBOL
0.10 1.35 0.33 0.19 4.80 5.80 3.80
0.25 1.75 0.51 0.25 5.00 6.20 4.00
1.27 0.25 0.40 0.50 1.27
24C16_8-LEAD_SOIC.eps
current Tape Reel information, download file from:
Notes: dimensions millimeters. Complies with JEDEC specification MS-012.
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
1103, Rev.
CAT24C128
8-LEAD TSSOP
DETAIL
GAGE PLANE
IDENT. 0.25 SEATING PLANE DETAIL
SYMBOL
0.05 0.80 0.19 0.09 2.90 6.30 4.30 0.50 0.00
1.20 0.15 1.05 0.30 0.20 3.10 6.50 4.50 0.75 8.00
0.90
3.00 4.40 0.65 0.60
current Tape Reel information, download file from:
Notes: dimensions millimeters. Complies with JEDEC specification MO-153.
Doc. 1103, Rev.
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C128
PACKAGE MARKING
8-Lead PDIP 8-Lead SOIC
24C128LI FYYWWB
24C128WI FYYWWB
24C128L
Catalyst Semiconductor, Inc. Device Code Temperature Range Production Year Production Week Product Revision Lead Finish NiPdAu
Catalyst Semiconductor, Inc. 24C128W Device Code Temperature Range Production Year Production Week Product Revision Lead Finish NiPdAu
8-Lead TSSOP
YMBF 24128I
24128
Production Year Production Month Product Revision Device Code Temperature Range Lead Finish NiPdAu
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
1103, Rev.
CAT24C128
ORDERING INFORMATION
Prefix Device 24C128 Suffix
Company
Product Number 24C128
Temperature Range Industrial (-40°C +85°C)
Tape Reel 3000/Reel
Package PDIP SOIC, JEDEC TSSOP
Lead Finish NiPdAu
Notes: packages RoHS-compliant (Lead-free, Halogen-free). standard lead finish NiPdAu. device used above example CAT24C128YI-GT3 (TSSOP, Industrial Temperature, NiPdAu, Tape Reel). additional package temperature options, please contact your nearest Catalyst Semiconductor Sales office.
Doc. 1103, Rev.
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C128
REVISION HISTORY
Date 10/07/05 11/16/05 02/02/06 03/13/06 04/26/06 Revision Comments Initial Issue Update Ordering Information Tape Reel Specifications Update A.C. Characteristics Update Ordering Information Update A.C. Characteristics Update Features Update Device Description Update Configuration Update A.C. Characteristics Update Hardware Write Protecttion Figure 8-Lead TSSOP Package Drawing Update Ordering Information 8-Lead TSSOP Package Marking Update Features Update Device Description Update Configuration Update Ordering Information Update D.C. Operating Characteristics Update Impedance Characteristics Update A.C. Characteristics Power-On Reset (POR) Update 8-Lead PDIP Package Drawing Update 8-Lead SOIC Package Drawing Update 8-Lead TSSOP Package Drawing Update Tape Reel Update Features Update D.C. Operating Characteristics Update Impedance Characteristics Update A.C. Test Conditions Update Power-On Reset (POR) Update Description Update Protocol Update Device Addressing Update Acknowledge Update Write Operations Update Byte Write Update Page Write Update Acknowledge Polling Delivery State Update Read Operations Update Selective Read Update Sequential Read Update Figure Update Part Marking Update Ordering Information
1103, Rev.
05/19/06
08/11/06
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
CAT24C128
Copyrights, Trademarks Patents Trademarks registered trademarks Catalyst Semiconductor include each following: MiniPot
Catalyst Semiconductor been issued U.S. foreign patents patent applications pending that protect products. CATALYST SEMICONDUCTOR MAKES WARRANTY, REPRESENTATION GUARANTEE, EXPRESS IMPLIED, REGARDING SUITABILITY PRODUCTS PARTICULAR PURPOSE, THAT PRODUCTS WILL INFRINGE INTELLECTUAL PROPERTY RIGHTS RIGHTS THIRD PARTIES WITH RESPECT PARTICULAR APPLICATION SPECIFICALLY DISCLAIMS LIABILITY ARISING SUCH APPLICATION, INCLUDING LIMITED CONSEQUENTIAL INCIDENTAL DAMAGES. Catalyst Semiconductor products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Catalyst Semiconductor product could create situation where personal injury death occur. Catalyst Semiconductor reserves right make changes discontinue product service described herein without notice. Products with data sheets labeled "Advance Information" "Preliminary" other products described herein production offered sale. Catalyst Semiconductor advises customers obtain current version relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications complete.
Doc. 1103, Rev.
2006 Catalyst Semiconductor, Inc. Characteristics subject change without notice
Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Santa Clara, 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com
Publication Revison: Issue date:
1103 08/11/06

128-Kb CMOS Serial EEPROM DEVICE DESCRIPTION CAT24C128 128-Kb Ser

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