WM9714L highly integrated input/output device designed mobile computin
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AC'97 Audio CODEC
WM9714L highly integrated input/output device designed mobile computing communications. chip architected dual CODEC operation, supporting Hi-Fi stereo Codec functions link interface, additionally supporting voice Codec functions type Synchronous Serial Port (SSP). third, auxiliary provided which used support generation supervisory tones, ring-tones different sample rates main codec. device connect directly mono stereo microphones, stereo headphones stereo speaker, reducing total component count system. Cap-less connections headphones, speakers, earpiece used, saving cost board area. Additionally, multiple analog input output pins provided seamless integration with analog connected wireless communication devices. device functions accessed controlled through single AC-Link interface compliant with AC'97 standard. 24.576 masterclock input directly generated internally from 13MHz other frequency) clock on-chip PLL. supports wide range input clock from 2.048MHz 78.6MHz. WM9714L operates supply voltages from 1.8V 3.6V. Each section chip powered down under software control save power. device available small leadless 7x7mm package, ideal hand-held portable systems.
WM9714L
FEATURES
AC'97 compatible stereo codec 94dB, -85dB 87dB, -86dB Variable Rate Audio, supports WinCE sample rates Tone Control, Bass Boost Enhancement On-chip 45mW headphone driver On-chip 400mW mono stereo speaker drivers Stereo, mono differential microphone input Automatic Level Control (ALC) insert button press detection Auxiliary mono (ring tone level generation) Seamless interface wireless chipset Additional PCM/I2S interface support voice CODEC derived audio clocks. Supports input clock ranging from 2.048MHz 78.6MHz 1.8V 3.6V supplies (digital down 1.62V, speaker 4.2V) 7x7mm 48-lead package
APPLICATIONS
Personal Digital Assistants (PDA) with without phone Smartphones Handheld Tablet Computers
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS
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WM9714L TABLE CONTENTS
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DESCRIPTION FEATURES.1 APPLICATIONS BLOCK DIAGRAM TABLE CONTENTS CONFIGURATION.4 ORDERING INFORMATION DESCRIPTION ABSOLUTE MAXIMUM RATINGS.6 RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS
AUDIO OUTPUTS. AUDIO INPUTS. AUXILIARY MONO (AUXDAC). VOICE (VXDAC) AUXILIARY ADC. COMPARATORS REFERENCE VOLTAGES DIGITAL INTERFACE CHARACTERISTICS.
POWER CONSUMPTION DEVICE DESCRIPTION.11
INTRODUCTION. AUDIO PATHS OVERVIEW. CLOCK GENERATION CLOCK DIVISION MODES MODE DIGITAL INTERFACES. AC97 INTERFACE INTERFACE
AUDIO ADCS
STEREO ADC. RECORD SELECTOR RECORD GAIN. AUTOMATIC LEVEL CONTROL.
AUDIO DACS
STEREO DAC. VOICE AUXILIARY DAC.
VARIABLE RATE AUDIO SAMPLE RATE CONVERSION AUDIO INPUTS
LINE INPUT MICROPHONE INPUT. MONOIN INPUT. PCBEEP INPUT DIFFERENTIAL MONO INPUT
AUDIO MIXERS.43
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MIXER OVERVIEW HEADPHONE MIXERS SPEAKER MIXER MONO MIXER. MIXER OUTPUT INVERTERS.
ANALOGUE AUDIO OUTPUTS
HEADPHONE OUTPUTS HPR. MONO OUTPUT SPEAKER OUTPUTS SPKL SPKR AUXILIARY OUTPUTS OUT3 OUT4 THERMAL SENSOR JACK INSERTION AUTO-SWITCHING.
DIGITAL AUDIO (SPDIF) OUTPUT.53 AUXILIARY ADDITIONAL FEATURES.58
BATTERY ALARM ANALOGUE COMPARATORS. GPIO INTERRUPT CONTROL.
POWER MANAGEMENT
INTRODUCTION. AC97 CONTROL REGISTER. EXTENDED POWERDOWN REGISTERS ADDITIONAL POWER MANAGEMENT. POWER RESET (POR) AC97 INTERFACE TIMING.
REGISTER MAP.71
REGISTER BITS ADDRESS
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS. LINE OUTPUT AC-COUPLED HEADPHONE OUTPUT. COUPLED (CAPLESS) HEADPHONE OUTPUT LOUDSPEAKER OUTPUT COMBINED HEADSET SPEAKER. COMBINED HEADSET SINGLE-ENDED SPEAKER. JACK INSERT DETECTION HOOKSWITCH DETECTION. TYPICAL OUTPUT CONFIGURATIONS
PACKAGE DIMENSIONS IMPORTANT NOTICE
ADDRESS:.
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WM9714L CONFIGURATION
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ORDERING INFORMATION
DEVICE WM9714LGEFL/V WM9714LGEFL/RV Note: Reel quantity 2,200 TEMPERATURE RANGE +85oC +85oC PACKAGE 48-lead (Pb-free) 48-lead (Pb-free, tape reel) MOISTURE SENSITIVITY LEVEL MSL3 MSL3 PEAK SOLDERING TEMPERATURE 260oC 260oC
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WM9714L
NAME DBVDD MCLKA MCLKB GPIO6 (ADA MASK) DGND1 SDATAOUT BITCLK DGND2 SDATAIN DCVDD SYNC RESETB GPIO7 AUX4 GPIO8 (SPDIF) AVDD2 AGND3 PCBEEP MONOIN MIC1 MICCM LINEL LINER AVDD AGND VREF MICBIAS MIC2A COMP1 AUX1 MIC2B COMP2 AUX2 MONO CAP2 OUT4 SPKGND SPKL SPKR OUT3 SPKVDD HPGND AGND2 HPVDD TYPE Supply Digital Input Digital In/Out Supply Digital Input Digital Output Supply Digital Output Supply Digital Input Digital Analogue Supply Analogue Input Analogue Input Analogue Input Analogue Input Supply Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Supply Supply Analogue Output Analogue Output Analogue Input Analogue Input Analog output Analogue Analogue Output Supply Analogue Output Analogue Output Analogue Output Supply Analogue Output Supply Analogue Output Supply Supply Digital Buffer Supply Master Clock Input Master Clock Input GPIO6 (ADA output MASK input) Digital Ground (return path both DCVDD DBVDD) Serial Data Output from Controller Input WM9714L Serial Interface Clock Output Controller Digital Ground (return path both DCVDD DBVDD) Serial Data Input Controller Output from WM9714L Digital Core Supply Serial Interface Synchronisation Pulse from Controller Reset (asynchronous, active Low, resets registers their default) GPIO7 Auxiliary input GPIO8 (SPDIF digital audio output) Analogue Supply connect connect connect connect Analogue Ground Line Input analogue audio mixers, typically used beeps Mono Input (RX) Microphone preamp input Microphone common mode input Left Line Input Right Line Input Analogue Supply (audio DACs, ADCs, PGAs, amps, mixers) Analogue Ground Internal Reference Voltage (buffered CAP2) Bias Voltage Microphones (buffered CAP2 1.8) Microphone preamp input COMP1 input Auxillary input Microphone preamp input COMP2 input Auxillary input Mono output driver (line headphone) Internal Reference Voltage (normally AVDD/2, overdriven) Auxillary output driver (speaker, line headphone) Speaker ground (feeds output buffers pins Left speaker driver (speaker, line headphone) Right speaker driver (speaker, line headphone) Auxillary output driver (speaker, line headphone) Speaker supply (feeds output buffers pins Headphone left driver (line headphone) Headphone ground (feeds output buffers pins Headphone right driver (line headphone) Analogue ground, chip substrate Headphone supply (feeds output buffers pins
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WM9714L
Notes: NAME GPIO1 PCMCLK GPIO2 GPIO3 PCMFS GPIO4 MASK PCMDAC GPIO5 SPDIF PCMADC GND_PADDLE TYPE Digital Digital Digital Digital Digital DESCRIPTION GPIO interface clock GPIO (Interrupt Request) output GPIO frame signal
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GPIO (ADC data available) output Mask input input (DAC) data GPIO SPDIF digital audio output output (ADC) data Paddle (Note
recommended that GND_PADDLE connected analogue ground. Refer "Recommended External Components" diagram "Package Dimensions" section further information.
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings stress ratings only. Permanent damage device caused continuously operating beyond these limits. Device functional operating limits guaranteed performance specifications given under Electrical Characteristics test conditions specified. Sensitive Device. This device manufactured CMOS process. therefore generically susceptible damage from excessive static voltages. Proper precautions must taken during handling storage this device. Wolfson tests package types according IPC/JEDEC J-STD-020B Moisture Sensitivity determine acceptable storage conditions prior surface mount assembly. These levels are: MSL1 unlimited floor life <30°C Relative Humidity. normally stored moisture barrier bag. MSL2 storage year <30°C Relative Humidity. Supplied moisture barrier bag. MSL3 storage hours <30°C Relative Humidity. Supplied moisture barrier bag. Moisture Sensitivity Level each package type specified Ordering Information. CONDITION Digital supply voltages (DCVDD, DBVDD) Analogue supply voltages (AVDD, AVDD2, HPVDD) Speaker supply voltage (SPKVDD) Voltage range digital inputs Voltage range analogue inputs Operating temperature range, -0.3V -0.3V -0.3V DGND -0.3V AGND -0.3V
+3.63V +3.63V +4.2V DBVDD +0.3V AVDD +0.3V +85oC
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital input/output buffer supply range Digital core supply range Analogue supply range Speaker supply range Digital ground Analogue ground Difference AGND DGND Note: AGND normally same DGND1/DGND2 DCVDD DBVDD DCVDD AVDD DCVDD should >=2V when using SYMBOL DBVDD DCVDD AVDD, AVDD2, HPVDD SPKVDD DGND1, DGND2 AGND, AGND3, HPGND, SPKGND Note -0.3 TEST CONDITIONS 1.71 1.71 +0.3 UNIT
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ELECTRICAL CHARACTERISTICS
AUDIO OUTPUTS
Test Conditions DBVDD=3.3V, DCVDD 3.3V, AVDD=HPVDD=SPKVDD =3.3V, +25oC, 1kHz signal, 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Full-scale output (0dBFS) Signal Noise Ratio (A-weighted) Total Harmonic Distortion Power Supply Rejection PSRR -3dB output 100mV, 20Hz 20kHz signal AVDD 200mW SYMBOL TEST CONDITIONS AVDD 3.3V, gains UNIT Line-Out (HPL/R, SPKL/R MONO with 50pF load)
Speaker Output (SPKL/SPKR with bridge tied load, INV=1) Output Power Abs. output power Total Harmonic Distortion Signal Noise Ratio (A-weighted) Output Power Abs. output power Total Harmonic Distortion Signal Noise Ratio (A-weighted) Output Power channel Total Harmonic Distortion POmax 0.05 (rms) (rms)
Stereo Speaker Output (SPKL/OUT4 SPKR/OUT3 with bridge tied load, INV=1) POmax 200mW 0.05 (rms) (rms)
Headphone Output (HPL/R, OUT3/4 SPKL/SPKR with load) Output power very closely correlated with THD; below. PO=10mW, RL=16 PO=10mW, RL=32 PO=20mW, RL=16 PO=20mW, RL=32 Signal Noise Ratio (A-weighted) Note: values valid output power level quoted above example, HPVDD=3.3V RL=16, -80dB when output power 10mW. Higher output power possible, will result deterioration THD.
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AUDIO INPUTS
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Test Conditions DBVDD=3.3V, DCVDD 3.3V, AVDD 3.3V, +25oC, 1kHz signal, 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Full Scale Input Signal Level (0dBFS) SYMBOL VINFS TEST CONDITIONS AVDD 3.3V AVDD 1.8V differential input mode AVDD 3.3V differential input mode AVDD 1.8V Input Resistance Input Capacitance Line input (LINEL, LINER, MONOIN) Signal Noise Ratio (A-weighted) Total Harmonic Distortion Power Supply Rejection Signal Noise Ratio (A-weighted) Total Harmonic Distortion PSRR -3dBFS input 20Hz 20kHz 20dB boost enabled 20dB boost enabled gain 12dB gain 25.6 10.4 0.545 0.273 38.4 15.6 UNIT Vrms
LINEL/R, MIC1/2A/2B MONOIN pins
Microphone input (MIC1/2A/2B pins)
AUXILIARY MONO (AUXDAC)
Test Conditions DBVDD=3.3V, DCVDD 3.3V, AVDD 3.3V, +25oC, 1kHz signal, 8kHz, 24-bit audio data unless otherwise stated. PARAMETER Resolution Full scale output voltage Signal Noise Ratio (A-weighted) Total Harmonic Distortion AVDD=3.3V SYMBOL TEST CONDITIONS UNIT bits Vrms
VOICE (VXDAC)
Test Conditions DBVDD=3.3V, DCVDD 3.3V, AVDD 3.3V, 1kHz signal, 8kHz, 24-bit audio data unless otherwise stated. PARAMETER Resolution Sample rates Full scale output voltage Signal Noise Ratio (A-weighted) Total Harmonic Distortion AVDD=3.3V SYMBOL TEST CONDITIONS UNIT bits Ks/s Vrms
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AUXILIARY
Test Conditions DBVDD 3.3V, DCVDD 3.3V, AVDD 3.3V, +25oC, unless otherwise stated. PARAMETER Input Voltage Input leakage current Resolution Differential Non-Linearity Error Integral Non-Linearity Error Offset Error Gain Error Power Supply Rejection Channel-to-channel isolation Throughput Rate Settling Time (programmable) 1111 (zero settling time) MCLK 24.576MHz PSRR selected input SYMBOL TEST CONDITIONS AGND ±0.25 AVDD UNIT bits
Input Pins AUX4, COMP1/AUX1, COMP2/AUX2
COMPARATORS
Test Conditions DBVDD 3.3V, DCVDD 3.3V, AVDD 3.3V, +25oC, unless otherwise stated. PARAMETER Input Voltage Input leakage current Comparator Input Offset (COMP1, COMP2 only) COMP2 delay (COMP2 only) MCLK 24.576MHz selected input SYMBOL TEST CONDITIONS AGND 10.9 AVDD UNIT
COMP1/AUX1 COMP2/AUX2 (pins when used inputs)
REFERENCE VOLTAGES
Test Conditions DBVDD=3.3V, DCVDD 3.3V, AVDD 3.3V, +25oC, 1kHz signal, 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Audio ADCs, DACs, Mixers Reference Input/Output Buffered Reference Output Microphone Bias Bias Voltage Bias Current Source Output Noise Voltage VMICBIAS IMICBIAS 20kHz 2.92 2.97 3.00 nV/Hz CAP2 VREF 1.63 1.64 1.65 1.65 1.66 1.67 SYMBOL TEST CONDITIONS UNIT
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DIGITAL INTERFACE CHARACTERISTICS
Test Conditions DBVDD 3.3V, DCVDD 3.3V, +25oC, unless otherwise stated. PARAMETER Input HIGH level Input level Output HIGH level Output level Clock Frequency Master clock (MCLKA pin) AC'97 clock (BIT_CLK pin) AC'97 sync pulse (SYNC pin) Note: audio non-audio sample rates other timing scales proportionately with master clock. signal timing AC-Link, please refer AC'97 specification (Revision 2.2) 24.576 12.288 SYMBOL source current sink current TEST CONDITIONS
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UNIT
Digital Logic Levels (all digital input output pins) CMOS Levels
POWER CONSUMPTION
power consumption WM9714L depends following factors: Supply voltages: Reducing supply voltages also reduces digital supply currents, therefore results significant power savings especially digital sections WM9714L. Operating mode: Significant power savings achieved always disabling parts WM9714L that used (e.g. audio ADC, DAC, AUXADC). Sample rates: Running lower sample rates will reduce power consumption significantly. figures below 48kHz (unless otherwise specified), many scenarios necessary this frequency, e.g. 8kHz voice call scenario uses only 11.4mW (see below).
MODE
AVDD Supply Current 0.01 0.014 2.37 3.644 3.733 4.801
DCVDD Supply Current 9.720
DBVDD Supply Current 0.005 0.005 0.006 2.974 2.789 2.814
Total Power (mW) 0.05 0.06 11.4 58.05 53.60 59.79
(lowest possible power) Clocks stopped. This default configuration after power-up. (Low Power Standby) VREF maintained using 1MOhm string Voice call (fs=8kHz) Record from mono microphone Stereo Playback link headphone) Stereo Playback link headphone) running with 13MHz input MCLKB Maximum Power everything Table Supply Current Consumption
10.973 10.504
13.656 15.472
2.938 105.82
Notes: Unless otherwise specified, figures +25C, audio sample rate 48kHz, with zero signal (quiescent), voltage references settled. power dissipated headphones speakers included above table.
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WM9714L
DEVICE INTRODUCTION
WM9714L largely compatible upgrade WM9712, with voice codec added. This codec interfaced type audio interface which makes GPIO pins connection. designed meet mixed-signal requirements portable wireless smartphone systems. includes audio recording playback, battery monitoring, auxiliary GPIO functions, controlled through single 5-wire AC-Link interface. Additionally, voice codec functions supported through provision additional voice audio serial interface. included allow unrelated reference clocks used generation link system clock. Typically 13MHz 2.048MHz references might used reference.
SOFTWARE SUPPORT
basic audio features WM9714L software compatible with standard AC'97 device drivers. However, better support additional functions, Wolfson Microelectronics supplies custom device drivers selected CPUs operating systems. Please contact your local Wolfson Sales Office more information.
AC'97 COMPATIBILITY
WM9714L uses AC'97 interface communicate with microprocessor controller. audio GPIO functions largely compliant with AC'97 Revision 2.2. following differences from AC'97 standard noted: Pinout: function some pins been changed support device specific features. PHONE PCBEEP pins have been moved different locations device package. Package: default package WM9714L leadless package. Audio mixing: WM9714L handles audio functions smartphone, including audio playback, voice recording, phone calls, phone call recording, ring tones, well simultaneous these features. AC'97 mixer architecture does fully support this. WM9714L therefore uses modified AC'97 mixer architecture with three separate mixers. Tone Control, Bass Boost Enhancement: These functions implemented digital domain therefore affect only signals being played through audio DACs, output signals stipulated AC'97.
Some other functions additional AC'97: On-chip loudspeaker driver mono stereo speakers On-chip driver speaker (phone receiver) Auxiliary mono ring tones, system alerts etc. Auxiliary Inputs Analogue Comparators Battery Alarm Programmable Filter Characteristics Tone Control Enhancement interface additional Voice existing audio ADCs create AC'97 system clock from unrelated reference clock input
CODEC
voice codec functions typically required mobile telephony devices provided extra voice WM9714L, which interfaced standard type data interface, which constructed through optional GPIO pins WM9714L. audio output data from both audio ADCs also output over this interface, allowing full voice codec function implemented. This interface supports sample rates from 48ks/s using standard AC'97 master clock.
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AUDIO PATHS OVERVIEW
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Figure Audio Paths Overvie
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WM9714L
CLOCK GENERATION
WM9714L supports clocking from separate sources, which selected AC'97 interface: External clock input MCLKA External clock input MCLKB
source clock divided appropriate frequencies order AC'97 interface, interface, voice Hi-fi means programmable divider block. Clock rates changed during operation AC'97 link order support alternative modes, example power mode when voice data being transmitted only. present flexibility selection input clock frequencies, typical choices being 2.048MHz, 4.096MHz 13MHz. Default mode power-up assumes clock will present MCLKA with powered down. This enables data clocked AC'97 link define desired clock divider mode whether needs activated. Note: This clock available frequency. When muxing between MCLKA MCLKB both clocks must active least clock cycles after switching event.
CLOCK DIVISION MODES
Figure shows clocking strategy WM9714L. Clocking controlled CLK_MUX, CLK_SRC S[6:0]. CLKAX2, CLKBX2 clock doublers inputs MCLKA MCLKB. CLK_MUX selects between MCLKA MCLKB. CLK_SRC selects between external derived clock reference. S[3:0] sets voice clock rate interface clock when master mode (division ratio available). S[6:4] sets hi-fi clocking rate (division ratio available).
registers used these switches accessed from register address (see Table mode change requires switching from external clock generated clock then recommended clock division ratios required clock scheme prior switching between clocks. This option accommodated means sets registers. SPLL[6:0] used divide ratio clock when mode SEXT[6:0] used divide clock when derived from external source. selected (CLK_SRC S[6:0] SPLL[6:0]. SPLL[6:0] defined register (see Table written using page address mode. More details page address mode controlling found page Register also contains number separate control bits relating PLL's function. external clock selected (CLK_SRC S[6:0] SEXT[6:0]. SEXT[6:0] defined register address 44h. Writing registers enables pre-programming required clock mode before output selected.
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Figure Clocking Architecture WM9714L
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WM9714L
DESCRIPTION Defines clock division ratio Hi-fi: DSP, ADCs DACs 000: 001: 111: Defines clock division ratio interface voice external clock mode only: 0000: 0001: 1111: f/16 Selects between clock External clock clock external clock Sets AUXADC clock divisor 000: f/16 001: f/12 010: 011: 100: 101: 110: 111: Clock doubler MCLKB Clock doubler MCLKA Selects between MCLKA MCLKB (N.B. power-up clock must present MCLKA must active clock cycles after switching MCLKB) SYSCLK=MCLKA SYSCLK=MCLKB
11:8
SEXT[3:0]
0000 (div
CLKSRC
(ext clk)
PENDIV
(div
CLKBX2 CLKAX2 CLKMUX
(Off) (Off) (MCLKA)
Table Clock Muxing Division Control
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INTERNAL CLOCK FREQUENCIES
internal clock frequencies defined follows (refer Figure
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AC97 nominally 24.576MHz, used generate AC97 BITCLK 12.288MHz. HIFI HIFI playback 48ks/s HIFI 24.576MHz. Table voice only playback. Voice Table sample rate clock frequency. SAMPLE RATE VOICE FREQUENCY 2.048MHz 2.048MHz 4.096MHz 4.096MHz 8.192MHz 12.288MHz HIFI FREQUENCY 24.576MHz 4.096MHz 24.576MHz 8.192MHz 24.576MHz 24.576MHz
8ks/s voice HIFI 8ks/s voice only (power save) 16ks/s voice HIFI 16ks/s voice only (power save) 32ks/s voice HIFI 48ks/s voice HIFI Table Clock Division Mode Table
AUXADC
clock AUXADC nominally runs 768kHz derived from BITCLK. divisor clock generator PENDIV. This enables AUXADC clock frequency according power consumption conversion rate considerations.
MODE
operation controlled register (see Table modes operation: Integer Fractional
been optimized nominal input clock (PLL_IN) frequencies range 8.192MHz 19.661MHz (LF=0) 2.048MHz 4.9152MHz (LF=1). Through clock divider (div input frequencies 78.6MHz accommodated. input clock divider enabled DIVSEL (0=Off) division ratio DIVCTL (0=div2, 1=div4).
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WM9714L
integer division control (must between integer mode) Allows operation with frequency input clocks 8.192MHz) Sigma Delta Modulator enable. Allows fractional division Enables input clock divided input clock above 14.4MHz Controls division mode when DIVSEL high. Pager address bits access programming K[21:0] SPLL[6:0] Pager data bits
Table Clock Control
INTEGER MODE
nominal output frequency (PLL_OUT) 98.304MHz which divided achieve nominal system clock 24.576MHz. integer division ratio determined FPLL_out FPLL_IN N[3:0] must range integer operation (0101 1100 12). Note that setting LF=1 enables further division required input frequencies range 2.048MHz 4.096MHz. Integer mode selected setting SDM=0.
FRACTIONAL MODE
Fractional mode provides divide resolution K[21:0] (register 46h, section). relationship between required division fractional division K[21:0] integer division N[3:0]
where rounded nearest whole number. example, PLL_IN clock 13MHz desired PLL_OUT clock 98.304MHz then desired division, 7.5618. N[3:0] will K[21:0] will 23F488h produce desired 98.304MHz clock (see Table INPUT CLOCK (PLL_IN) DESIRED OUTPUT (PLL_OUT) 98.304MHz 98.304MHz 98.304MHz 98.304MHz 98.304MHz DIVISION REQUIRED 7.5618 7.2818 FRACTIONAL DIVISION INTEGER DIVISION
2.048MHz 4.096MHz 12.288MHz 13MHz 27MHz (13.5MHz)**
0.5618 0.2818
12x4* 6x4*
*Divide enabled feedback path frequency inputs. **Divide enabled input frequencies 14.4MHz 38MHz (DIVSEL DIVCTL Table Modes Operation
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REGISTER PAGE ADDRESS MAPPING
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clock division control bits SPLL[6:0] fractional division bits accessed through register using sub-page address system. pager address allows blocks data words accessed whilst register address 46h. This means that when register address selected further cycles programming required page data bits. Control allocation these page addresses described Table PAGE ADDRESS 31:28 27:24 LABEL SPLL[6:4] SPLL[3:0] DEFAULT DESCRIPTION Clock division control SPLL[6:0]. Clock divider reads this control word enabled. Bits [6:4] [3:0] have same functionality [14:12] [11:8] respectively Reserved bits Sigma Delta Modulator control word fractional division. Division resolution 1/222
23:22 21:20 19:16 15:12 11:8
Reserved K[21:0]
Table Pager Control Allocation Powerdown internal clocks registers (see Table REGISTER ADDRESS LABEL DEFAULT (Off) (Off) DESCRIPTION Internal clock disable (active high) powerdown (active high)
N.B. both must asserted before enabled Table Powerdown Control
DIGITAL INTERFACES
WM9714L interfaces, data control AC'97 interface data only interface. AC'97 interface available through dedicated pins (SDATAOUT, SDATAIN, SYNC, BITCLK RESETB) sole control interface with access data streams device except Voice DAC. interface available through GPIO pins (PCMCLK, PCMFS, PCMDAC PCMADC) provides access Voice DAC. also transmit data from Stereo ADC. This useful, example, allow both sides phone conversation recorded mixing transmit receive paths channels transmitting over interface.
AC97 INTERFACE
INTERFACE PROTOCOL
WM9714L uses AC'97 interface both data transfer control. AC-Link wires: SDATAIN (pin carries data from WM9714L controller SDATAOUT (pin carries data from controller WM9714L BITCLK (pin clock, derived from either MCLKA MCLKB inputs supplied controller. SYNC synchronization signal generated controller passed WM9714L RESETB resets WM9714L default state
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WM9714L
Figure AC-Link Interface (typical case with BITCLK generated AC97 codec) SDATAIN SDATAOUT signals each carry time-division multiplexed data streams (slots 12). complete sequence slots referred AC-Link frame, contains total bits. frame rate 48kHz. This makes possible simultaneously transmit receive multiple data streams (e.g. audio, AUXADC, control) sample rates 48kHz. Detailed information found AC'97 (Revision 2.2) specification, which obtained Note: SDATAOUT SYNC must held when RESETB applied. These signals must held entire duration RESETB pulse especially during low-to-high transition RESETB. SDATAOUT SYNC high during reset, WM9714L enter test modes. Information relating this operation available AC'97 specification Wolfson applications note WAN-0104 available www.wolfsonmirco.com.
INTERFACE
OPERATION
WM9714L implement voice codec function using dedicated VXDAC either both existing hi-fi ADC's. codec mode, VXDAC input output interfaced style port GPIO pins. This interface support channel, stereo/dual channels required, (two channels data sent frame back back words). voice only mode, link used only control information, audio data. Therefore will generally shut down (PR4=1), except when control data must sent. interface makes GPIO interface pins, clock, frame, data in/out. codec function enabled then GPIO pins used other functions.
INTERFACE PROTOCOL
WM9714L audio interface used input data Voice output data from Stereo ADC. When enabled, audio interface uses four GPIO pins: GPIO1/PCMCLK: clock GPIO3/PCMFS: Frame Sync GPIO4/PCMDAC: Voice data input GPIO5/PCMADC: Stereo data output
Depending mode operation (see "PCM Interface Modes"), least these four pins must output writing register (see Table 57). When enabled GPIOs used other functions WM9714L.
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INTERFACE MODES
WM9714L audio interface configured four modes:
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Disabled Mode: WM9714L disables tri-states interface pins. clock input ignored ADC/DAC data transferred. Slave Mode: WM9714L accepts PCMCLK PCMFS inputs from external source. Master Mode: WM9714L generates PCMCLK PCMFS outputs. Partial Master Mode: WM9714L generates PCMCLK output, accepts PCMFS external input.
AUDIO DATA FORMATS Four different audio data formats supported: mode Left justified Right justified
four these modes first. They described below. Refer Electrical Characteristic section timing information. Interface configured Mono mode, where only channel data output. this mode interface should configured mode. short long frame sync supported available either (mode (mode rising edge VXCLK. Note that when operating stereo mode mono Voice always uses left channel data input.
1/fs PCMCLK
PCMFS
PCMCLK
PCMADC/ PCMDAC
Input Word Length (WL)
Figure Interface Mono Mode (mode FSP=0)
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1/fs PCMCLK
PCMFS
PCMCLK
PCMADC/ PCMDAC
Input Word Length (WL)
Figure Interface Mono Mode (mode FSP=1) mode, left channel available either (mode (mode rising edge PCMCLK (selectable FSP) following rising edge PCMFS. Right channel data immediately follows left channel data. Depending word length, PCMCLK frequency sample rate, there unused PCMCLK cycles between right channel data next sample.
1/fs BCLK VXCLK
PCMFS
PCMCLK
LEFT CHANNEL PCMADC/ PCMDAC
RIGHT CHANNEL
Input Word Length (WL)
Figure Mode Audio Interface (mode FSP=0)
1/fs BCLK VXCLK
PCMFS
PCMCLK
LEFT CHANNEL PCMADC/ PCMDAC
RIGHT CHANNEL
Input Word Length (WL)
Figure Mode Audio Interface (mode FSP=1)
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1/fs
LEFT CHANNEL PCMFS
RIGHT CHANNEL
PCMCLK
PCMADC/ PCMDAC
Figure Left Justified Audio Interface (assuming n-bit word length) Right Justified mode, available last rising edge PCMCLK before PCMFS transition. other bits transmitted before (MSB first). Depending word length, PCMCLK frequency sample rate, there unused PCMCLK cycles after each PCMFS transition.
1/fs
LEFT CHANNEL PCMFS
RIGHT CHANNEL
PCMCLK
PCMADC PCMDAC
Figure Right Justified Audio Interface (assuming n-bit word length) mode, available second rising edge PCMCLK following PCMFS transition. other bits then transmitted order. Depending word length, PCMCLK frequency sample rate, there unused PCMCLK cycles between sample next.
1/fs
LEFT CHANNEL PCMFS
RIGHT CHANNEL
PCMCLK
BCLK BCLK
PCMADC/ PCMDAC
Figure Justified Audio Interface (assuming n-bit word length)
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WM9714L
CONTROL
register bits controlling audio format, word length operating modes summarised below. CTRL must override normal interface pins GPIOs, MODE must specify master/slave modes. REGISTER ADDRESS Control LABEL CTRL DEFAULT DESCRIPTION Sets function control registers GPIO interface pins. GPIO pins GPIOs GPIO pins configured interface controlled this register interface mode when CTRL=1 interface disabled [PCMCLK tristated, PCMFS tri-stated] interface slave mode [PCMCLK input, PCMFS input] interface master mode [PCMCLK output, PCMFS output] interface partial master mode [PCMCLK output, PCMFS input] Voice clock PCMCLK divider. master mode PCMCLK derived from Voice clock. PCMCLK Voice clock PCMCLK Voice clock PCMCLK Voice clock PCMCLK Voice clock PCMCLK Voice clock VXDAC oversample rate: PCMCLK polarity invert PCMCLK polarity normal PCMCLK polarity Right, Left modes PCMFS polarity invert PCMFS polarity normal PCMFS polarity Mode mode select available PCMCLK rising edge after rising edge (mode available PCMCLK rising edge after rising edge (mode channel select Output left right data Swap output left right data Output left data only Output right data only
14:13
MODE
11:9
VDACOS
June 2006
WM9714L
REGISTER ADDRESS LABEL DEFAULT DESCRIPTION Data Word Length bits (see Note) bits bits bits Data Format Select Mode Format Left justified Right justified
Pre-Production
Table Codec Control Note: Right justified does support 32-bit data.
AUDIO ADCS
STEREO
WM9714L stereo sigma-delta digitize audio signals. achieves high quality audio recording power consumption. sample rate controlled writing control register (see "Variable Rate Audio"). independent sample rate. save power, left right ADCs separately switched using Powerdown bits ADCL ADCR (register 3Ch, bits 5:4), whereas disables both ADCs (see "Power Management" section). only running, same data appears both left right AC-Link slots. output from sent over either link usual, output interface which configured GPIO pins.
HIGH PASS FILTER
WM9714L audio incorporates digital high pass filter that eliminates bias from output data. filter enabled default. measurements, disabled writing (register 5Ch, This high pass filter corner frequency selected have different values WM9714L, suit applications such voice where higher cutoff frequency required. REGISTER ADDRESS LABEL DEFAULT DESCRIPTION High-pass filter disable Filter enabled (for audio) Filter disabled (for measurements) corner frequency Fs=48kHz 82Hz Fs=16kHz 82Hz Fs=8kHz 170Hz Fs=8kHz
HPMODE
Note: filter corner frequency proportional sample rate. Table Controlling Highpass Filter
SLOT MAPPING
default, output left audio appears slot SDATAIN signal (pin right data appears slot However, output data also sent other slots, setting (ADC slot select) control bits shown below.
June 2006
Pre-Production REGISTER ADDRESS Additional Functions LABEL DEFAULT
WM9714L
slot mapping Left Slot Right Slot (default) Left Slot Right Slot Left Slot Right Slot Left Slot Right Slot
Table Slot Mapping
RECORD SELECTOR
record selector determines which input signals routed into audio ADC. left right channels selected independently. This useful recording phone call: channel used signal other signal, that both sides conversation digitized. REGISTER ADDRESS Record Routing Select LABEL RECBST DEFAULT DESCRIPTION 20dB Boost Boost input signal 20dB boost Note: RECBST gain addition microphone pre-amps (MPABST MPBBST bits) record gain (GRL bits). Left signal source 000: MICA (pre-PGA) 001: MICB (pre-PGA) 010: LINEL (pre-PGA) 011: MONOIN (pre-PGA) 100: Headphone (left) 101: Speaker 110: Mono 111: Reserved this setting) Right signal source 000: MICA (pre-PGA) 001: MICB (pre-PGA) 010: LINER (pre-PGA) 011: MONOIN (pre-PGA) 100: Headphone (right) 101: Speaker 110: Mono 111: Reserved this setting)
RECSL
RECSR
Table Audio Record Selector
June 2006
WM9714L
RECORD GAIN
Pre-Production
amplitude signal that enters audio controlled Record (Programmable Gain Amplifier). gain programmed either writing Record Gain register, Automatic Level Control (ALC) circuit (see next section). When enabled, writes Record Gain register have effect. different gain ranges implemented: standard gain range defined AC'97 standard, extended gain range with smaller gain steps. circuit always uses extended gain range, this been found result better sound quality. REGISTER ADDRESS Record Gain LABEL DEFAULT DESCRIPTION Mute Audio (both channels) Mute (OFF) Mute (ON) Gain range select (left) Standard 22.5dB, 1.5dB step size) Extended (-17.25 +30dB, 0.75dB steps) Record Volume (left) Standard (GRL=0) XX0000: XX0001: +1.5dB (1.5dB steps) XX1111: +22.5dB Extended (GRL=1) 000000: -17.25dB 000001: -16.5dB (0.75dB steps) 111111: +30dB
13:8
RECVOLL
000000
Zero Cross Enable Record Gain changes immediately Record Gain changes when signal zero after time-out Gain range select (right) Similar Record Volume (right) Similar RECVOLR
RECVOLR
000000
Table Record Gain Register output Record also mixed into phone and/or headphone outputs (see "Audio Mixers"). This makes possible function microphone signal smartphone application. REGISTER ADDRESS Record Routing 15:14 LABEL DEFAULT (mute) DESCRIPTION Controls record headphone mixer paths. 00=stereo, 01=left only, 10=right only, 11=mute left right Controls gain record headphone mixer paths. 000: +6dB 001: +3dB (3dBsteps) 111: -15dB Controls record mono mixer path. 00=stereo, 01=left only, 10=right only, 11=mute left right Enables 20dB gain boost record mono mixer path
13:11
R2HVOL
(0dB)
10:9
(mute)
R2MBST
(OFF)
Table Record Routing Control
June 2006
Pre-Production
WM9714L
AUTOMATIC LEVEL CONTROL
WM9714L automatic level control that aims keep constant recording volume irrespective input signal level. This achieved continuously adjusting gain that signal level input remains constant. digital peak detector monitors output changes gain necessary.
input signal
gain
signal after
target level
hold time
decay time
attack time
Figure Operation function enabled using ALCSEL control bits. When enabled, recording volume programmed between -6dB -28.5dB (relative full scale) using ALCL register bits. HLD, control hold, decay attack times, respectively.
HOLD TIME
Hold time time delay between peak level detected being below target gain beginning ramp programmed power-of-two (2n) steps, e.g. 2.67ms, 5.33ms, 10.67ms etc. 43.7s. Alternatively, hold time also zero. hold time only applies gain ramp-up, there delay before ramping gain down when signal level above target.
DECAY (GAIN RAMP-UP) TIME
Decay time time that takes gain ramp across range (e.g. from -15B 27.75dB). time takes recording level return target value therefore depends both decay time gain adjustment required. gain adjustment small, will shorter than decay time. decay time programmed power-of-two (2n) steps, from 24ms, 48ms, 96ms, etc. 24.58s.
ATTACK (GAIN RAMP-DOWN) TIME
Attack time time that takes gain ramp down across range (e.g. from 27.75dB down -15B gain). time takes recording level return target value therefore depends both attack time gain adjustment required. gain adjustment small, will shorter than attack time. attack time programmed power-of-two (2n) steps, from 6ms, 12ms, 24ms, etc. 6.14s. When operating stereo, peak detector takes maximum left right channel peak values, gain setting applied both left right PGAs, that stereo image preserved. However, function also enabled channel only. this case, only controlled mechanism, while other channel runs independently with gain through control register.
June 2006
WM9714L
Pre-Production When channel unused, peak detector disregards that channel. function also operate when outputs mixed mono digital domain, they mixed mono analogue domain, before entering ADCs.
REGISTER ADDRESS Noise Gate Control
15:14
LABEL ALCSEL
DEFAULT (OFF)
DESCRIPTION function select (PGA gain register) Right channel only Left channel only Stereo (PGA registers unused) gain limit +30dB +24dB .(6dB steps) -6dB -12dB Programmable zero cross timeout (delay 12.288MHz BITCLK): 2^17 tbitclk (10.67 2^16 tbitclk (5.33 2^15 tbitclk (2.67 2^14 tbitclk (1.33 target sets signal level input 0000 -28.5dB 0001 -27.0dB (1.5dB steps) 1110 -7.5dB 1111 -6dB hold time before gain increased. 0000 0001 2.67ms 0010 5.33ms (time doubles with every step) 1111 43.691s decay (gain ramp-up) time 0000 24ms 0001 48ms 0010 96ms (time doubles with every step) 1010 higher 24.58s attack (gain ramp-down) time 0000 0001 12ms 0010 24ms (time doubles with every step) 1010 higher 6.14s
13:11
MAXGAIN
(+30dB)
10:9
ZCTIMEOUT
Control
15:12
ALCL
1011 (-12dB)
11:8
0000 (0ms)
0011 (192ms)
0010 (24ms)
Table Control
June 2006
Pre-Production
WM9714L
MAXIMUM GAIN
MAXGAIN register sets maximum gain value that whilst under control ALC. This effect when enabled.
PEAK LIMITER
prevent clipping when large signal occurs just after period quiet, circuit includes limiter function. input signal exceeds 87.5% full scale (-1.16dB), gain ramped down maximum attack rate when 0000), until signal level falls below 87.5% full scale. This function automatically enabled whenever enabled. (Note: 0000, then limiter makes difference operation ALC. designed prevent clipping when long attack times used).
NOISE GATE
When signal very quiet consists mainly noise, function cause "noise pumping", i.e. loud hissing noise during silence periods. WM9714L noise gate function that prevents noise pumping comparing signal level input pins (i.e. before record PGA) against noise gate threshold, NGTH. Provided that noise gate function enabled (NGAT noise gate cuts when: Signal level [dB] NGTH [dB] gain [dB] Boost gain [dB] This equivalent Signal level input [dB] NGTH [dB] gain then held constant (preventing from ramping normally would when signal quiet). set, output also muted when noise gate cuts table below summarises noise gate control register. NGTH control bits noise gate threshold with respect full-scale range. threshold adjusted 1.5dB steps. Levels extremes range cause inappropriate operation, care should taken with set-up function. Note that noise gate only works conjunction with function, always operates same channel(s) (left, right, both, none). REGISTER ADDRESS Noise Gate Control LABEL NGAT DEFAULT DESCRIPTION Noise gate function enable enable disable Noise gate type gain held constant mute output Noise gate threshold 00000: -76.5dBFS 00001: -75dBFS steps 11110: -31.5dBFS 11111: -30dBFS
NGTH(4:0)
00000
Table Noise Gate Control
June 2006
WM9714L AUDIO DACS
STEREO
Pre-Production
WM9714L stereo sigma-delta that achieves high quality audio playback power consumption. Digital tone control, adaptive bass boost enhancement functions operate digital audio data before passed stereo DAC. (Contrary AC'97 specification, they have effect analogue input signals signals played through auxiliary DAC. Nevertheless, bits reset register, 00h, indicate that WM9714L supports tone control bass boost.) output volume control. sample rate controlled writing control register (see "Variable Rate Audio"). independent sample rate. When DACs separately powered down using Powerdown register bits DACL DACR (register 3Ch, bits [7:6]).
STEREO VOLUME
volume output signal controlled (Programmable Gain Amplifier). Each mixed into headphone, speaker mono mixer paths (see "Audio Mixers") controlled register 0Ch. Each DAC-to-mixer path independent mute bit. When DAC-to-mixer paths muted muted automatically. When PGAs powered down using Powerdown register bits DACL DACR (register 3Ch, bits [7:6]). REGISTER ADDRESS Volume 12:8 LABEL DACL DEFAULT 01000 (0dB) DESCRIPTION Mute path headphone mixer Mute, mute (ON) Mute path speaker mixer Mute, mute (ON) Mute path mono mixer Mute, mute (ON) Left Volume 00000: +12dB (1.5dB steps) 11111: -34.5dB Right Volume similar DACLVOL Read-only indicate auto-muting auto-muted muted Auto-Mute Enable Automatically mutes analogue output stereo digital input zero Auto-mute
Additional Functions
DACR AMUTE
01000 (0dB)
AMEN
Table Stereo Volume Control
June 2006
Pre-Production
WM9714L
TONE CONTROL BASS BOOST
WM9714L provides separate controls bass treble with programmable gains filter characteristics. This function operates digital audio data before passed audio DACs. Bass control take different forms: Linear bass control: bass signals amplified attenuated user programmable gain. This independent signal volume, very high bass gains loud signals lead signal clipping. Adaptive bass boost: bass volume amplified variable gain. When bass volume low, boosted more than when bass volume high. This method recommended because prevents clipping, usually sounds more pleasant human ear.
Treble control applies user programmable gain, without adaptive boost function. Treble, linear bass enhancement produce signals that exceed full-scale. order avoid limiting under these conditions, recommended attenuate digital input signal 6dB. gain outputs should increased compensate attenuation. Cut-only tone adjustment (i.e. bass treble gains adaptive bass boost cannot produce signals above full-scale therefore require set. REGISTER ADDRESS Tone Control LABEL DEFAULT DESCRIPTION Bass Mode Linear bass control Adaptive bass boost Bass Cut-off Frequency (130Hz 48kHz sampling) High (200Hz 48kHz sampling) Bass Intensity Code 0000 0001 0010 0111 1011-1101 1110 1111 BB=0 +9dB +9dB +7.5dB (1.5dB steps) (1.5dB steps) -6dB -6dB Bypass (OFF) BB=1 (max) (min)
11:8
BASS
1111 (OFF)
-6dB attenuation Treble Cut-off Frequency High (8kHz 48kHz sampling) (4kHz 48kHz sampling) Treble Intensity 0000 0001 +9dB 0010 +7.5dB (1.5dB steps) 1011 1110 -6dB 1111 Treble Control Disabled
TRBL
1111 (Disabled)
Table Tone Control Note: cut-off frequencies change proportionally with sample rate.
June 2006
WM9714L
STEREO ENHANCEMENT
Pre-Production
stereo enhancement function artificially increases separation between left right channels amplifying (L-R) difference signal frequency range where human sensitive directionality. programmable depth setting controls degree stereo expansion introduced function. Additionally, upper lower limits frequency range used enhancement selected using 3DFILT control bits.
REGISTER ADDRESS General Purpose Control
LABEL
DEFAULT (disabled)
DESCRIPTION enhancement enable
3DLC
Lower Cut-off Frequency (200Hz 48kHz sampling) High (500Hz 48kHz sampling) Upper Cut-off Frequency High (2.2kHz 48kHz sampling) (1.5kHz 48kHz sampling) Depth 0000: (minimum effect) 0001: 6.67% .(6.67% steps) 1110: 93.3% 1111: 100% (maximum)
3DUC
3DDEPTH
0000
Table Stereo Enhancement Control Note: cut-off frequencies change proportionally with sample rate.
June 2006
Pre-Production
WM9714L
VOICE
VXDAC 16-bit mono intended playback voice signals input interface. Performance been optimised operating 8ks/s 16ks/s. VXDAC will function other sample rates 48ks/s, this recommended. analogue output VXDAC routed directly into output mixers. signal gain into each mixer adjusted mixer inputs using control register 18h. When VXDAC powered down using Powerdown register VXDAC (register 3Ch, 12).
REGISTER ADDRESS Powerdown VXDAC Output Control
LABEL VXDAC
DEFAULT
DESCRIPTION VXDAC powerdown OFF, Mute VXDAC path headphone mixer Mute, mute (ON) VXDAC headphone mixer gain 000: +6dB (3dB steps) 111: -15dB Mute VXDAC path speaker mixer Mute, mute (ON) VXDAC speaker mixer gain 000: +6dB (3dB steps) 111: -15dB Mute VXDAC path mono mixer Mute, mute (ON) VXDAC mono mixer gain 000: +6dB (3dB steps) 111: -15dB
14:12
V2HVOL
(0dB)
10:8
V2SVOL
(0dB)
V2MVOL
(0dB)
Table VXDAC Control
June 2006
WM9714L
AUXILIARY
Pre-Production
AUXDAC simple 12-bit mono DAC. used generate signals (with numeric input written into control register), signals such telephone-quality ring tones system beeps (with input signal supplied through AC-Link slot). mode (XSLE input data binary offset coded; mode (XSLE there offset. analogue output AUXDAC routed directly into output mixers. signal gain into each mixer adjusted mixer inputs using control register 12h. slot mode (XSLE AUXDAC also supports variable sample rates (See "Variable Rate Audio" section). When auxillary powered down using Powerdown register AUXDAC (register 3Ch, 11). REGISTER ADDRESS Powerdown AUXDAC Input Control LABEL AUXDAC XSLE DEFAULT DESCRIPTION AUXDAC powerdown OFF, AUXDAC input selection from AUXDACVAL (for signals) from AC-Link slot selected AUXDACSLT (for signals) AUXDAC Input Selection Slot bits 8-19 (with XSLE=1) Slot bits 8-19 (with XSLE=1) Slot bits 8-19 (with XSLE=1) Slot bits 8-19 (with XSLE=1) Slot bits 8-19 (with XSLE=1) Slot bits 8-19 (with XSLE=1) Slot bits 8-19 (with XSLE=1) RESERVED use) AUXDAC Digital Input (with XSLE=0) 000h: minimum FFFh: full-scale Mute AUXDAC path headphone mixer Mute, mute (ON) AUXDAC headphone mixer gain 000: +6dB (3dB steps) 111: -15dB Mute AUXDAC path speaker mixer Mute, mute (ON) AUXDAC speaker mixer gain 000: +6dB (3dB steps) 111: -15dB Mute AUXDAC path mono mixer Mute, mute (ON) AUXDAC mono mixer gain 000: +6dB (3dB steps) 111: -15dB
14:12
AUXDAC
11:0
AUXDAC
000h
AUXDAC Output Control
14:12
A2HVOL
(0dB)
10:8
A2SVOL
(0dB)
A2MVOL
(0dB)
Table AUXDAC Control
June 2006
Pre-Production
WM9714L
VARIABLE RATE AUDIO SAMPLE RATE CONVERSION
using AC'97 Rev2.2 compliant audio interface, WM9714L record playback commonly used audio sample rates, offer full split-rate support (i.e. DAC, AUXDAC sample rates completely independent each other combination possible). default sample rate 48kHz. register set, then other sample rates selected writing registers 2Ch, 2Eh. AC-Link continues frames second irrespective sample rate selected. However, sample rate less than 48kHz, then some frames carry audio sample. REGISTER ADDRESS Extended Audio Stat/Ctrl Audio Sample Rate LABEL DEFAULT (OFF) DESCRIPTION Variable Rate Audio (DAC 48kHz) (sample rates determined registers 32h) Audio sample rate 1F40h: 8kHz 2B11h: 11.025kHz 2EE0h: 12kHz 3E80h: 16kHz 5622h: 22.05kHz 5DC0h: 24kHz 7D00h: 32kHz AC44h: 44.1kHz BB80h: 48kHz other value defaults nearest supported sample rate Audio sample rate similar DACSR AUXDAC sample rate similar DACSR
15:0
DACSR
BB80h (48kHz)
Audio Sample Rate AUXDAC Sample Rate
15:0
ADCSR
BB80h (48kHz) BB80h (48kHz)
15:0
AUXDA
Table Audio Sample Rate Control
Note: Changing sample rate will only effective ADC's DAC's enabled powered before sample rate changed. This done setting relevant bits registers 3Ch, well register 2Ah.
process follows: Enable power ADC's DAC's registers 3Ch. Enable 2Ah, Change sample rate respective register.
June 2006
WM9714L AUDIO INPUTS
Pre-Production
following sections give overview analogue audio input pins their function. more information recommended external components, please refer "Applications Information" section.
LINE INPUT
LINEL LINER inputs designed record line level signals, and/or into analogue outputs. Both pins directly connected record selector. record adjusts recording volume, controlled register function. analogue mixing, line input signals pass through separate PGA, controlled register 0Ah. signals mixed into headphone, speaker mono mixer paths (see "Audio Mixers"). Each LINE-to-mixer path independent mute bit. When LINE-to-mixer paths muted line muted automatically. When line inputs used, line switched save power (see "Power Management" section). LINEL LINER biased internally reference voltage VREF. Whenever inputs muted device placed into standby mode, inputs remain biased VREF using special antithump circuitry suppress audible clicks when changing inputs. REGISTER ADDRESS 12:8 LABEL LINEL DEFAULT 01000 (0dB) DESCRIPTION Mute LINE path headphone mixer Mute, mute (ON) Mute LINE path speaker mixer Mute, mute (ON) Mute LINE path mono mixer Mute, mute (ON) LINEL input gain 00000: +12dB (1.5dB steps) 11111: -34.5dB LINER input gain similar LINELVOL
LINER
01000 (0dB)
Table Line Input Control Additionally, line inputs used single-ended microphone inputs through record provide clickless function bypassing offset introduced through microphone pre-amps. Note that line inputs mixers should deselected this input configuration used.
MICROPHONE INPUT
MICROPHONE PRE-AMPS
There microphone pre-amplifiers, MPB, which configured variety ways accommodate selectable differential microphone inputs differential microphone inputs operating simultaneously stereo noise cancellation. microphone input circuit shown Figure
June 2006
Pre-Production
WM9714L
Vmid
MIC1
Vmid 22h: 13-12
22h:11-10 +12dB +30dB
MIC2A
Vmid
MICA MICB
MIC2B
22h:9-8 +12dB +30dB
MICCM
Figure Microphone Input Circuit input pins used microphones MIC1, MICCM, MIC2A MIC2B. Note that input pins MIC2A MIC2B multi-function inputs must configured microphone inputs when required. This achieved using MICCMPSEL[1:0] register (see Table 23). input microphone pre-amp selected from three microphone inputs MIC1, MIC2A MIC2B using MPASEL[1:0]. Each pre-amp independent boost control from +12dB +30dB four steps. This controlled MPABST[1:0] MPBBST[1:0]. When each microphone pre-amp powered down using Powerdown register bits (register 3Eh, bits [1:0]). When disabled inputs tied Vmid (for MIC2A MIC2B this only applies when they selected microphone inputs, otherwise they left floating). REGISTER ADDRESS 15:14 LABEL MICCMPSEL DEFAULT DESCRIPTION MIC2A MIC2B configuration MIC2A MIC2B microphone inputs MIC2A only MIC2B only neither pre-amp input select MIC1 MIC2A MIC2B unused select) pre-amp gain control +12dB +18dB +24dB +30dB pre-amp gain control +12dB +18dB +24dB +30dB
13:12
MPASEL
11:10
MPABST
MPBBST
Table Microphone Pre-amp Control
June 2006
WM9714L
SINGLE OPERATION
Pre-Production
three microphones connected single-ended configuration. three MICs selected input using MPASEL[1:0] (Register 22h, bits 13:12). Only microphone MIC2B selected MPB. Note that MPABST always sets gain selected input microphone. MIC2B selected input recommended that disabled.
DUAL OPERATION
microphones connected dual differential configuration. This suitable stereo microphone noise cancellation applications. Mic1 connected between MIC2A MICCM inputs mic2 connected between MIC2B MICCM inputs shown Figure Additionally, another microphone supported MIC1 selected through input mux. Note that microphones connected single-ended configuration.
Figure Dual Microphone Configuration
MICROPHONE BIASING CIRCUIT
MICBIAS output provides noise reference voltage suitable biasing electret type microphones associated external resistor biasing network. Refer Applications Information section recommended external components. MICBIAS voltage altered MBVOL register 22h. When MBVOL=0, MICBIAS=0.9*AVDD when MBVOL=1, MICBIAS=0.75*AVDD. microphone bias driven dedicated MICBIAS enabled MPOP1EN register 22h. also configured drive GPIO8 enabled MPOP2EN register 22h. When microphone bias powered down using Powerdown register MICBIAS (register 3Eh, 14).
June 2006
Pre-Production REGISTER ADDRESS LABEL MBOP2EN MBOP1EN MBVOL DEFAULT (Off) (On)
WM9714L
Microphone bias enable GPIO8 (pin Microphone bias enable MICBIAS (pin Microphone bias voltage control AVDD 0.75 AVDD
Table Microphone Bias Voltage Control internal MICBIAS circuitry shown Figure Note that maximum source current capability MICBIAS 3mA. external biasing resistors therefore must large enough limit MICBIAS current 3mA.
Figure Microphone Bias Schematic
MICBIAS CURRENT DETECT
WM9714L includes microphone bias current detect circuit with programmable thresholds microphone bias current, above which interrupt will triggered. There separate interrupt bits, MICDET e.g. distinguish between microphones connected WM9714L, MICSHT detect shorted microphone (mic button press). microphone current detect threshold MCDTHR[2:0], MICDET, MCDSCTHR[1:0] MICSHT. Thresholds each code shown Table When microphone bias current detect circuit powered down using Powerdown register (register 3Eh, 15). GPIO Interrupt Controller sections details interrupt status readback these MICBIAS current detection features. REGISTER ADDRESS LABEL MCDTHR DEFAULT DESCRIPTION current detect threshold 000:100uA 001:200uA .100uA steps 111:800uA These values 3.3V supply scale with supply voltage (AVDD). current detect short circuit threshold 600uA 1200uA 1800uA 2400uA These values 3.3V supply scale with supply voltage (AVDD).
MCDSCTR
Table Microphone Current Detect Control
June 2006
WM9714L
MICROPHONE PGAS
Pre-Production
microphone pre-amps drive into microphone PGAs whose gain controlled register 0Eh. signals routed into headphone mixers mono mixer, speaker mixer prevent forming feedback loop) controlled register 10h. When signals selected input mixers outputs PGAs muted automatically. When microphone PGAs powered down using Powerdown register bits (register 3Eh, bits [3:2]). REGISTER ADDRESS Volume 12:8 LABEL MICAVOL DEFAULT 01000 (0dB) DESCRIPTION MICA input gain 00000: +12dB (1.5dB steps) 11111: -34.5dB MICB input gain 00000: +12dB (1.5dB steps) 11111: -34.5dB
MICBVOL
01000 (0dB)
Table Microphone Volume Control REGISTER ADDRESS Routing LABEL MA2M MB2M MIC2MBST MIC2H DEFAULT DESCRIPTION Mute MICA path mono mixer Mute, mute (ON) Mute MICB path mono mixer Mute, mute (ON) mono mixer boost 0dB, +20dB headphone mixers select Stereo (MICA HPL, MICB HPR) MICA only (MICA HPR) MICB only (MICB HPR) none (mutes microphone PGAs) headphone mixers gain 000: +6dB (3dB steps) 111: -15dB
MIC2HVOL
(0dB)
Table Microphone Routing Control
MONOIN INPUT
(MONOIN) mono input designed connect receive path telephony device.The connects directly record selector phone call recording (Note: record both sides phone call, channel should record MONOIN signal while other channel records signal). record adjusts recording volume, controlled register function (see "Record Gain" "Automatic Level Control" sections).
June 2006
Pre-Production REGISTER ADDRESS Record Routing 15:14 LABEL DEFAULT (mute)
WM9714L
Controls record headphone mixer paths. 00=stereo 01=left only 10=right only 11=mute left right Controls gain record headphone mixer paths 000: +6dB (3dB steps) 111: -15dB Controls record mono mixer path. 00=stereo 01=left only 10=right only 11=mute left right Enables 20dB gain boost record mono mixer path
13:11
R2HVOL
(0dB)
10:9
(mute)
R2MBST
(OFF)
Table Record Routing Control listen MONOIN signal, signal passes through separate PGA, controlled register 08h. signal routed into headphone mixer (for normal phone call operation) and/or speaker mixer (for speakerphone operation), into mono mixer prevent forming feedback loop). When signal selected input mixers output muted automatically. When MONOIN powered down using Powerdown register MOIN (register 3Eh, MONOIN biased internally reference voltage VREF. Whenever input muted device placed into standby mode, input remains biased VREF using special anti-thump circuitry suppress audible clicks when changing inputs. REGISTER ADDRESS MONOIN Routing 12:8 LABEL MONOIN DEFAULT 01000 (0dB) DESCRIPTION Mute MONIN path headphone mixer Mute, mute (ON) Mute MONOIN path speaker mixer Mute, mute (ON) MONOIN input gain 00000: +12dB (1.5dB steps) 11111: -34.5dB
Table Mono Control
PCBEEP INPUT
(PCBEEP) mono, line level input intended externally generated signal warning tones. routed directly record selector three output mixers, without input amplifier. signal gain into each mixer independently controlled, with separate mute each signal path. PCBEEP biased internally reference voltage VREF. When signal selected input mixers input remains biased VREF using special anti-thump circuitry suppress audible clicks when changing inputs.
June 2006
WM9714L
REGISTER ADDRESS PCBEEP input 14:12 LABEL B2HVOL DEFAULT (0dB)
Pre-Production
Mute PCBEEP path headphone mixer Mute, mute (ON) PCBEEP headphone mixer gain 000: +6dB (3dB steps) 111: -15dB Mute PCBEEP path speaker mixer Mute, mute (ON) PCBEEP speaker mixer gain 000: +6dB (3dB steps) 111: -15dB Mute PCBEEP path mono mixer Mute, mute (ON) PCBEEP mono mixer gain 000: +6dB (3dB steps) 111: -15dB
10:8
B2SVOL
(0dB)
B2MVOL
(0dB)
Table PCBEEP Control
DIFFERENTIAL MONO INPUT
PCBEEP MONOIN inputs configured provide differential mono input. This achieved mixing inputs together using headphone mixers speaker mixer. Note that gain MONOIN must match gain PCBEEP mixer input achieve balanced differential mono input.
June 2006
Pre-Production
WM9714L
AUDIO MIXERS
MIXER OVERVIEW
WM9714L four separate low-power audio mixers cover audio functions required smartphones, PDAs handheld computers. These mixers used drive audio outputs HPL, HPR, MONO, SPKL, SPKR, OUT3 OUT4. There also inverters used provide differential output signals (e.g. driving loads)
HEADPHONE MIXERS
There headphone mixers, headphone mixer left headphone mixer right (HPMIXL HPMIXR). These mixers stereo output driver source. They used drive stereo outputs HPR. They also used drive SPKL SPKR outputs and, when used conjunction with OUT3 OUT4, they configured drive complementary signals through output inverters support bridge-tied load (BTL) stereo loudspeaker outputs. following signals mixed into headphone path: MONOIN (controlled register 08h, "Audio Inputs") LINEL/R (controlled register 0Ah, "Audio Inputs") output Record (controlled register 14h, "Audio ADC", "Record Gain") stereo signal (controlled register 0Ch, "Audio DACs") signal (controlled register 10h, "Audio Inputs") PC_BEEP (controlled register 16h, "Audio Inputs") VXDAC signal (controlled register 18h, "Audio DACs") AUXDAC signal (controlled register 1Ah, "Auxiliary DAC")
typical smartphone application, headphone signal MONOIN VXDAC sidetone (for phone calls) stereo signal (for music playback). When headphone mixers powered down using Powerdown register bits HPLX HPRX (register 3Ch, bits [3:2]).
SPEAKER MIXER
speaker mixer (SPKMIX) mono source. typically used drive mono loudspeaker configuration. following signals mixed into speaker path: MONOIN (controlled register 08h, "Audio Inputs") LINEL/R (controlled register 0Ah, "Audio Inputs") stereo signal (controlled register 0Ch, "Audio DACs") PC_BEEP (controlled register 16h, "Audio Inputs") VXDAC signal (controlled register 18h, "Audio DACs") AUXDAC signal (controlled register 1Ah, "Auxiliary DAC")
typical smartphone application, speaker signal AUXDAC (for system alerts ring tone playback), MONOIN VXDAC (for speakerphone function), PC_BEEP (for externally generated ring tones). Note that when selected stereo input pairs LINEL/R DACL/R summed attenuated -6dB that 0dBFS signals each channel give 0dBFS mono signal. When speaker mixer powered down using Powerdown register SPKX (register 3Ch,
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MONO MIXER
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mono mixer drives MONO pin. following signals mixed into MONO: LINEL/R (controlled register 0Ah, "Audio Inputs") output Record (controlled register 14h, "Audio ADC", "Record Gain") stereo signal (controlled register 0Ch, "Audio DACs") signal (controlled register 10h, "Audio Inputs") PC_BEEP (controlled register 16h, "Audio Inputs") VXDAC signal (controlled register 18h, "Audio DACs") AUXDAC signal (controlled register 12h, "Auxiliary DAC")
typical smartphone application, MONO signal amplified microphone signal (possibly with Automatic Gain Control) enabled) audio playback signal from stereo auxiliary DAC. Note that when selected stereo input pairs LINEL/R DACL/R summed attenuated -6dB that 0dBFS signals each channel give 0dBFS mono signal. When mono mixer powered down using Powerdown register (register 3Ch,
MIXER OUTPUT INVERTERS
There general purpose mixer output inverters, INV1 INV2. Each inverter selected drive HPMIXL, HPMIXR, SPKMIX, MONOMIX HPMIXL HPMIXR outputs inverters used generate complimentary signals drive configured loads) provide greater flexibility output driver configurations. INV1 selected source SPKL, MONO OUT3 INV2 source SPKR OUT4. input source each inverter selected using INV1[2:0] INV2[2:0] register (see Table 31). When input selected inverter powered down. REGISTER ADDRESS 15:13 LABEL INV1 DEFAULT (OFF) DESCRIPTION INV1 source select 000: (OFF source selected) 001: MONOMIX 010: SPKMIX 011: HPMIXL 100: HPMIXR 101: HPMIXMONO 110: unused 111: Vmid INV2 source select Same INV1
12:10
INV2
(OFF)
Table Mixer Inverter Source Select
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WM9714L
ANALOGUE AUDIO OUTPUTS
following sections give overview analogue audio output pins. WM9714L three outputs capable driving loads down (headphone line drivers) HPL, MONO four outputs capable driving loads down (loudspeaker line drivers) SPKL, SPKR, OUT3 OUT4. combination output drivers, mixers mixer inverters means that many output configurations supported. examples typical output mixer configurations please refer "Typical Output Configuration" section. more information recommended external components, please refer "Applications Information" section. Each output driven with gain range -46.5dB -1.5dB steps. Each input source mux, mute zero-cross detect circuit (delaying gain changes until zero-cross detected, after time-out).
HEADPHONE OUTPUTS
outputs (pins designed drive headphone load. They also used line outputs. They used coupled coupled (capless) configuration. available input sources HPMIXL/R Vmid (see Table 32). REGISTER ADDRESS Output Select LABEL DEFAULT (Vmid) DESCRIPTION input source select Vmid input (tri-stated HPL=1 register 3Eh) HPMIXL unused input source select Vmid input (tri-stated HPR=1 register 3Eh) HPMIXR unused
(Vmid)
Table Input Source signal volume independently adjusted under software control writing register 04h. When powered down using Powerdown register bits (register 3Eh, bits [10:9]). minimise pops clicks when powered down recommended that Vmid input selected during power down cycle. This ensures same level maintained output throughout.
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REGISTER ADDRESS Headphone Volume LABEL DEFAULT (Mute)
Pre-Production DESCRIPTION Mute Mute (OFF) Mute (ON) Left zero cross enable Change gain immediately Change gain only zero crossings, after time-out Volume 000000: (maximum) 000001: -1.5dB (1.5dB steps) 011111: -46.5dB 1xxxxx: -46.5dB Mute Mute (OFF) Mute (ON) Right zero cross enable Change gain immediately Change gain only zero crossings, after time-out Volume Similar HPLVOL
13:8
HPLVOL
000000 (0dB)
(Mute)
HPRVOL
000000 (0dB)
Table Control
MONO OUTPUT
MONO output (pin designed drive headphone load also used line output. available input sources MONOMIX, INV1 Vmid (see Table REGISTER ADDRESS Output Select 15:14 LABEL MONO DEFAULT (Vmid) DESCRIPTION MONO input source select Vmid input (tri-stated MONO=1 register 3Eh) MONOMIX INV1
Table MONO Input Source signal volume MONO independently adjusted under software control writing register 08h. When MONO powered down using Powerdown register MONO (register 3Eh, 13). minimise pops clicks when powered down recommended that Vmid input selected during power down cycle. This ensures same level maintained output throughout.
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Pre-Production REGISTER ADDRESS MONO LABEL DEFAULT (Mute)
WM9714L
DESCRIPTION Mute MONO Mute (OFF) Mute (ON) Right zero cross enable Change gain immediately Change gain only zero crossings, after time-out MONO Volume 000000: (maximum) 000001: -1.5dB (1.5dB steps) 011111: -46.5dB 1xxxxx: -46.5dB
MONOVOL
000000 (0dB)
Table Mono Control
SPEAKER OUTPUTS SPKL SPKR
SPKL SPKR (pins designed drive loudspeaker load down also used line outputs headphone outputs. They designed drive load coupled (capless) configuration. available input sources HPMIXL/R, SPKMIXL/R, INV1/2 Vmid (see Table 36). REGISTER ADDRESS Output Select 13:11 LABEL SPKL DEFAULT (Vmid) DESCRIPTION SPKL input source select 000: Vmid 001: input (tri-stated SPKL=1 register 3Eh) 010: HPMIXL 011: SPKMIX 100: INV1 101-111: unused SPKR input source select 000: Vmid 001: input (tri-stated SPKR=1 register 3Eh) 010: HPMIXR 011: SPKMIX 100: INV2 101-111: unused
10:8
SPKR
(Vmid)
Table SPKL SPKR Input Source signal volume SPKL SPKR independently adjusted under software control writing register 02h. When SPKL SPKR powered down using Powerdown register bits SPKL SPKR (register 3Eh, bits [8:7]). minimise pops clicks when powered down recommended that Vmid input selected during power down cycle. This ensures same level maintained output throughout.
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REGISTER ADDRESS Speaker Volume LABEL DEFAULT (Mute)
Pre-Production DESCRIPTION Mute SPKL Mute (OFF) Mute (ON) Left zero cross enable Change gain immediately Change gain only zero crossings, after time-out SPKL Volume 000000: (maximum) 000001: -1.5dB (1.5dB steps) 011111: -46.5dB 1xxxxx: -46.5dB Mute SPKR Mute (OFF) Mute (ON) Right zero cross enable Change gain immediately Change gain only zero crossings, after time-out SPKR Volume Similar SPKLVOL
13:8
SPKLVOL
000000 (0dB)
(Mute)
SPKRVOL
000000 (0dB)
Table SPKL SPKR Control Note: speaker drive, recommended that both PGAs have same gain setting.
AUXILIARY OUTPUTS OUT3 OUT4
OUT3 OUT4 outputs (pins designed drive loudspeaker load down also used line outputs headphone outputs. They designed drive load coupled (capless) configuration used midrail buffer drive headphone outputs capless configuration. available input sources INV1/2 Vmid (see Table 38). REGISTER ADDRESS Output Select LABEL OUT3 DEFAULT (Vmid) DESCRIPTION OUT3 input source select Vmid buffer disabled) INV1 unused OUT4 input source select Vmid buffer disabled) INV2 unused
OUT4
(Vmid)
Table OUT3 OUT4 Input Source signal volume OUT3 OUT4 independently adjusted under software control writing register 06h. When OUT3 OUT4 powered down using Powerdown register bits OUT3 OUT4 (register 3Eh, bits [11:12]). minimise pops clicks when powered down recommended that Vmid input selected during power down cycle. This ensures same level maintained output throughout.
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WM9714L
DESCRIPTION Mute OUT4 Mute (OFF) Mute (ON) OUT4 zero cross enable Change gain immediately Change gain only zero crossings, after time-out OUT4 Volume 000000: (maximum) 000001: -1.5dB (1.5dB steps) 011111: -46.5dB 1xxxxx: -46.5dB Mute OUT3 Mute (OFF) Mute (ON) OUT3 zero cross enable Change gain immediately Change gain only zero crossings, after time-out OUT3 Volume Similar OUT4VOL
13:8
OUT4VOL
000000 (0dB)
(Mute)
OUT3VOL
000000 (0dB)
Table OUT3 OUT4 Control
THERMAL SENSOR
speaker headphone outputs drive very large currents. protect WM9714L from becoming hot, thermal sensor been built chip temperature reaches approximately 150°C, set, WM9714L deasserts GPIO register 54h, virtual GPIO that generate interrupt (see "GPIO Interrupt Control" section). REGISTER ADDRESS LABEL TSHUT DEFAULT DESCRIPTION Power down thermal sensor Enabled Disabled Thermal sensor (virtual GPIO) Temperature below 150°C Temperature above 150°C also "GPIO Interrupt Control" section.
Table Thermal Cutout Control
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JACK INSERTION AUTO-SWITCHING
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phone application, speaker connected across MONO HPL, stereo headphone stereo speakers SPKL, SPKR, OUT3 OUT4 (see Figure 15). Typically, only these three output devices used given time: when headphone plugged speaker stereo speakers active, otherwise headphone used.
Figure Typical Output Configuration presence headphone detected using GPIO1/6/7/8 (pins external pull-up resistor (see Figure page circuit diagram). When jack inserted, GPIO pulled switch socket. When jack removed GPIO pulled high resistor. JIEN set, WM9714L automatically switches between headphone other output configuration, typically speaker stereo speaker that been Powerdown Output Select registers. Note: Please refer WAN_0182 further information jack detect configuration addition typical configuration explained above, WM9714L also support automatic switching between following three configurations speaker headphone. REGISTER ADDRESS Output Volume Mapping (Jack Insert) LABEL EARSPKSEL DEFAULT DESCRIPTION Default, speaker configuration selected. MONO driver selected speaker. OUT3 driver selected speaker. OUT4 driver selected speaker.
Table Speaker Configuration example OUT4 selected speaker, user should select EARSPKSEL then OUT4 tri-stated jack insert prevent sound across speaker during headphone operation volume OUT4 volume jack ensure correct speaker operation. should noted that other outputs except HPL, selected speaker driver disabled internally connected VREF jack insert. This maintains VREF those outputs helps prevent pops when outputs enabled.
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Finally user wishes couple headphone outputs user needs select between OUT3 OUT4 mid-rail output buffer driver. selected mid-rail output buffer enabled jack insert. jack defaults whatever configuration been Powerdown Output Select registers.
REGISTER ADDRESS Output Volume Mapping (Jack Insert)
LABEL DCDRVSEL
DEFAULT
DESCRIPTION Default, coupled headphone. OUT4 mid-rail output buffer. OUT3 mid-rail output buffer.
Table Coupled Headphone Configuration summary: JIEN set: Outputs work normal selected Powerdown Output Select registers. JIEN set: jack insert GPIO1/6/7/8 pulled low, enabled, DCDRVSEL decides headphones coupled configures OUT3 OUT4 suit, EARSPKSEL decides MONO, OUT3 OUT4 need tri-stated ensure sound ear-speaker finally other outputs disabled explained above prevent pops re-enabling. jack GPIO1/6/7/8 pulled high, outputs work normal selected Powerdown Output Select registers except that Volume controlled EARSPKSEL ensure correct speaker operation.
REGISTER ADDRESS Output Volume Mapping (Jack Insert) Additional Functions
LABEL JIEN
DEFAULT (OFF)
DESCRIPTION Jack Insert Enable Takes output GPIO1 logic
JSEL
(GPIO1)
GPIO select jack insert detection: GPIO1 GPIO6 GPIO7 GPIO8
Table Jack Insertion Auto-Switching
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VOLUME
MONO STATE
VOLUME
MODE DESCRIPTION GPIO1
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled User Controlled User Controlled
Jack Insert Detection Enabled. Headphone plugged Speaker Selected. Coupled Headphone Selected. Jack Insert Detection Enabled. Headphone plugged MONO Speaker Selected. Coupled Headphone Selected. Jack Insert Detection Enabled. Headphone plugged OUT3 Speaker Selected. Coupled Headphone Selected. Jack Insert Detection Enabled. Headphone plugged OUT4 Speaker Selected. Coupled Headphone Selected. Jack Insert Detection Enabled. Headphone plugged OUT4 Speaker Selected. OUT3 Coupled Headphone Selected. Jack Insert Detection Enabled. Headphone plugged out. Speaker Selected. Jack Insert Detection Enabled. Headphone plugged out. OUT4 Speaker Selected.
Volume
Volume
Enabled
Enabled
Volume
Volume
Tri-Stated
Enabled
Enabled
Volume
Volume
Tri-Stated
Enabled
Enabled
Volume
Volume
Tri-Stated
Enabled
Enabled
Volume
Volume
Tri-Stated
Enabled
Enabled
VMID
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
User Controlled
Table Jack Insertion Auto-Switching
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User Controlled
OUT4 Volume
User Controlled
User Controlled
Jack Insert Detection Disabled.
SPKR STATE
SPKL STATE
OUT3 STATE
OUT4 STATE
EARSPKSEL
STATE
STATE
DCDRVSEL
JIEN
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DIGITAL AUDIO (SPDIF) OUTPUT
WM9714L supports SPDIF standard. Pins used output SPDIF data. Note that pins also used GPIO pins. bits (register 56h, select between GPIO SPDIF functionality pins respectively (see "GPIO Interrupt control" section). Register read/write register that controls SPDIF functionality manages fields propagated channel status sub-frame case). With exception this register should only written when SPDIF transmitter disabled (SPDIF register `0'). Once desired values have been written this register, contents should read back ensure that sample rate particular supported, then SPDIF validity SPCV register should read ensure desired configuration valid. Only then should SPDIF enable register set. This ensures that control status information start correctly beginning SPDIF transmission. REGISTER ADDRESS Extended Audio LABEL SPCV SPSA DEFAULT DESCRIPTION SPDIF validity (read-only) SPDIF slot assignment (ADCO Slots Slots Slots Slots SPDIF output enable enabled, disabled Validity bit; indicates frame valid, indicates frame valid Indicates that WM9714L does support double rate SPDIF output (read-only) Indicates that WM9714L only supports 48kHz sampling SPDIF output (readonly) Generation level; programmed required user Category code; programmed required user Pre-emphasis; indicates pre-emphasis, indicates 50/15us pre-emphasis Copyright; indicates copyright asserted, indicates copyright Non-audio; indicates data PCM, indicates non-PCM format (e.g. DTS) Professional; indicates consumer, indicates professional Source SPDIF data SPDIF data comes from SDATAOUT (pin slot selected SPSA SPDIF data comes from audio
SPDIF Control Register 13:12
SPSR
10:4 Additional Function Control
COPY AUDIB ADCO
0000000
Table SPDIF Output Control
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WM9714L AUXILIARY
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WM9714L includes very power, 12-bit successive approximation type which used battery auxiliary measurements. Three pins that used auxiliary inputs: MIC2A COMP1 AUX1 (pin MIC2B COMP2 AUX2 (pin AUX4 (pin
Pins also used comparator inputs (see "Battery Alarm Analogue Comparators"), auxiliary measurements still taken these pins time. Additionally, speaker supply (SPKVDD) used auxillary input through onchip potential divider giving input auxillary SPKVDD/3. This input referred AUX3 input.
Figure Auxiliary Inputs accessed controlled through AC-Link interface.
AUXADC POWER MANAGEMENT
save power, AUXADC independently disabled when used. AUXADC powered-down using PADCPD, register state controlled following bits. REGISTER ADDRESS 15:14 LABEL PADCPD DEFAULT DESCRIPTION power down Additional enable AUXADC USED USED
Table AUXADC Power Management
INITIATION MEASUREMENTS
WM9714L interface supports both polling routines (direct memory access) control flow data from host CPU.
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polling routine, starts each measurement individually writing POLL (register 74h, This automatically resets itself when measurement completed. REGISTER ADDRESS LABEL POLL DEFAULT DESCRIPTION Writing initiates measurement. (when set) Polling mode Continuous mode (for DMA) Continuous mode rate (DEL 1111) 93.75 (every AC-Link frames) (every AC-Link frames) 153.75 (every AC-Link frames) 187.5Hz (every AC-Link frames) Continuous mode "fast rate" (DEL 1111) (every AC-Link frames) (every four AC-Link frames) (every other AC-Link frame) (every AC-Link frame)
Table Control (Initiation Measurements) continuous mode (CTC WM9714L autonomously initiates measurements sets measurements) rate supplies measured data unused AC'97 time slots. DMA-enabled CPUs write data directly into FIFO without intervention core. This reduces loading speeds execution user programs handheld systems. Note that measurement frequency continuous mode also affected bits. faster rates achieved when 1111 useful when used multiple measurements.
MEASUREMENT TYPES
ADCSEL control bits determine which type measurement performed (see below). REGISTER ADDRESS POLL LABEL DEFAULT DESCRIPTION Writing initiates measurement. (when set) ADCSEL_AUX4 Polling mode Continuous mode (for DMA) Enable COMP1/AUX4 measurement (pin32). Only bits[7:4] should set. Enable COMP1/AUX3 measurement (pin31) Only bits[7:4] should set. Enable COMP1/AUX2 measurement (pin30) Only bits[7:4] should set. Enable COMP1/AUX1 measurement (pin29) Only bits[7:4] should set.
ADCSEL_AUX3
ADCSEL_AUX2
ADCSEL_AUX1
Table Control (Measurement Types) WM9714L performs single measurement either polling mode continuously, indicated bit. type measurement specified ADCSEL[7:4] bits. Only ADCSEL[7:4] bits should set.
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CONVERSION RATE
AUXADC conversion rate specified bits (reg 76h).
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93.75Hz (every AC-Link Frames), 120Hz (every AC-Link Frames), 153.75Hz (every AC-Link frames) 187.5Hz (every AC-Link frames). only ADRSEL[7:1] then each individual conversion occurs rate specified multiple ADRSEL[7:1] bits then complete conversions requested completed rate specified
DATA READBACK
AUXADC measured data stored register 7Ah, retrieved reading register usual manner (see AC-Link Interface section). Additionally, data also passed controller AC-Link time slots used audio functions. output data word interface consists three parts: Unused (Ignore). Output data from bits) ADCSRC: additional bits that indicate source data.
data being read back using polling method, there several ways determine when measurement finished: Reading back POLL bit. been reset `0', then measurement finished. Monitoring signal, GPIO interrupt section. goes high after every single conversion. Reading back until data appears
REGISTER ADDRESS AC-Link slot selected
14:12
LABEL ADCSRC
DEFAULT
DESCRIPTION Source 000: measurement 001: used 010: used 011: used 100: COMP1/AUX1 measurement (pin 101: COMP2/AUX2 measurement (pin 110: BMON/AUX3 measurement (pin 111: used Data (read-only) effect (new data overwrites unread data register 7Ah) data held back, measurements delayed, until register read)
11:0
ADCD
000h
WAIT
Table Data avoid losing data that been read, WM9714L delay overwriting register with conversions until data been read. This function enabled using WAIT bit. SLEN `1', then data appears AC-Link slot selected control
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bits, shown below. Slot `tag' corresponding selected time slot asserted whenever there data that slot. REGISTER ADDRESS LABEL SLEN DEFAULT DESCRIPTION Slot Readback Enable Disabled (readback through register only) Enable (readback slot selected SLT) AC'97 Slot Selection Data 000: Slot 001: Slot 101: Slot 110: Slot 111: RESERVED
Table Returning Data Through AC-Link Time Slot
MASK INPUT CONTROL
Sources glitch noise, such signals driving display, feed through inputs affect measurement accuracy. order minimise this effect, signal applied MASK (pin delay synchronise sampling input ADC. effect MASK signal depends bits register (bits [7:6]), described below. REGISTER ADDRESS LABEL DEFAULT DESCRIPTION MASK input control (see
Table MASK Input Control MSK[1-0] EFFECT SIGNAL MASK Mask effect conversions GPIO input disabled (default) Static; `hi' MASK stops conversions, `lo' effect. Edge triggered; rising falling edge MASK delays conversions amount DEL[3-0] register. Conversions asynchronous MASK signal. Synchronous mode; conversions wait until rising falling edge MASK initiates cycle; screen starts driven when edge arrives, conversion sample being taken period DEL[3-0] after edge.
Table Controlling MASK Feature Note that also used GPIO(see "GPIO Interrupt Control" section), output signal (see below).
SIGNAL
Whenever data becomes available from ADC, internal (ADC Data Available) signal goes high remains high until data been read from register SLEN until been sent AC-Link slot SLEN goes high after every conversion normal mode, COO=0) used generate interrupt, (register 52h, (see "GPIO interrupt control" section) also possible output signal this used GPIO. GE4/6 must achieve this (see "GPIO interrupt control" section). Alternatively, read from register 54h.
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WM9714L ADDITIONAL FEATURES
BATTERY ALARM ANALOGUE COMPARATORS
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battery alarm function differs from battery measurement that does actually measure battery voltage. Battery alarm only indicates "OK", "Low" "Dead". advantage battery alarm function that does require clock therefore used low-power sleep standby modes.
Figure Battery Alarm Example Schematic typical schematic dual threshold battery alarm shown above. This alarm thresholds, "dead battery" (COMP1) "low battery" (COMP2). threshold voltages. Their values about order keep battery current [IALARM VBATT (R1+R2+R3)] minimum (higher resistor values affect accuracy system leakage currents into input pins become significant). Dead battery alarm: COMP1 triggers when VBATT VREF (R1+R2+R3) (R2+R3) dead battery alarm highest priority interrupt system. should immediately save unsaved data shut down system. GP15, GS15 GW15 bits must generate this interrupt. battery alarm: COMP2 triggers when VBATT VREF (R1+R2+R3) battery alarm lower priority than dead battery alarm. Since threshold voltage higher than dead battery alarm, there enough power left battery give user warning and/or shut down "gracefully". When VBATT gets close battery threshold, spurious alarms filtered COMP2 delay function. purpose capacitor remove from comparator inputs high frequency noise glitches that present battery (for example, noise generated charge pump). forms pass filter with pass cutoff [Hz] (R2+R3))) Provided that cutoff frequency several orders magnitude lower than noise frequency this simple circuit achieve excellent noise rejection. Noise rejection [dB] circuit shown above also allows measuring battery voltage VBATT. This achieved simply setting AUXADC input either COMP1 (ADCSEL 100) COMP2 (ADCSEL 101) (see also Auxiliary Inputs). WM9714L on-chip comparators that used implement battery alarm function, other functions such window comparator. Each comparator inputs tied COMP1 (pin COMP2 (pin 30), other tied voltage reference. voltage reference either internally generated (VREF AVDD/2) externally connected AUX4 (pin 12).
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comparator output signals passed GPIO logic block (see "GPIO Interrupt Control" section), where they used send interrupt AC-Link pin, wake WM9714L from sleep mode. COMP1/AUX1 (pin corresponds GPIO COMP2/AUX2 (pin30) REGISTER ADDRESS LABEL DEFAULT DESCRIPTION COMP1 Polarity (see also "GPIO Interrupt Control") Alarm when COMP1 voltage below VREF Alarm when COMP1 voltage above VREF COMP2 Polarity (see also "GPIO Interrupt Control") Alarm when COMP2 voltage below VREF Alarm when COMP2 voltage above VREF Battery Alarm Delay 000: delay 001: 0.17s (213 8192 AC-Link frames) 010: 0.34s (214 16384 AC-Link frames) 011: 0.68s (215 32768 AC-Link frames) 100: 1.4s (216 65536 AC-Link frames) 101: 2.7s (217 131072 AC-Link frames) 110: 5.5s (218 262144 AC-Link frames) 111: 10.9s (219 524288 AC-Link frames)
15:13
COMP2
Table Comparator Control REGISTER ADDRESS Additional Analogue Functions LABEL C1REF DEFAULT DESCRIPTION Comparator Reference Voltage 13:12 C1SRC C2REF 10:9 C2SRC Table Comparator Reference Source Control VREF AVDD/2 WIPER/AUX4 (pin AVDD/2 when C1REF='1'. Otherwise comparator powered down COMP1/AUX1 (pin COMP2/AUX2 (pin Reserved VREF AVDD/2 WIPER/AUX4 (pin AVDD/2 when C2REF='1'. Otherwise comparator powered down COMP1/AUX1 (pin COMP2/AUX2 (pin Reserved
Comparator Signal Source
Comparator Reference Voltage
Comparator Signal Source
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COMP2 DELAY FUNCTION
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COMP2 optional delay function when input signal noisy. When COMP2 triggers delay enabled (i.e. COMP2DEL non-zero), then GPIO does change state immediately, interrupt generated. Instead, WM9714L starts delay timer checks COMP2 again after delay time passed. COMP2 still active, then GPIO interrupt generated (depending state GW14 bit). COMP2 longer active, GPIO set, i.e. register bits COMP2 never triggered.
COMP2 TRIGGERS
C2W?
COMP2 DEL?
non-zero
START TIMER
WAIT time=COMP2DEL SHUT DOWN TIMER
COMP2?
Inactive
[FALSE ALARM]
Active
GI14
Figure COMP2 Delay Flow Chart
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GPIO INTERRUPT CONTROL
WM9714L eight GPIO pins that operate defined AC'97 Revision specification. Each GPIO input output, corresponding bits register slot state GPIO output determined sending data through slot outgoing frames (SDATAOUT). Data returned from GPIO input reading register bit, examining slot incoming frames (SDATAIN). GPIO inputs made sticky, programmed generate interrupt, transmitted either through AC-Link through dedicated, level-mode interrupt (GPIO2/IRQ, 45). addition, GPIO pins used interface setting register (see "PCM Codec" section). Setting this disables GPIO functions selected these pins. REGISTER ADDRESS Codec Control LABEL CTRL DEFAULT DESCRIPTION Enables interface GPIO pins Normal GPIO functions interface enabled Note: interface, more these pins (depending master/slave/partial master mode) must output writing register (see Table Toggle GPIO function: secondary function enabled GPIO enabled
GPIO Sharing
(GPIO)
Table GPIO Additional Function Control GPIO pins multi-purpose pins that also used other (non-GPIO -PCM) purposes, e.g. SPDIF output. This controlled register (see Table Note that GPIO6/7/8 each have additional function independent GPIO auxillary functions discussed above. these pins used GPIO then independent function needs disabled using control registers, e.g. GPIO then RESETB function needs disabled (RSTDIS, register 5Ah, Independently GPIO pins, WM9714L also seven virtual GPIOs. These signals from inside WM9714L, which treated they were GPIO input signals. From software perspective, virtual GPIOs same GPIO pins, they cannot outputs, tied actual pin. This allows simple, uniform processing different types signals that generate interrupts (e.g. battery warnings, jack insertion, high-temperature warning, GPIO signals).
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Figure GPIO Logic GPIO SLOT TYPE GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Virtual GPIO Virtual GPIO Virtual GPIO Virtual GPIO Virtual GPIO Virtual GPIO [MICDET] [MICSHT] [Thermal Cutout] [ADA] [COMP2] [COMP1] GPIO1 GPIO2 enabled only when used GPIO3 GPIO4 MASK enabled only when used GPIO5 SPDIF_OUT enabled only when used SPDIF_OUT GPIO6 MASK Enabled only when used GPIO7 GPIO8 SPDIF_OUT enabled only when used SPDIF_OUT Internal microphone bias current detect, generates interrupt above threshold (see MICBIAS Current Detect) Internal shorted microphone detect, generates interrupt above threshold (see MICBIAS Current Detect) Internal thermal cutout signal, indicates when internal temperature reaches approximately 150°C (see "Thermal Sensor") Internal (ADC Data Available) Signal enabled only when AUXADC active Internal COMP2 output (Low Battery Alarm) enabled only when COMP2 Internal COMP1 output (Dead Battery Alarm) enabled only when COMP1
Table GPIO Bits Pins Note: GPIO7 (Pin independent RESETB function. This must disabled using RSTDIS (Register 5Ah, before using GPIO.
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properties GPIOs controlled through registers 52h, shown below. REGISTER ADDRESS LABEL DEFAULT DESCRIPTION GPIO Configuration Output Input GC9-15 always GPIO Polarity Type Input (GCn=1) Active Active High [GIn level XNOR GPn] GPIO Sticky Sticky Sticky GPIO Wake-up Wake (generate interrupts from this pin) wake-up interrupts generated) GPIO Status Read: Returns status each GPIO Write: Writing clears sticky Output (GCn=0) Active High Active
Table GPIO Control following procedure recommended handling interrupts: When controller receives interrupt, check register 54h. each GPIO descending order priority, check `1'. yes, execute corresponding interrupt routine, then write corresponding 54h. continue next lower priority GPIO. After GPIOs have been checked, check interrupt still present yes, repeat procedure. then jump back process that before interrupt. system cannot execute such interrupt routine, preferable switch internal signals directly onto GPIO pins. However, this case interrupt signals cannot made sticky, more GPIO pins tied both WM9714L CPU.
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REGISTER ADDRESS GPIO pins function select LABEL DEFAULT
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GPIO2 output select disconnected from GPIO logic 4Ch, output signal connected GPIO logic (IRQ disabled) GPIO4 MASK output select disconnected from GPIO logic 4Ch, output signal 4Ch, input MASK signal connected GPIO logic GPIO5 SPDIF output select SPDIF (disconnected from GPIO logic) 4Ch, output SPDIF signal connected GPIO logic (SPDIF disabled) GPIO6 MASK output select disconnected from GPIO logic 4Ch, output signal 4Ch, input MASK signal connected GPIO logic GPIO8 SPDIF output select SPDIF (disconnected from GPIO logic) 4Ch, output SPDIF signal connected GPIO logic (SPDIF disabled)
Table Using GPIO Pins Non-GPIO Functions
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WM9714L
POWER MANAGEMENT
INTRODUCTION
WM9714L includes standard power down control register defined AC'97 specification (register 26h). Additionally, also allows more specific control over individual blocks device through register Powerdown registers 3Eh. Each particular circuit block active when both relevant register relevant Powerdown registers `0'. Note that default power-up condition OFF.
AC97 CONTROL REGISTER
REGISTER ADDRESS Powerdown/ Status register LABEL DEFAULT (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) DESCRIPTION Disables output PGAS Disables internal clock Disables AC-link interface (external clock off) Disables VREF, input PGAs, DACs, ADCs, mixers outputs Disables input PGAs mixers Disables stereo Disables stereo ADCs record Read-only bit, indicates VREF ready (inverse PR3) Read-only bit, indicates analogue mixers ready (inverse PR2) Read-only bit, indicates stereo ready (inverse PR1) Read-only bit, indicates stereo ready (inverse PR0)
Table Powerdown Status Register (Conforms AC'97 2.2)
EXTENDED POWERDOWN REGISTERS
REGISTER ADDRESS Powerdown LABEL PADCPD VMID1M TSHUT VXDAC AUXDAC VREF DACL DACR ADCL ADCR HPLX HPRX SPKX DEFAULT (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) DESCRIPTION Disables AUXADC Disables 1Meg Vmid resistor string Disables thermal shutdown Disables VXDAC Disables AUXDAC Disables master bias reference generator Disables Disables left (see Note Disables right (see Note Disables left Disables right Disables left headphone mixer Disables right headphone mixer Disables speaker mixer Disables mono mixer
Note: When analogue inputs outputs disabled, they internally connected VREF through large resistor (VREF=AVDD/2 except when VREF VMID1M both OFF). This maintains potential that node helps eliminate pops when pins re-enabled. Table Extended Power Down Register (Additional AC'97 2.2) Note: When disabling PGA, always ensure that muted first. June 2006
WM9714L
REGISTER ADDRESS Powerdown LABEL MICBIA MONO OUT4 OUT3 SPKL SPKR MOIN DEFAULT (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) (OFF) (OFF)
Pre-Production
Disables microphone current detect Disables microphone bias Disables MONO output (see Note Disables OUT4 output Disables OUT3 output Disables output Disables output Disables SPKL output Disables SPKR output Disables LINEL Disables LINER Disables MONOIN Disables Disables Disables pre-amp Disables pre-amp
Note: When analogue inputs outputs disabled, they internally connected VREF through large resistor (VREF=AVDD/2 except when VREF VMID1M both OFF). This maintains potential that node helps eliminate pops when pins re-enabled. Table Extended Power Down Register (Additional AC'97 2.2) Note: When disabling PGA, always ensure that muted first.
ADDITIONAL POWER MANAGEMENT
Mixer output inverters: "Mixer output Inverters" section. Inverters default.
SLEEP MODE
Whenever (reg. 26h) set, AC-Link interface disabled, WM9714L sleep mode. There fact very large number different sleep modes, depending other control bits. example, low-power standby mode described below sleep mode. desirable sleep modes whenever possible, this will save power. following functions require clock therefore operate sleep mode: Analogue-to-analogue audio (DACs ADCs unused), e.g. phone call mode GPIO interrupts Battery alarm analogue comparators
WM9714L awake from sleep mode result warm reset AC-Link (according AC'97 specification) signal GPIO configured input, with wake-up enabled "GPIO Interrupt Control" section) virtual GPIO event such battery alarm, etc. (see "GPIO Interrupt Control" section)
June 2006
Pre-Production
WM9714L
POWER STANDBY MODE
bits registers 26h, except VMID1M (register 3Ch, 14), then WM9714L low-power standby mode consumes very little current. resistor string remains connected across AVDD generate VREF. This necessary on-chip analogue comparators used (see "Battery Alarm Battery Measurement" section), helps shorten delay between wake-up playback readiness. VREF required, resistor string disabled setting VMID1M bit, reducing current consumption further.
SAVING POWER SUPPLY VOLTAGES
analogue supplies WM9714L from 1.8V 3.6V. default, analogue circuitry optimized 3.3V. This set-up also good other supply voltages down 1.8V. However, lower voltages, possible save power reducing internal bias currents used analogue circuitry. This controlled shown below. REGISTER ADDRESS LABEL VBIAS DEFAULT DESCRIPTION Analogue Bias optimization Lowest bias current, optimized 1.8V bias current, optimized 2.5V Default bias current, optimized 3.3V
Table Analogue Bias Selection
POWER RESET (POR)
WM9714L internal power reset (PORB) which ensures that reset applied registers until supply threshold been exceeded. circuitry monitors voltage both AVDD DCVDD will release internal reset signal once these supplies both nominally greater than 1.36V. internal reset signal PORB RESETB input signal. recommended that operation WM9714L, device power rails should stable before configuring device operation.
AC97 INTERFACE TIMING
Test Characteristics: DBVDD 3.3V, DCVDD 3.3V, DGND1 DGND2 -25°C +85°C, unless otherwise stated.
CLOCK SPECIFICATIONS
tCLK_HIGH BITCLK tCLK_LOW
tCLK_PERIOD tSYNC_HIGH tSYNC_LOW
SYNC tSYNC_PERIOD
Figure Clock Specifications (50pF External Load)
June 2006
WM9714L
PARAMETER BITCLK frequency BITCLK period BITCLK output jitter BITCLK high pulse width (Note BITCLK pulse width (Note SYNC frequency SYNC period SYNC high pulse width SYNC pulse width Note: Worst case duty cycle restricted 45/55 tSYNC_PERIOD tSYNC_HIGH tSYNC_LOW tCLK_HIGH tCLK_LOW 40.7 40.7 20.8 19.5 tCLK_PERIOD SYMBOL 12.288 81.4
Pre-Production UNIT
DATA SETUP HOLD
Figure Data Setup Hold (50pF External Load) Note: Setup hold times SDATAIN with respect AC'97 controller, WM9714L. PARAMETER Setup falling edge BITCLK Hold from falling edge BITCLK Output valid delay from rising edge BITCLK SYMBOL tSETUP tHOLD UNIT
June 2006
Pre-Production
WM9714L
SIGNAL RISE FALL TIMES
triseCLK BITCLK triseSYNC SYNC triseDIN SDATAIN triseDOUT SDATAOUT tfallDOUT tfallDIN tfallSYNC tfallCLK
Figure Signal Rise Fall Times (50pF External Load)
PARAMETER BITCLK rise time BITCLK fall time SYNC rise time SYNC fall time SDATAIN rise time SDATAIN fall time SDATAOUT rise time SDATAOUT fall time
SYMBOL triseCLK tfallCLK triseSYNC tfallSYNC triseDIN tfallDIN triseDOUT tfallDOUT
UNIT
AC-LINK POWERDOWN
SLOT SYNC
SLOT
BITCLK
SDATAOUT
WRITE 0X20
DATA
DON'T CARE
tS2_PDOWN SDATAIN
Figure AC-Link Powerdown Timing AC-Link powerdown occurs when (register 26h, (see "Power Management" section). PARAMETER Slot BITCLK SDATAIN SYMBOL tS2_PDOWN UNIT
June 2006
WM9714L
COLD RESET (ASYNCHRONOUS, RESETS REGISTER SETTINGS)
Pre-Production
tRST_LOW RESETB
tRST2CLK
BITCLK
Figure Cold Reset Timing Note: correct operation SDATAOUT SYNC must held entire RESETB active period otherwise device enter test mode. AC'97 specification Wolfson applications note WAN104 more details. PARAMETER RESETB active pulse width RESETB inactive BITCLK startup delay SYMBOL tRST_LOW tRST2CLK 162.8 UNIT
WARM RESET (ASYNCHRONOUS, PRESERVES REGISTER SETTINGS)
Figure Warm Reset Timing
PARAMETER SYNC active high pulse width SYNC inactive BITCLK startup delay
SYMBOL tSYNC_HIGH tRST2CLK
162.4
UNIT
June 2006
Pre-Production
WM9714L
MONO INVA MPABST REV1 REV0 SPCV B2HVOL V2HVOL A2HVOL SPKL INVB BASS MPBBST AMAP LDAC
REGISTER
Reset Speaker Volume Headphone Volume OUT3/4 Volume MONO MONOIN Routing LINEIN Volume Routing Volume Routing Volume Routing Record Volume Record Routing Select PCBEEP Volume Routing VxDAC Volume Routing AUXDAC Volume Routing Output Select Control Select Tone Control Input Select Bias Detect Ctrl Output Volume Mapping (Jack Insert) Powerdown Ctrl/Stat Extended Audio Ext'd Audio Stat/Ctrl Audio DACs Sample Rate AUXDAC Sample Rate Audio ADCs Sample Rate codec control SPDIF control Powerdown Powerdown General Purpose Fast Power-Up Control MCLK Control MCLK Control GPIO Configuration GPIO Polarity Type GPIO Sticky GPIO Wake-Up GPIO Status GPIO Sharing GPIO Pull UP/DOWN Ctrl Additional Functions Additional Functions Control Noise Gate Control AUXDAC input control Digitiser Digitiser Digitiser Digitiser Read Back Vendor Vendor
AMUTE
Name
MB2M
Default
6174h 8080h 8080h 8080h C880h E808h E808h 0808h 00DAh 8000h D600h
SPKLVOL HPLVOL OUT4VOL MONOINVOL LINELVOL DACLVOL MICAVOL
SPKRVOL HPRVOL OUT3VOL MONOVOL MIC2MB MIC2H (Extended) RECSL B2MVOL V2MVOL A2MVOL OUT3 3DDEPTH TRBL MCDTHR JIEN SPSA DCDRVSEL SPDIF MCDSCTHR EARSPKSEL LINERVOL DACRVOL MICBVOL MIC2HVOL RECVOLR RECSR OUT4
MA2M
(Extended) R2HVOL
RECVOLL B2SVOL V2SVOL A2SVOL SPKR
AAA0h AAA0h AAA0h 0000h 0000h 0F0Fh 0040h 0000h 7F00h 0405h 0410h BB80h BB80h BB80h
3DLC 3DUC
MICCMPSEL
MPASEL
MBOP2E MBOP1E MBVOL SDAC CDAC
DACSR (Audio DACs Sample Rate) AUXDACSR (Auxiliary Sample Rate) ADCSR (Audio ADCs Sample Rate) CTRL MODE SPSR VREF VDACO (Category Code) SPKL DACL SPKR CLKSRC JSEL AMEN VBIAS (decay time) NGAT DACR MONO PGADDR ADCL SPKL ADCR MOIN SPKR PENDIV CLKBX2 N[3:0] COMP2DEL
COPY HPRX
SPKX OUT3 OUT4
4523h 2000h FDFFh FFFFh 0000h 0000h 0080h 0000h FFFEh FFFFh 0000h 0000h GPIO pins FFFEh 4000h 0000h 0000h B032h 3E00h 0000h
PADCPD VMID TSHUT BIAS MONO SEXT[6:4]
VXDAC AUXDAC OUT4 OUT3
HPLX
SEXT[3:0] C2SRC (hold time) DIVSEL DIVCTL RSTDIS
CLKAX2 CLKMUX PGDATA
C1SRC
HPMODE ADCO
Revision
WAKEE
ALCL (target level) ALCSEL XSLE MAXGAIN AUXDACSLT ADCSRC ASCII character ASCII character
(attack time) NGTH (threshold)
ZCTIMEOUT
AUXDAC WAIT POLL ADCSEL SLEN
0000h 0006h 0001h 0000h 574Dh 4C13h
ADCD (AUXADC DATA) ASCII character Device Identifier
Table WM9714L Register Note: Register provides access sub-page address system SPLL[6:0] K[21:0] register bits (see Table
June 2006
WM9714L
REGISTER BITS ADDRESS
REGISTER ADDRESS 14:10 LABEL [4:0] ID9:6 DEFAULT 11000 0101 DESCRIPTION Indicates codec from Wolfson Microelectronics Indicates bits resolution ADCs DACs Indicates that WM9714L supports bass boost Indicates that WM9714L headphone output Indicates that WM9714L does support simulated stereo Indicates that WM9714L supports bass treble control Indicates that WM9714L does support modem functions Indicates that WM9714L does have dedicated microphone
Pre-Production
REFER Intel's AC'97 Component Specification, Revision 2.2, page
Register read-only register. Writing value this register resets registers their default, does change contents reg. 00h. Reading register reveals information about codec driver, required AC'97 Specification, Revision
REGISTER ADDRESS
LABEL SPKLVOL SPKRVOL
DEFAULT (mute) (OFF) 000000 (0dB) (mute) (OFF) 000000 (0dB) Mutes SPKL
REFER Analogue Audio Outputs
Enables zero-cross detector SPKL SPKL volume Mutes SPKR Enables zero-cross detector SPKR SPKR volume
13:8
Register controls output pins SPKL SPKR.
REGISTER ADDRESS
LABEL
DEFAULT (mute) (OFF) 000000 (0dB) (mute) (OFF) 000000 (0dB) Mutes
REFER Analogue Audio Outputs
Enables zero-cross detector volume Mutes Enables zero-cross detector volume
13:8
Register controls headphone output pins, HPR.
REGISTER ADDRESS
LABEL OUT4VOL OUT3VOL
DEFAULT (mute) (OFF) 000000 (0dB) (mute) (OFF) 000000 (0dB) Mutes OUT4
REFER Analogue Audio Outputs
Enables zero-cross detector OUT4 volume Mutes OUT3 Enables zero-cross detector OUT3 volume
13:8
Register controls analogue output pins OUT3 OUT4.
June 2006
Pre-Production REGISTER ADDRESS 12:8 LABEL MONOINVOL MONOVOL DEFAULT (mute) (mute) 01000 (0dB) (mute) (OFF) 000000 (0dB) DESCRIPTION Mutes MONOIN headphone mixer paths Mutes MONOIN speaker mixer path Controls MONOIN input gain mixers (but ADC) Mutes MONO. Enables zero-cross detector MONO volume
WM9714L
REFER Analogue Inputs; Analogue Audio Outputs
Register controls analogue output MONO analogue input MONOIN.
REGISTER ADDRESS
LABEL LINELVOL LINERVOL
DEFAULT (mute) (mute) (mute) 01000 (0dB) 01000 (0dB)
DESCRIPTION Mutes LINE headphone mixer paths Mutes LINE speaker mixer path Mutes LINE mono mixer path Controls LINEL input gain mixers (but ADC) Controls LINER input gain mixers (but ADC)
REFER Analogue Inputs, Line Input
12:8
Register controls analogue input pins LINEL LINER.
REGISTER ADDRESS
LABEL DACLVOL DACRVOL
DEFAULT (mute) (mute) (mute) 01000 (0dB) 01000 (0dB)
DESCRIPTION Mutes headphone mixer path Mutes speaker mixer path Mutes mono mixer path Controls left input gain mixers Controls right input gain mixers
REFER Audio DACs
12:8
Register controls audio DACs (but AUXDAC).
REGISTER ADDRESS
12:8
LABEL MICAVOL MICBVOL
DEFAULT 01000 (0dB) 01000 (0dB)
DESCRIPTION Controls MICA volume Controls MICB volume
REFER Analogue Inputs, Microphone Input
Register controls microphone volume (MICA MICB).
REGISTER ADDRESS
LABEL MA2M MB2M MIC2MBST MIC2H
DEFAULT (mute) (mute) (OFF) (mute)
DESCRIPTION Mutes MICA mono mixer path Mutes MICB mono mixer path Enables 20dB gain boost mono mixer MICA MICB Controls microphone headphone mixer paths. 00=stereo, 01=MICA only, 10=MICB only, 11=mute MICA MICB Controls gain microphone headphone mixer path
REFER Analogue Inputs, Microphone Input
MIC2HVOL
(0dB)
Register controls microphone routing (MICA MICB).
June 2006
WM9714L
REGISTER ADDRESS LABEL DEFAULT (mute) (standard) DESCRIPTION Mutes audio input Selects gain range left ADC. 0=0.+22.5dB 1.5dB steps, 1=-17.25.+30dB 0.75dB steps Controls left recording volume Enables zero-cross detector Selects gain range right ADC. 0=0.+22.5dB 1.5dB steps, 1=-17.25.+30dB 0.75dB steps Controls right recording volume
Pre-Production REFER Audio ADC, Record Gain
13:8
RECVOLL
000000 (0dB) (OFF) (standard)
RECVOLR
000000 (0dB)
Register controls record volume.
REGISTER ADDRESS
15:14
LABEL
DEFAULT (mute)
DESCRIPTION Controls record headphone mixer paths. 00=stereo, 01=left only, 10=right only, 11=mute left right Controls gain record headphone mixer paths Controls record mono mixer path. 00=stereo, 01=left only, 10=right only, 11=mute left right Enables 20dB gain boost record mono mixer path Enables 20dB gain boost record path Selects left record signal source: 000=MICA, 001=MICB, 010=LINEL, 011=MONOIN, 100=HPMIXL, 101=SPKMIC, 110=MONOMIX, 111=Reserved use) Selects right record signal source: 000=MICA, 001=MICB, 010=LINER, 011=MONOIN, 100=HPMIXR, 101=SPKMIC, 110=MONOMIX, 111=Reserved use)
REFER Audio ADC, Record Selector
13:11 10:9
R2HVOL
(0dB) (mute)
R2MBST RECBST RECSL
(OFF) (OFF) (mic)
RECSR
(mic)
Register controls the.record selector mono mixer path.
REGISTER ADDRESS
LABEL B2HVOL B2SVOL B2MVOL
DEFAULT (mute) (0dB) (mute) (0dB) (mute) (0dB)
DESCRIPTION Mutes PCBEEP headphone mixer paths Controls gain PCBEEP headphone mixer paths Mutes PCBEEP speaker mixer path Controls gain PCBEEP speaker mixer path Mutes PCBEEP mono mixer path Controls gain PCBEEP mono mixer path
REFER Analogue Inputs, PCBEEP Input
14:12 10:8
Register controls analogue input PCBEEP.
June 2006
Pre-Production REGISTER ADDRESS 14:12 10:8 LABEL V2HVOL V2SVOL V2MVOL DEFAULT (mute) (0dB) (mute) (0dB) (mute) (0dB) DESCRIPTION Mutes VXDAC headphone mixer paths Controls gain VXDAC headphone mixer paths Mutes VXDAC speaker mixer path Controls gain VXDAC speaker mixer path Mutes VXDAC mono mixer path Controls gain VXDAC mono mixer path
WM9714L
REFER Audio Mixers, Side Tone Control
Register controls output signal Voice DAC.
REGISTER AD
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