SLAS514 DECEMBER 2006 16-BIT, 1-MSPS, PSEUDO-BIPOLAR, FULLY DIFFE

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SLAS514 DECEMBER 2006 16-BIT, 1-MSPS, PSEUDO-BIPOLAR, FULLY DIFFE

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ADS8472
SLAS514 DECEMBER 2006
16-BIT, 1-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE
FEATURES
APPLICATIONS
Medical Instruments 1-MHz Sample Rate Optical Networking ±0.4 Typ, ±0.65 Transducer Interface ±0.3 Typ, ±0.5 High Accuracy Data Acquisition Systems 16-Bit Ensured Over Temperature Magnetometers ±0.1-mV Offset Error ±0.05-PPM/°C Offset Error Drift DESCRIPTION ±0.035 %FSR Gain Error ADS8472 16-bit, 1-MSPS converter ±0.4-PPM/°C Gain Error Drift with internal 4.096-V reference 95dB SNR, -120dB THD, 123dB SFDR pseudo-bipolar, fully differential input. device includes 16-bit capacitor-based converter Zero Latency with inherent sample hold. ADS8472 offers Power: MSPS full 16-bit interface 8-bit option using Unipolar Differential Input Range: Vref -Vref read cycles. Onboard Reference with PPM/°C Drift ADS8472 available 48-lead Onboard Reference Buffer package characterized over industrial -40°C 85°C temperature range. High-Speed Parallel Interface Wide Digital Supply 5.25 8-/16-Bit Transfer 48-Pin Package HIGH SPEED CONVERTER FAMILY
TYPE/SPEED ADS8383 ~600 ADS8381 ADS8380 ADS8481 1.25 4MHz
18-Bit Pseudo-Diff 18-Bit Pseudo-Bipolar, Fully Diff ADS8327 16-Bit Pseudo-Diff ADS8328 16-Bit Pseudo-Bipolar, Fully Diff ADS8406 14-Bit Pseudo-Diff 12-Bit Pseudo-Diff ADS7886 ADS7890 ADS7883 ADS8413 ADS7891 ADS7881 ADS8372 ADS8472 ADS8405 ADS8402 ADS8410 ADS8412 ADS8422 ADS8382 ADS8370 ADS8371 ADS8482 ADS8471 ADS8401 ADS8411
REFIN 4.096-V Internal Reference
CDAC Comparator
Output Latches 3-State Drivers
BYTE 16-/8-Bit Parallel Output
REFOUT
Clock
Conversion Control Logic
CONVST BUSY
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2006, Texas Instruments Incorporated
ADS8472
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SLAS514 DECEMBER 2006
ORDERING INFORMATION
MODEL MAXIMUM INTEGRAL LINEARITY (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) MISSING CODES RESOLUTION (BIT) PACKAGE TYPE PACKAGE DESIGNATOR TEMPER-ATURE RANGE ORDERING INFORMATION TRANS-PORT MEDIA QTY. Tape reel Tape reel 1000 Tape reel Tape reel 1000
ADS8472IRGZT ADS8472I ±0.75 -40°C 85°C ADS8472IRGZR ADS8472IBRGZT ADS8472IB ±0.65 ±0.5 -40°C 85°C ADS8472IBRGZR
most current package ordering information, Package Option Addendum this document, website www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE AGND AGND Voltage AGND +VBD BDGND +VBD Digital input voltage BDGND Digital output voltage BDGND Tstg Operating free-air temperature range Storage temperature range Junction temperature max) package Lead temperature, soldering Power dissipation thermal impedance Vapor phase sec) Infrared sec) -0.4 -0.4 -0.3 -0.3 -0.3 2.55 -0.3 +VBD -0.3 +VBD (TJMax TA)/JA °C/W UNIT
Stresses beyond those listed under absolute maximum ratings cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under recommended operating conditions implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability.
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SLAS514 DECEMBER 2006
SPECIFICATIONS
-40°C 85°C, +VBD Vref 4.096 fSAMPLE MSPS (unless otherwise noted)
PARAMETER ANALOG INPUT Full-scale input voltage Absolute input voltage Common-mode input range Input capacitance Input leakage current SYSTEM PERFORMANCE Resolution missing codes
TEST CONDITIONS
UNIT
(-IN)
-Vref -0.2 -0.2 (Vref)/2 (Vref)/2
Vref Vref Vref (Vref)/2
ADS8472I ADS8472IB ADS8472I ADS8472IB ADS8472I ADS8472IB ADS8472I ADS8472IB ADS8472I ADS8472IB ADS8472I ADS8472IB ADS8472I ADS8472IB (±0.2 around Vref/2) (-IN) Vref 4.096 Vref 4.096 -0.1 -0.1 -0.65 -0.75 -0.5 -0.5 -0.5 ±0.4 ±0.4 ±0.3 ±0.3 ±0.1 ±0.1 ±0.05 ±0.05 ±0.035 ±0.035 ±0.4 ±0.4 1FFFFh output code 0.65 0.75
Bits Bits bit) bit)
Integral linearity
Differential linearity Offset error
Offset error temperature drift Gain error
ppm/°C ppm/°C
Gain error temperature drift
Common-mode rejection ratio Noise Power supply rejection ratio SAMPLING DYNAMICS Conversion time Acquisition time Throughput rate Aperture delay Aperture jitter Step response Over voltage recovery
Ideal input span, does include gain offset error. This endpoint INL, best fit. means least significant Measured relative ideal full-scale input [+IN (-IN)] 8.192 This specification does include internal reference voltage error drift.
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SLAS514 DECEMBER 2006
SPECIFICATIONS (Continued)
-40°C 85°C, +VBD Vref 4.096 fSAMPLE MSPS (unless otherwise noted)
PARAMETER DYNAMIC CHARACTERISTICS ADS8472I ADS8472IB Total harmonic distortion (THD) ADS8472I ADS8472IB ADS8472I ADS8472IB ADS8472I ADS8472IB Signal noise ratio (SNR) ADS8472I ADS8472IB ADS8472I ADS8472IB ADS8472I ADS8472IB Signal noise distortion (SINAD) ADS8472I ADS8472IB ADS8472I ADS8472IB ADS8472I ADS8472IB Spurious free dynamic range (SFDR) ADS8472I ADS8472IB ADS8472I ADS8472IB -3dB Small signal bandwidth -120 -121 -105 -110 -100 -103 95.1 95.3 95.1 94.5 95.2 94.5 TEST CONDITIONS UNIT
Calculated first nine harmonics input frequency.
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SLAS514 DECEMBER 2006
SPECIFICATIONS (Continued)
-40°C 85°C, +VBD Vref 4.096 fSAMPLE MSPS (unless otherwise noted)
PARAMETER VOLTAGE REFERENCE INPUT Reference voltage REFIN, Vref Reference resistance Reference current drain INTERNAL REFERENCE OUTPUT Internal reference start-up time Reference voltage range, Vref Source current Line regulation Drift DIGITAL INPUT/OUTPUT Logic family -CMOS Logic level Data format Straight Binary POWER SUPPLY REQUIREMENTS Power supply voltage Supply current Power dissipation TEMPERATURE RANGE Operating free-air +VBD 4.75 5.25 5.25 loads loads +VBD -0.3 +VBD +VBD From (+VA), with 1-µF storage capacitor Static load 4.75 5.25 4.081 4.096 4.111 PPM/°C 4.096 TEST CONDITIONS UNIT
vary ±20% This includes only current. +VBD current typical with load capacitance output pins.
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SLAS514 DECEMBER 2006
TIMING CHARACTERISTICS
specifications typical -40°C 85°C, =+VBD
PARAMETER t(CONV) t(ACQ) t(HOLD) tpd1 tpd2 tpd3 tsu1 tsu2 tpd4 tsu3 tdis tsu5 Conversion time Acquisition time Sample capacitor hold time CONVST BUSY high Propagation delay time, conversion BUSY Propagation delay time, start convert state rising edge BUSY Pulse duration, CONVST Setup time, CONVST Pulse duration, CONVST high CONVST falling edge jitter Pulse duration, BUSY signal Pulse duration, BUSY signal high Hold time, first data transition low, read cycle, BYTE input changes) after CONVST Delay time, Setup time, high high Pulse duration, Enable time, read cycle) data valid Delay time, data hold from high Delay time, BYTE rising edge falling edge data valid Pulse duration, high Pulse duration, high Hold time, last read cycle rising edge CONVST falling edge Propagation delay time, BUSY falling edge next read cycle) falling edge Delay time, BYTE edge edge skew Setup time, BYTE transition falling edge Hold time, BYTE transition falling edge Disable time, high high read cycle) 3-stated data Delay time, BUSY data valid delay Delay time, rising edge BUSY falling edge Delay time, BUSY falling edge rising edge BYTE transition setup time, from BYTE transition next BYTE transition. t(ACQ)min
UNIT
tsu(ABORT) Setup time from falling edge CONVST (used start valid conversion) next falling edge CONVST (when CONVST used abort) next falling edge (when used abort).
input signals specified with (10% +VBD) timed from voltage level (VIL VIH)/2. timing diagrams. timing measured with equivalent loads data bits BUSY pins.
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TIMING CHARACTERISTICS
specifications typical -40°C 85°C, +VBD
PARAMETER t(CONV) t(ACQ) t(HOLD) tpd1 tpd2 tpd3 tsu1 tsu2 tpd4 tsu3 tdis tsu5 Conversion time Acquisition time Sample capacitor hold time CONVST BUSY high Propagation delay time, conversion BUSY Propagation delay time, start convert state rising edge BUSY Pulse duration, CONVST Setup time, CONVST Pulse duration, CONVST high CONVST falling edge jitter Pulse duration, BUSY signal Pulse duration, BUSY signal high Hold time, first data transition low, read cycle, BYTE input changes) after CONVST Delay time, Setup time, high high Pulse duration, Enable time, read cycle) data valid Delay time, data hold from high Delay time, BYTE rising edge falling edge data valid Pulse duration, high Pulse duration, high Hold time, last read cycle rising edge CONVST falling edge Propagation delay time, BUSY falling edge next read cycle) falling edge Delay time, BYTE edge edge skew Setup time, BYTE transition falling edge Hold time, BYTE transition falling edge Disable time, high high read cycle) 3-stated data Delay time, BUSY data valid delay Delay time, rising edge BUSY falling edge Delay time, BUSY falling edge rising edge BYTE transition setup time, from BYTE transition next BYTE transition. t(ACQ)min
UNIT
tsu(ABORT) Setup time from falling edge CONVST (used start valid conversion) next falling edge CONVST (when CONVST used abort) next falling edge (when used abort).
input signals specified with (10% +VBD) timed from voltage level (VIL VIH)/2. timing diagrams. timing measured with equivalent loads data bits BUSY pins.
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SLAS514 DECEMBER 2006
ASSIGNMENTS
PACKAGE (TOP VIEW)
+VBD BDGND BYTE CONVST AGND AGND REFM REFM
REFOUT REFIN AGND AGND AGND AGND
BUSY BDGND +VBD DB10 DB11 DB12 DB13 DB14 DB15 AGND AGND
internal connection NOTE: package thermal must soldered printed circuit board thermal mechanical performance.
TERMINAL FUNCTIONS
NAME AGND BDGND BUSY BYTE CONVST Data DB15 DB14 DB13 DB12 DB11 DB10 Analog ground Digital ground interface digital supply Status output. High when conversion progress. Byte select input. Used 8-bit reading. fold back byte D[9:2] most significant bits folded back high byte most significant pins DB[17:10]. Convert start. falling edge this input ends acquisition period starts hold period. Chip select. falling edge this input starts acquisition period. 8-BIT BYTE (MSB) ones ones ones ones ones ones ones BYTE D15(MSB) 16-BIT BYTE DESCRIPTION
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TERMINAL FUNCTIONS (continued)
NAME REFIN REFOUT REFM +VBD (LSB) Inverting input channel Noninverting input channel connection Reference input Reference output. 1-µF capacitor between REFOUT REFM when internal reference used. Reference ground Synchronization pulse parallel output. When low, this serves output enable puts previous conversion results bus. Analog power supplies, Digital power supply ones ones ones DESCRIPTION (LSB)
TYPICAL CHARACTERISTICS
HISTOGRAM (8192 Conversion Outputs, Code Transition)
5000 4500 4000 4224 3968 3500
HISTOGRAM (8192 Conversion Outputs, Center Code)
9000 8045 8000
INTERNAL REFERENCE VOLTAGE FREE-AIR TEMPERATURE
4.098 4.0975 +VBD
Frequency
3000 2500 2000 1500 1000 Output Code +VBD 25°C, MSPS, Vref 4.096 Input Midscale
Frequency
6000 5000 4000 3000 2000 1000 Output Code +VBD 25°C, MSPS, Vref 4.096 Input Midscale
Reference Voltage
7000
4.097
4.0965
4.096 4.0955 4.095
Free-Air Temperature
Figure INTERNAL REFERENCE VOLTAGE SUPPLY VOLTAGE
4.0972 25°C 4.09719
Figure SUPPLY CURRENT FREE-AIR PERATURE
Figure SUPPLY CURRENT SUPPLY VOLTAGE
25°C, MSPS, Vref 4.096
45.6
Reference Voltage
+VBD MSPS,
Supply Current
45.6
Supply Current
4.09718 4.09717 4.09716 4.09715 4.09714 4.09713 4.75
Vref 4.096
45.2
45.2
44.8
44.8
44.4
44.4
4.85
4.95 5.05 5.15 Supply Voltage
5.25
4.75
4.85
4.95
5.05
5.15
5.25
Free-Air Temperature
Supply Voltage
Figure
Figure
Figure
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SLAS514 DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT SAMPLE RATE
+VBD 25°C, Vref 4.096
DIFFERENTIAL NONLINEARITY FREE-AIR TEMPERATURE
0.50 0.65 0.52
INTEGRAL NONLINEARITY FREE-AIR TEMPERATURE
0.25
0.39 0.26
Supply Current
LSBs
LSBs
0.13 -0.13 -0.26 -0.39
+VBD MSPS, Vref 4.096
-0.25
-0.52 -0.50 Sample Rate KSPS 1000 Free-Air Temperature -0.65 Free-Air Temperature
Figure DIFFERENTIAL NONLINEARITY SUPPLY VOLTAGE
0.50 0.25 0.65 0.52 0.39 0.26
Figure INTEGRAL NONLINEARITY SUPPLY VOLTAGE
0.50
Figure DIFFERENTIAL NONLINEARITY REFERENCE VOLTAGE
0.25
LSBs
LSBs
25°C,, MSPS, Vref 4.096
0.13 -0.13 -0.26 -0.39 -0.52
LSBs
25°C MSPS, Vref 4.096
25°C, MSPS
-0.25
-0.25
-0.50 4.75
4.85
4.95 5.05 5.15 Supply Voltage
5.25
-0.65 4.75
-0.50 4.85 4.95 5.05 Supply Voltage 5.15 5.25 Reference Voltage
Figure INTEGRAL NONLINEARITY REFERENCE VOLTAGE
0.65 0.52 0.39 0.200
Figure OFFSET ERROR FREE-AIR TEMPERATURE
0.150 0.150 +VBD MSPS, 0.100 Vref 4.096
Figure OFFSET ERROR SUPPLY VOLTAGE
25°C, MSPS, Vref 4.096
0.100
LSBs
0.13 -0.13 -0.26
25°C, MSPS
Offset Error
0.050 -0.050 -0.100
Offset Error
0.26
0.050
-0.39 -0.52 -0.65 Reference Voltage
-0.050 -0.150 -0.200 -0.100 4.75
4.85
Free-Air Temperature
4.95 5.05 5.15 Supply Voltage
5.25
Figure
Figure
Figure
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SLAS514 DECEMBER 2006
TYPICAL CHARACTERISTICS (continued)
OFFSET ERROR REFERENCE VOLTAGE
0.100 0.080 0.060 MSPS, -0.01 -0.02
GAIN ERROR SUPPLY VOLTAGE
-0.03
GAIN ERROR FREE-AIR TEMPERATURE
+VBD MSPS, Vref 4.096 -0.034
Gain Error
25°C, MSPS, Vref 4.096
Gain Error
-0.032
Offset Error
0.040 0.020 -0.020 -0.040 -0.060
-0.03 -0.04 -0.05 -0.06
-0.036
-0.038 -0.07
-0.080 -0.100 Reference Voltage -0.08 4.75 4.85 4.95 5.05 5.15 Supply Voltage 5.25 -0.04
Free-Air Temperature
Figure GAIN ERROR REFERENCE VOLTAGE
0.08 0.06 25°C, MSPS
Figure
Figure
OFFSET ERROR TEMPERATURE DRIFT DISTRIBUTION Samples)
GAIN ERROR TEMPERATURE DRIFT DISTRIBUTION Samples)
Gain Error
0.04 0.02 -0.02 -0.04 -0.06 -0.08 -0.1 Reference Voltage
+VBD MSPS, Vref 4.096
Frequency
+VBD MSPS, Vref 4.096
Frequency
0.01 0.03 0.04 0.05 0.07 Offset Drift ppm/C 0.08 0.03 0.19 0.35 0.50 0.66 Gain Error Drift ppm/C 0.90
Figure TOTAL HARMONIC DISTORTION REFERENCE VOLTAGE
-119 95.4 +VBD MSPS, -120 25°C,
Figure SIGNAL-TO-NOISE RATIO REFERENCE VOLTAGE
+VBD MSPS, 25°C,
Figure SIGNAL-TO-NOISE DISTORTION REFERENCE VOLTAGE
SINAD Signal-to-Noise Distortion
95.4 95.2 94.8 94.6 94.4 94.2 93.8 Vref Reference Voltage +VBD MSPS, 25°C,
Signal-to-Noise Ratio
95.2 94.8 94.6 94.4 94.2 93.8
-121 -122 Vref Reference Voltage
Vref Reference Voltage
Figure
Figure
Figure
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TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION FREE-AIR TEMPERATURE
SFDR Spurious Free Dynamic Range
-115
SPURIOUS FREE DYNAMIC RANGE FREE-AIR TEMPERATURE
120.8 120.6 120.4 120.2 119.8 119.6 +VBD MSPS, 25°C, 95.30
SIGNAL-TO-NOISE RATIO FREE-AIR TEMPERATURE
+VBD 95.25 MSPS, Vref 4.096 95.20
Total Harmonic Distortion
-116 -117 -118 -119 -120 -121 -122
Vref 4.096
Signal-to-Noise Ratio
+VBD MSPS,
95.15
95.10 95.05
Free-Air Temperature
Free-Air Temperature
Free-Air Temperature
Figure
Figure SIGNAL-TO-NOISE DISTORTION FREE-AIR TEMPERATURE
SINAD Signal-to-Noise Distortion
95.30 95.25 95.20 +VBD MSPS, Vref 4.096
Figure
95.15 95.10 95.05
Free-Air Temperature
Figure
-0.1 -0.2 -0.3 -0.4 -0.5 -32768 +VBD 25°C, MSPS, Vref 4.096
LSBs
-16384
Output Code Figure
16384
32768
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TYPICAL CHARACTERISTICS (continued)
0.65 0.52 0.39 0.26 0.13 -0.13 -0.26 -0.39 -0.52 -0.65 -32768 +VBD 25°C, MSPS, Vref 4.096
LSBs
-16384
Output Code Figure
16384
32768
Amplitude
-100 -120 -140 -160 -180 -200
+VBD 25°C, MSPS, Vref 4.096 kHz, 65536 Points,
100000
200000
300000
400000
500000
Frequency Figure
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TYPICAL CHARACTERISTICS (continued) TIMING DIAGRAMS
CONVST tpd1 BUSY tsu1 tpd3 CONVERT t(HOLD) SAMPLING (When Toggle) t(ACQ) BYTE tsu(ABORT) tsu5 tsu5 tpd4 tsu5 tsu5 tsu2 tsu(ABORT) t(CONV) t(CONV) tpd2
DB[15:8] Hi-Z D[15:8] DB[7:0]
Signal
tdis Hi-Z D[7:0] Hi-Z D[7:0]
Hi-Z
internal device
Figure Timing Conversion Acquisition Cycles With Toggling
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TYPICAL CHARACTERISTICS (continued)
CONVST tpd1 BUSY tsu6 tpd3 CONVERT t(CONV) t(HOLD) SAMPLING (When Toggle) t(ACQ) tsu(ABORT) BYTE tsu5 tdis tpd4 Hi-Z Previous [15:8] Hi-Z D[15:8] DB[7:0] Hi-Z Previous [7:0] Hi-Z D[7:0]
Signal
tpd2
t(CONV)
tsu(ABORT) tsu5 tsu5 tsu5
tsu2 tdis Hi-Z D[7:0] Hi-Z Previous [7:0] Previous [15:8]
DB[15:8]
internal device
Figure Timing Conversion Acquisition Cycles With Toggling, Tied BDGND
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TYPICAL CHARACTERISTICS (continued)
CONVST tpd1 BUSY tpd2
tpd3 CONVERT t(CONV) t(HOLD) t(CONV)
SAMPLING (When tsu(ABORT) BYTE tpd4 DB[15:8] Hi-Z
t(ACQ)
tsu5 tsu5 tdis
tsu(ABORT)
Hi-Z D[15:8] D[7:0] Hi-Z D[7:0]
DB[7:0]
Hi-Z
Signal
internal device
Figure Timing Conversion Acquisition Cycles With Tied BDGND, Toggling
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TYPICAL CHARACTERISTICS (continued)
CONVST tpd1 BUSY tpd2
CONVERT tpd3 t(HOLD)
t(CONV) tpd3 t(HOLD) t(ACQ)
t(CONV)
SAMPLING (When tsu(ABORT) BYTE tsu5 tdis tsu5 tsu(ABORT)
tsu5 DB[15:8] Previous D[7:0] D[15:8] DB[7:0] D[7:0]
Signal
tsu5
D[7:0] Next D[15:8]
Next D[7:0]
internal device
Figure Timing Conversion Acquisition Cycles With Tied BDGND Auto Read
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TYPICAL CHARACTERISTICS (continued)
tsu4 BYTE Hi-Z Valid tdis Hi-Z Valid Valid tdis Hi-Z
DB[15:0]
Figure Detailed Timing Read Cycles
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APPLICATION INFORMATION ADS8472 HIGH PERFORMANCE INTERFACE
Figure shows parallel interface between ADS8472 Texas instruments high performance such TMS320C6713 using full 16-bit bus. ADS8472 mapped onto memory space TMS320C6713 DSP. read reset signals generated using 3-to-8 decoder. read operation from address 0xA000C000 generates pulse data converter, wheras read operation form word address 0xA0014000 generates pulse RESET/PD1 pin. signal acts (chip select) converter. TMS320C6713 features 32-bit external memory interface, BYTE input converter tied permanently low, disabling foldback data bus. BUSY signal ADS8472 appiled EXT_INT6 interrupt input DSP, enabling EDMA controller react falling edge this signal collect conversion result. TOUT1 (timer TMS320C6713 used source CONVST signal converter.
AGND Input Analog Input
REFIN REFM AGND
TMS320C6713 Address Decoder EA[16:14] TOUT1 EXT_INT6 ED[15:0]
Supply +VBD +2.7 ADS8472 +VBD CONVST BUSY DB[15:0] BDGND BYTE Digital Ground BDGND
Figure ADS8472 Application Circuitry
Analog
AGND
REFOUT REFM REFIN AGND
AGND
ADS8472
Figure ADS8472 Using Internal Reference
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PRINCIPLES OPERATION
ADS8472 high-speed successive approximation register (SAR) analog-to-digital converter (ADC). architecture based charge redistribution which inherently includes sample/hold function. Figure application circuit ADS8472. conversion clock generated internally. conversion time capable sustaining throughput. analog input provided input pins: -IN. When conversion initiated, differential input these pins sampled internal capacitor array. While conversion progress, both inputs disconnected from internal function.
REFERENCE
ADS8472 operate with external reference with range from reference voltage input (REFIN) converter internally buffered. clean, noise, well-decoupled reference voltage this required ensure good performance converter. noise band-gap reference like REF3240 used drive this pin. 0.1-µF decoupling capacitor required between REFIN REFM pins (pin #12) converter. This capacitor should placed close possible pins device. Designers should strive minimize routing length traces that connect terminals capacitor pins converter. network also used filter reference voltage. 100- series resistor 0.1-µF capacitor, which also serve decoupling capacitor used filter reference voltage.
REFM
REF3240 REFIN
ADS8472
Figure ADS8472 Using External Reference ADS8472 also limited pass filtering capability built into converter. equivalent circuitry REFIN input shown Figure
REFIN REFM CDAC
CDAC
Figure Simplified Reference Input Circuit REFM input ADS8472 should always shorted AGND. 4.096-V internal reference included. When internal reference used, (REFOUT) connected (REFIN) with 0.1-µF decoupling capacitor 1-µF storage capacitor between (REFOUT) pins (REFM) (see Figure 38). internal reference converter double buffered. external reference used, second buffer provides isolation between external reference CDAC. This buffer also used recharge capacitors CDAC during conversion. (REFOUT) left unconnected (floating) external reference used.
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PRINCIPLES OPERATION (continued) ANALOG INPUT
When converter enters hold mode, voltage difference between inputs captured internal capacitor array. Both input range -0.2 Vref input span [+IN (-IN)] limited -Vref Vref. input current analog inputs depends upon number factors: sample rate, input voltage, source impedance. Essentially, current into ADS8472 charges internal capacitor array during sample period. After this capacitance been fully charged, there further input current. source analog input must able charge input capacitance 16-bit settling level within acquisition time (320 device. When converter goes into hold mode, input impedance greater than Care must taken regarding absolute analog input voltage. maintain linearity converter, inputs span [+IN (-IN)] must within limits specified. Outside these ranges, converter's linearity meet specifications. minimize noise, bandwidth input signals with low-pass filters used. Care must taken ensure that output impedance sources driving inputs matched. this observed, inputs could have different setting times. This result offset error, gain error, linearity error which varies with temperature input voltage. analog input converter needs driven with noise, high-speed op-amp like THS4031. filter recommended input pins low-pass filter noise from source. input converter uni-polar input voltage range Vref. THS4031 used source follower configuration drive converter.
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PRINCIPLES OPERATION (continued)
+VIN THS4031 (+)IN
2200
THS4031 +2.048 (-)IN
Figure Single-Ended Input, Differential Output Configuration systems, where input differential, THS4031 used inverting configuration with additional bias applied input keep input ADS8472 within rated operating voltage range. bias derived from REF3220 REF3240 reference voltage ICs. input configuration shown below capable delivering better than 97dB -103db input frequency kHz. case band-pass filters used filter input, care should taken ensure that signal swing input band-pass filter small keep distortion introduced filter minimal. such cases, gain circuit shown below increased keep input ADS8472 large keep system high. Note that gain system from input output THS4031 such configuration function gain signal. resistor divider used scale output REF3220 REF3240 reduce voltage input THS4031 keep voltage input converter within rated operating range.
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PRINCIPLES OPERATION (continued)
+2.048 +VIN THS4031
(+)IN
Cascade System
-12V
2200
Cascade System Pattern Generator Platform SNR: 95.3 SINAD: 95.3 THD: -121 SFDR: ENOB(SINAD): 15.5 -VIN
+12V THS4031 (-)IN
+2.048
Figure Differential Input, Differential Output Configuration
DIGITAL INTERFACE
Timing Control timing diagrams specifications section detailed information timing signals their requirements. ADS8472 uses internal oscillator generated clock which controls conversion rate turn throughput converter. external clock input required.
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ADS8472
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PRINCIPLES OPERATION (continued)
Conversions initiated bringing CONVST minimum (after minimum requirement been met, CONVST brought high), while low. ADS8472 switches from sample hold mode falling edge CONVST command. clean jitter falling edge this signal important performance converter. BUSY output brought high immediately following CONVST going low. BUSY stays high throughout conversion process returns when conversion ended. Sampling starts with falling edge BUSY signal when tied starts with falling edge when BUSY low. Both high during before conversion with exception must when CONVST goes initiate conversion). Both pins brought order enable parallel output with conversion. Reading Data ADS8472 outputs full parallel data straight binary format shown Table parallel output active when both low. There minimal quiet zone requirement around falling edge CONVST. This prior falling edge CONVST after falling edge. data read should attempted within this zone. other combination sets parallel output 3-state. BYTE used multiword read operations. BYTE used whenever lower bits output higher byte bus. Refer Table ideal output codes. Table Ideal Input Voltages Output Codes
DESCRIPTION Full scale range Least significant (LSB) +Full scale Midscale Midscale Zero ANALOG VALUE +Vref (+Vref)/65536 (+Vref) -Vref DIGITAL OUTPUT STRAIGHT BINARY BINARY CODE 0111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 1000 0000 0000 0000 CODE 1FFF 0000 3FFF 2000
output data full 16-bit word (D15-D0) DB15-DB0 pins (MSB-LSB) BYTE low. result also read 8-bit convenience. This done using only pins DB15-DB8. this case reads necessary: first before, leaving BYTE reading most significant bits pins DB15-DB8, then bringing BYTE high. When BYTE high, bits (D7-D0) appear pins DB15-DB8. these multiword read operations performed with multiple active (toggling) with held simplicity. This referred AUTO READ operation. Table Conversion Data Read
DATA READ BYTE High PINS DB15-DB8 D7-D0 D15-D8 PINS DB7-DB0 One's D7-D0
RESET
power-up, internal POWER-ON RESET circuitry generates reset required device. first three conversions after power-up used load factory trimming data specific device assure high accuracy converter. results first three conversions invalid should discarded. device also reset through combination CONVST. Since BUSY signal held high during conversion, either these conditions triggers internal self-clear reset converter.
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Issue CONVST when internal convert state high. falling edge CONVST starts reset. Issue (select device) while internal convert state high. falling edge causes reset.
Once device reset, output latches cleared (set zeroes) BUSY signal brought low. sampling period started falling edge BUSY signal immediately after instant internal reset.
LAYOUT
optimum performance, care must taken with physical layout ADS8472 circuitry. ADS8472 offers single-supply operation, often used close proximity with digital logic, microcontrollers, microprocessors, digital signal processors. more digital logic present design higher switching speed, more difficult achieve good performance from converter. basic architecture sensitive glitches sudden changes power supply, reference, ground connections digital inputs that occur just prior latching output analog comparator. Thus, driving single conversion n-bit converter, there least windows which large external transient voltages affect conversion result. Such glitches might originate from switching power supplies, nearby digital logic, high power devices. degree error digital output depends reference voltage, layout, exact timing external event. average, ADS8472 draws very little current from external reference reference voltage internally buffered. reference voltage external originates from amp, make sure that drive bypass capacitor capacitors without oscillation. 0.1-µF capacitor recommended from (REFIN) directly (REFM). REFM AGND must shorted same ground plane under device. AGND BDGND pins should connected clean ground point. cases, this should analog ground. Avoid connections which close grounding point microcontroller digital signal processor. required, ground trace directly from converter power supply entry point. ideal layout consists analog ground plane dedicated converter associated analog circuitry. with AGND connections, should connected power supply plane trace that separate from connection digital logic until they connected power entry point. Power ADS8472 should clean well bypassed. 0.1-µF ceramic bypass capacitor should placed close device possible. Table placement capacitor. addition, 1-µF 10-µF capacitor recommended. some situations, additional bypassing required, such 100-µF electrolytic capacitor even filter made inductors capacitors-all designed essentially low-pass filter supply, removing high frequency noise. Table Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE SUPPLY PINS pairs that require shortest path decoupling capacitors Pins that require decoupling CONVERTER ANALOG SIDE (7,8), (9,10), (16,17), (20,21), (22,23), (25,26) CONVERTER DIGITAL SIDE (36,37) (1,2)
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device ADS8472IBRGZR ADS8472IBRGZRG4 ADS8472IBRGZT ADS8472IBRGZTG4 ADS8472IRGZR ADS8472IRGZRG4 ADS8472IRGZT ADS8472IRGZTG4
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type
Package Drawing
Pins Package Plan 2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR
2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
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SLAS514 DECEMBER 2006 16-BIT, 1-MSPS, PSEUDO-BIPOLAR, FULLY DIFFE

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