Scalable System Design CALISTO PRODUCT CALISTO Ser

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Scalable System Design CALISTO PRODUCT CALISTO Ser

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Scalable System Design
CALISTO
PRODUCT
CALISTO
Service Stack Channel Socket
CALISTO CALISTO CALISTO
Brief
SpiceBus
Bridge (Aggregation Device)
Bridge (Aggregation Device)
Transport Medium
Gateway xChange field-hardened software CALISTO communication processor integrated with Gateway xChange software provides:
Packet voice VAD/CNG Line echo cancellation with 16-128 tail length Voice compression: G.711 µ-law/A-law Kbps, G.726 16/24/32/40 Kbps, G.729A/B Kbps, G.729E 11.8 Kbps, G.723.1/A 5.3/6.3 Kbps, G.728 Kbps Dynamic jitter buffer manager services relay synchronization T.38 relay over AAL2 Data pumps: V.17 14400 bps, V.29 9600 bps, V.27ter Data relay
HausWare Framework's RTOS provides ability
Host System
Includes field-hardened Gateway xChange services. Open platform provides customers with flexibility
customize solutions adding their unique services.
dynamically configure system over channels carrier class G.711 channels full universal port processing.
Application Software
CALISTO Object Channel Socket Object
Enables toll-quality voice. Shorten product development time with CALISTO GUIbased tools suite:
Industry-leading optimizing compiler Assembler Linker Debugger with cycle-accurate simulator profiler Unique multichannel, multiservice debug paradigm Remote debug capability
Bridge Object
CALISTO Host
Transport Layer
CALISTO Host CALISTO Host C-language, re-entrant library that lets multi-threaded applications control CALISTO SpiceBridge devices. library implemented ANSI standard programming language, protected from underlying operating system abstraction layer. library ported between operating systems host platforms. library, CALISTO Host always executes task contexts provided application software. CALISTO Host allows users embed CALISTO SpiceBridge products into custom hardware architectures. provides language software objects that correspond hardware components, tied together reflect architecture custom system. object-oriented design provides flexibility expand capability added CALISTO, when hardware devices become available. Users place library objects into tables maintained call management applications, system-specific data objects that they themselves become table entries. objects encapsulate addressing state data provide flexible scalable data organization. object-oriented approach also lets manage state related objects. users reset CALISTO, Channel Socket Objects associated with CALISTO change state well. This encapsulation assists users managing connections, implementing backup redundancy scheme.
Data synchronization Data pumps: V.34 33600 bps, V.32bis/V.32 14400 bps, V.22bis/V.22 2400 Signaling relay: DTMF, MF-R1, Type Caller CPM/CPG
Reference design platform training available
testing customization projects.
BCM1500/1510 chip
Robust
processing units chip: SpiceEnginesand RISC processors physical interfaces: ports, SpiceBus ports, SDRAM port, JTAG port, serial boot port, port 19-mm, 239-ball ceramic fine-pitch Reconfigurable-adaptive instruction sets Over GMACs signal processing power compiler robust Integrated Development Environment (IDE) included
CALISTO Architecture
Shared Memory
Cluster Memory Boot
Cluster Proc
Cluster Memory
Broadcom pulse logo Connecting everything trademarks Broadcom Corporation and/or subsidiaries United States certain other countries. other trademarks property their respective owners.
Cluster Proc
Master Proc Cluster Memory
SpiceEngine Array
Cluster Proc
Spice Engine
Cluster Proc
Cluster Memory
BROADCOM CORPORATION 16215 Alton Parkway, P.O. 57013 Irvine, California 92619-7013
2003 BROADCOM CORPORATION. rights reserved. 1500VoP-PB03-R-4.15.03
Phone: 949-450-8700 FAX: 949-450-8710 Email: info@broadcom.com Web: www.broadcom.com
SpiceBus
DRAM (optional)
CALISTO Sub-system Diagram
Host
Gateway xChange CALISTO
Packet Network
Packet Interface Service Supervisory Service
RTP/AAL2
Interface
Bridge
Buffer
Packet Voice Jitter Buffer Manager In-band Signaling Relay VAD/CNG Voice Compression
G.711 mu-law/A-law kbps G.726 16/24/32/40 kbps G.729A/B kbps G.729E 11.8 kbps G.723.1/A 5.3/6.3 kbps G.728 kbps
Packet Voice
G.7xx CDIS
BCM15101
BCM15102
BCM1510N-1
BCM1510N
Relay
Data Relay
Conferencing Service
Relay Jitter Buffer Manager Modems
V.17 14400 V.29 9600 V.26ter 4800
IN/OUT
IN/OUT
Synchronization T.3x Relay
Highway Interface
DTMF/MFG
V.2x/V.1x Data Pump
Tone Service
DTMF/MFD
CALISTO BCM1500/1510 Architecture CALISTO architecture employs reconfigurable-adaptive instruction sets, hierarchical multi-processing, hybrid RISC/DSP implementation provide over GMACS signal processing horsepower (that's over packet telephony channels chip). This unique architecture enables convergence voice data services over unified data network with highest voice density square inch, watt, industry. CALISTO explicitly designed meet exceed current future challenges complex packet processing, signal processing, high-speed memory requirements carrier broadband access networks. Working with Gateway xChange suite services, CALISTO manages compute-intensive tasks such echo cancellation, voice fax/data modem signal processing, packetization, transformation data into cells, delay equalization, telephony protocols within packet telephony applications including carrier gateways, broadband access gateways, remote access concentrators. this power packed into 19-mm, 239-ball ceramic finepitch BGA. Chip Interfaces
serial boot port provides standard Serial Peripheral Interface (SPI) running MHz. standard test access port provides support JTAG IEEE 1149.1. internal provides core frequencies MHz.
Call Descriminator Service Circuit Interface Service
V.21/CED/ CNG/V.18
V.21/CED/ CNG/V.18
Data Relay Jitter Buffer Manager Data Synchronization Data Modems
V.34 33600 V.32bis/V.32 14400 V.22bis/V.22 2400
G.165/168 G.711 G.711
Data Relay V.3x/V.2x Data Pump
CALISTO Subsystem preceding figure shows CALISTO-based subsystem capable handling OC-3 (2016 DS0). Each CALISTO pushes data towards system interface, SpiceBus, thus eliminating need host-assisted from shared memory, allowing efficient aggregation devices, SpiceBridges. Each SpiceBridge aggregates, single step, control data traffic from eight CALISTO devices towards system backplane. Broadcom provides several flavors SpiceBridge flexible logic cores. example, Bridge preceding figure, CALISTO (Media Independent Interface) Bridge, supports FPGA implementation CALISTO BCM1500/1510 carrier-access architecture. device built around this logic core bridge eight BCM1500/1510s single interface. SpiceBridge enables design high density Voice over subsystems. CALISTO Bridge integral Broadcom's multichannel, multiservice, carrier-access architecture. handling packet-side control data flows, bridge supports flexible integration circuit-switched packet-switched networks. Broadcom-supported Verilog block, CALISTO Bridge quickly reconfigured meet changing customer requirements. Gateway xChange software conjunction with CALISTO BCM1500/1510 enables highest density processing voice/fax/data over packet networks industry. xChange Services Circuit Interface Service (PCM AAL1) supports G.711 µ-law/A-law, hosts G.168 echo cancellation with 32/64/128 tail lengths, detects generates idle patterns, initializes linear ingress egress media buffers, stores ingress/egress history, provides loopback towards circuit packet network, provides gain control ingress/egress samples, provides energy measurement ingress media. Call Discrimination Service (CDIS) hosts fax/modem/V.18 detection, allows detection events used supervisory service reconfigure channel, runs either ingress egress direction. Tone Service (PTE) detects DTMF, tones, incorporates programmable tone generation packet direction, with features support special tones like calling cards. Conferencing Service transmits samples another channel, receives samples sums with local data, includes aggregation channel provide support larger conferences. Packet Voice Service (PVE) incorporates adaptable/configurable jitter buffer, vocoders, VAD/CNG; supports asymmetric encode/decode; provides G.711, G.726, G.729A/B/E, G.728, G.723.1, AMR, GSM/EFR algorithms, with 5-ms packetizations G.711, G.726, G.278; allows super-packetization eight frames, reorders packets jitter buffer, provides jitter buffer statistics, includes packet loss concealment algorithm, provides egress jitter buffer adaptation control absence arriving SIDS) noise level/spectrum matching; supports voice band data mode, with clock drift compensation, modem/fax pass-through. Relay Service accepts T.38 AAL2 packet formats, supports V.21, V.27ter, V.29, V.17 V.33 data algorithms, incorporates end-of-line spoofing non-ECM calls HDLC spoofing V.21 calls supports both T.32 Data Rate Management methods. Supervisory Service intercepts filters events generated services, provides high-level control interface. Packet Interface Service supports either RTP/UDP/IP AAL1/AAL2 packet encapsulation, converts from internal packet headers protocol-specific headers, sends receives data packet interface, provides support loopback towards circuit packet network.
line-side ports provide glueless connection offthe-shelf framers MVIP switches. packet-side full-duplex SpiceBus ports, running MHz, provide efficient connection backplane. SDRAM port provides 32-bit-wide data path capable running MHz.

Scalable System Design CALISTO PRODUCT CALISTO Ser

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