512Mbit banks supply, power SDRAM 512Mbit Synchronous Dynamic Org

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512Mbit banks supply, power SDRAM 512Mbit Synchronous Dynamic Org

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M65KG512AB
512Mbit banks supply, power SDRAM
512Mbit Synchronous Dynamic Organized banks Mwords, each bits wide Double Data Rate (DDR) Data Transfers/Clock cycle Data Rate: Mbit/s max. speed class Supply voltage (1.8 typical accordance with JEDEC standard) VDDQ Inputs/Outputs Synchronous Burst Read Write Fixed Burst Lengths: words Burst Types: Sequential Interleaved. Clock Frequency: (7.5 speed class), speed class) Clock Valid Output Delay (CAS Latency): maximum clock frequency Burst Read Control Burst Read Terminate Precharge Commands Automatic Precharge Byte Write controlled LDQM UDQM Low-power features Partial Array Self Refresh (PASR) Automatic Temperature Compensated Self Refresh (ATCSR) Driver Strength (DS) Deep Power-Down mode Auto Refresh Self Refresh LVCMOS interface compatible with multiplexed addressing Operating temperature: M65KG512AB only available part multi-chip package product.
Wafer
February 2007
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Contents
M65KG526AB
Contents
Description Signal descriptions
2.10 2.11 2.12 2.13 2.14 2.15 Address Inputs (A0-A12) Bank Select Address Inputs (BA0-BA1) Data Inputs/Outputs (DQ0-DQ15) Chip Enable Column Address Strobe (CAS) Address Strobe (RAS) Write Enable Clock Inputs Clock Enable (KE) Lower/Upper Data Input Mask (LDQM, UDQM) Lower/Upper Data Read/Write Strobe Input/Output (LDQS, UDQS) supply voltage VDDQ supply voltage ground VSSQ ground
Commands
3.10 3.11 Mode Register command (MRS) Extended Mode Register command (EMRS) Bank(Row) Activate command (ACT) Read command (READ) Read with Auto Precharge command (READA) Burst Read Terminate command (BST) Write command (WRIT) Write with Auto Precharge command (WRITA) Precharge Selected Bank/Precharge Banks command (PRE/PALL) Self Refresh Entry command (SELF) Self Refresh Exit command (SELFX)
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M65KG526AB
Contents
3.12 3.13 3.14 3.15 3.16 3.17
Auto Refresh command (REF) Power-Down Entry command (PDEN) Power-Down Exit command (PDEX) Deep Power-Down Entry command (DPDEN) Device Deselect command (DESL) Operation command (NOP)
Operating modes
Power-Up Burst Read Burst Write Self Refresh Auto Refresh Power-Down Deep Power-Down
Registers description
Mode Register description Extended Mode Register description
Maximum rating parameters Part numbering Revision history
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List tables
M65KG526AB
List tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Signal names Bank selection using BA0-BA1 Commands Minimum delay between commands concurrent Auto Precharge Mode Burst Type Definition Operating modes Mode Register definition Extended Mode Register definition Absolute maximum ratings Operating measurement conditions Capacitance Characteristics characteristics Self Refresh current (IDD6) normal operating mode characteristics characteristics characteristics measured clock period Ordering Information Scheme. Document revision history
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M65KG526AB
List figures
List figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Logic diagram Functional block diagram Simplified command state diagram. measurement waveform measurement load circuit Definition command address inputs timings Definition Read timings Definition Read timings Consecutive Bank(Row) Activate command. Read followed Read same bank Read followed Read different bank Read with Auto Precharge Read followed Auto Precharge waveforms Read operation (Burst lengths latency Burst Terminate during Read operation Write followed Write same bank Write followed Write different bank Write operation with Auto Precharge Write with Auto Precharge Waveforms Write operation (Burst lengths latency Write waveforms (data masking using LDQM/UDQM). Mode Register/Extended Mode Register commands waveforms Read followed Write using Burst Read Terminate command (BST) Write followed Read (Write completed) Write followed Read same Bank (Write Interrupted). Power-Up sequence Auto Refresh command waveforms Self Refresh Entry Exit commands waveforms Deep Power-Down Entry command waveforms Deep Power-Down Exit waveforms
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Description
M65KG526AB
Description
M65KG512AB 512Mbit Double Data Rate (DDR) Power Synchronous DRAM (LPSDRAM). memory array organized Banks 8,388,608 words bits each. device achieves power consumption very high-speed data transfer using 2bit prefetch pipeline architecture that allows doubling data input/output rate. Command address inputs synchronized with rising edge clock while data inputs/outputs transferred both edges system clock. M65KG512AB well suited handheld battery powered applications like PDAs, mobile phones handheld computers. device architecture illustrated Figure Functional block diagram. uses Burst mode read write data. capable two, four, eight-word, sequential interleaved burst. minimize current consumption during self refresh operations, M65KG512AB includes three mechanisms configured Extended Mode Register:
Automatic Temperature Compensated Self Refresh (ATCSR) adapts refresh frequency according operating temperature provided built-in temperature sensor. Partial Array Self Refresh (PASR) performs limited refresh half bank, quarter bank, bank, banks banks. Deep Power-Down (DPD) mode completely halts refresh operation achieves minimum current consumption cutting supply voltage from whole memory array.
device programmable through registers, Mode Register Extended Mode Register:
Mode Register used select Latency, Burst Type (sequential, interleaved) Burst Length. more details, refer Table Mode Register definition, Section 3.1: Mode Register command (MRS). Partial Array Self Refresh (PASR) performs limited refresh half bank, quarter bank, bank, banks banks. Extended Mode Register used configure low-power features (PASR, ATCSR Driver Strength) reduce current consumption during Self Refresh operations. more details, refer Table Extended Mode Register definition, Section 3.2: Extended Mode Register command (EMRS).
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M65KG526AB Figure Logic diagram
VDDQ A0-A12 BA0-BA1 UDQM LDQM M65KG512AB UDQS LDQS DQ0-DQ15
Description
VSSQ
AI12443
Table
A0-A12 BA0-BA1 DQ0-DQ15 UDQM LDQM UDQS LDQS VDDQ VSSQ
Signal names
Address Inputs Bank Select Inputs Data Inputs/Outputs Clock Inputs Clock Enable Input Chip Enable Input Write Enable Input Address Strobe Input Column Address Strobe Input Upper Data Input Mask Lower Data Input Mask Upper Data Read/ Write Strobe Lower Data Read/Write Strobe Supply Voltage Input/Output Supply Voltage Ground Input/Output Ground
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Description Figure
M65KG526AB Functional block diagram
Clock Generator TCSR, PASR Extended Mode Register Self Refresh Logic Timer Internal Counter Active PreDecoders Bank Bank Bank Sense Gate Bank Memory Cell Array Column Decoders Bank Select Column Counter Buffer Logic Decoders Decoders Decoders Decoders
StateMachine
Refresh Column Active
DQ15 UDQM/LDQM UDQS/LDQS
Column PreDecoders
Address Buffers
Address Registers Burst Counter Burst Length Mode Register
Latency
Data Control
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M65KG526AB
Signal descriptions
Signal descriptions
Figure Logic diagram, Table Signal names, brief overview signals connected this device.
Address Inputs (A0-A12)
A0-A12 Address Inputs used select column made active. selected, thirteen, A0-A12 Address Inputs used. column selected, only least significant Address Inputs, A0-A9, used. this latter case, determines whether Auto Precharge used:
During Read Write operation: High (set `1'), Read Write operation includes Auto Precharge cycle. (set `0'), Read Write cycle does include Auto Precharge cycle. Low, only bank selected BA1-BA0 will precharged. High, banks will precharged.
When issuing Precharge command:
address inputs latched cross point rising edge falling edge.
Bank Select Address Inputs (BA0-BA1)
Banks Select Address Inputs, BA1, used select bank made active (see Table Bank selection using BA0-BA1). When selecting addresses, device must enabled, Address Strobe, RAS, must Low, VIL, Column Address Strobe, CAS, must High, VIH.
Data Inputs/Outputs (DQ0-DQ15)
Data Inputs/Outputs output data stored selected address during Read operation, input data during write operation.
Chip Enable
Chip Enable input, activates memory state machine, address buffers decoders when driven Low, VIL. When High, VIH, device selected.
Column Address Strobe (CAS)
Column Address Strobe, CAS, used conjunction with Address Inputs A0-A9 BA1-BA0, select starting column location prior read write operation.
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Signal descriptions
M65KG526AB
Address Strobe (RAS)
Address Strobe, RAS, used conjunction with Address Inputs A0-A12 BA1-BA0, select starting address location prior Read Write.
Write Enable
Write Enable input, controls writing.
Clock Inputs
Clock signals, master clock inputs. input signals except UDQM/LDQM, UDQS/LDQS DQ0-DQ15 referred cross point rising edge falling edge. During read operations, UDQS/LDQS DQ0-DQ15 referred cross point rising edge falling edge. During write operations, UDQM/LDQM DQ0-DQ15 referred cross point UDQS/LDQS VREF, UDQS/LDQS cross point rising edge falling edge.
Clock Enable (KE)
When driven Low, VIL, Clock Enable input, used suspend Clock switch device Self Refresh, Power-Down Deep Power-Down mode. Clock Enable, must stable least clock cycle. This means that, level changes rising edge falling edge with setup time tAS, must same level next rising edge with hold time tAH.
2.10
Lower/Upper Data Input Mask (LDQM, UDQM)
Lower Data Input Mask Upper Data Input Mask input signals used mask data input during write operations. UDQM LDQM sampled when UDQS/LDQS level crosses VREF. When LDQM Low, VIL, inputs selected. When UDQM Low, VIL, DQ15 inputs selected.
2.11
Lower/Upper Data Read/Write Strobe Input/Output (LDQS, UDQS)
LDQS UDQS write data strobe input) read data strobe output) respectively. LDQS UDQS strobe signals DQ15, respectively. During read operations, device outputs data strobe through LDQS/UDQS pins simultaneously with data (see Figure 10). Data output both rising falling edge data strobe. During write operations, LDQS/UDQS should input strobe input data together with LDQM/UDQM (see Figure 18). inputs data should synchronized with high pulse LDQS/UDQS.
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M65KG526AB
Signal descriptions
2.12
supply voltage
provides power supply internal core memory device. main power supply operations (Read Write).
2.13
VDDQ supply voltage
VDDQ provides power supply pins enables Outputs powered independently VDD. VDDQ tied separate supply. recommended power-up power-down VDDQ together avoid certain conditions that would result data corruption.
2.14
ground
Ground, VSS, reference core power supply. must connected system ground.
2.15
VSSQ ground
VSSQ ground reference input/output circuitry driven VDDQ. VSSQ must connected VSS.
Note:
Each device system should have VDDQ decoupled with 0.1µF ceramic capacitor close (high frequency, inherently inductance capacitors should close possible package). Table Bank selection using BA0-BA1
Selected bank Bank Bank Bank Bank
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Commands
M65KG526AB
Commands
M65KG512AB recognizes commands that obtained specific statuses Chip Enable, Column Address Strobe, CAS, Address Strobe, RAS, Write Enable, address inputs. Refer Table Commands, conjunction with text descriptions below. Figure Simplified command state diagram shows operations that performed when each command issued each state LPSDRAM.
Mode Register command (MRS)
Mode Register command used configure Burst Length, Burst Type Latency device programming Mode Register. command issued with held High, with BA0, `0', RAS, driven Low, VIL. value address inputs determines Burst Length, Burst Type Latency device (see Table Mode Register definition Figure Mode Register/Extended Mode Register commands waveforms):
Burst Length words) programmed using address inputs A2-A0 Burst Type (sequential interleaved) programmed using Latency Clock cycles) programmed using A6-A4.
required execute Mode Register command Power-up sequence. Once command been issued, necessary wait least clock cycles before issuing another command.
Extended Mode Register command (EMRS)
Extended Mode Register command used configure low-power features device programming Extended Mode Register. command issued with held High, `0', `1', `0', driving RAS, Low, VIL. value address inputs determines Driver Strength, part array that refreshed during Self Refresh Automatic Temperature Compensated Self Refresh feature (see Table Extended Mode Register definition Figure Mode Register/Extended Mode Register commands waveforms):
part array refreshed (all banks, Bank Bank only) during Self Refresh using A2-A0. Driver Strength (full, strength, strength, strength) using bits A6-A5 Automatic temperature Compensated Self Refresh feature always enabled `0').
required execute Extended Mode Register command Powerup sequence. Once command been issued, necessary wait least clock cycles before issuing another command.
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M65KG526AB
Commands
Bank(Row) Activate command (ACT)
Bank(Row) Activate command used switch specific bank device from Idle active mode. bank selected (see Table Bank selection using BA0-BA1). This command initiated driving High, VIH, with Low, VIL, High. minimum delay tRCD required after issuing Bank (Row) Activate command prior initiating Read Write operations from active bank. minimum time required between Bank(Row) Activate commands same bank (see Figure Consecutive Bank(Row) Activate command).
Read command (READ)
Read command used read from memory array Burst Read mode. this mode, data output bursts synchronized with cross points clock signals, start address Burst Read determined column address, A12, bank address, BA0-BA1, beginning Burst Read operation. valid Read command initiated driving Low, VIL, High, VIH.
Read with Auto Precharge command (READA)
This command identical Read command except that precharge automatically performed Read operation. precharge starts tRPD (Burst Length/2 clock periods) after Read with Auto Precharge command input. tRAS(min) delay elapses between Bank (Row) Activate Auto Precharge commands. This lock-out mechanism allows Read with auto Precharge command issued bank that been activated (opened) satisfied tRAS(min) requirement. LPSDRAM supports Concurrent Auto Precharge mode: Read with autoprecharge followed command another active bank, long that command does interrupt read data transfer, that other related limitations apply (e.g. contention between read data written data must avoided). Table Minimum delay between commands concurrent Auto Precharge Mode shows minimum delays between Read with Auto Precharge command bank command different bank. Refer Figure description Read operation with Auto Precharge.
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Commands
M65KG526AB
Burst Read Terminate command (BST)
Burst Read Terminate command used terminate Burst Read operation. issued with held High, driving High. tBSTZ after issuing Burst Read Terminate command, DQ0-DQ15 LDQS, UDQS revert high impedance state (see Figure Burst Terminate during Read operation). There such command Burst Write operations.
Write command (WRIT)
This Write command used write memory array Burst Write mode. this mode, data input synchronized with cross points clock signals, start address Burst Write determined column address, address selected bank, BA0-BA1, beginning Burst Read operation. valid Write command initiated driving Low, VIL, High, VIH.
Write with Auto Precharge command (WRITA)
This command identical Write command except that precharge automatically performed Write operation. precharge starts tWPD (Burst Length/2 clock periods) after Write with Auto Precharge command input. Refer Figure description Write operation with Auto Precharge.
Precharge Selected Bank/Precharge Banks command (PRE/PALL)
Precharge Selected Bank Precharge Banks used place bank selected (see Table Bank selection using BA0-BA1) banks idle mode, respectively. precharge commands issued driving Low, with held High. value determines whether either selected bank banks will precharged:
High, BA0-BA1 Don't Care banks precharged. when, only bank selected BA0-BA1 precharged.
bank(s) is/are placed Idle mode after issuing Precharge command. Once bank Idle mode, Bank (Row) Activate command issued switch bank back active mode. precharge commands issued during Burst Read Burst Write which case Burst Read Write operation terminated selected bank placed Idle mode. device needs Idle mode before entering Self Refresh, Auto Refresh, PowerDown Deep Power-Down.
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M65KG526AB
Commands
3.10
Self Refresh Entry command (SELF)
Self Refresh Entry command used start Self Refresh operation. Before starting Self Refresh, device must idle. Self Refresh Entry command issued driving Low, with RAS, Low, High (see Figure Self Refresh Entry Exit commands waveforms). During Self Refresh operation, internal memory controller generated addresses refreshed. Self Refresh operation goes long Clock Enable signal, held Low.
3.11
Self Refresh Exit command (SELFX)
Self Refresh Exit command used exit from Self Refresh mode. There ways exit from Self Refresh mode:
Driving High, with High, RAS, Don't Care, Driving RAS, High.
Non-read commands executed 3tCK after Self Refresh operation, where Clock period Cycle time. Figure description Self Refresh Exit waveforms.
3.12
Auto Refresh command (REF)
This command performs Auto Refresh. device placed Auto refresh mode from Idle holding High, VIH, driving driving High. address bits "Don't Care" because addresses bank refreshed internally determined internal refresh controller. output buffer becomes High-Z after Auto Refresh started. Precharge operations automatically completed after Auto Refresh. Bank(Row) Activate, Mode Register Extended Mode Register command issued tRFC after last Auto Refresh command (see Figure Auto Refresh command waveforms). average refresh cycle tREF (see Table characteristics °C). optimize operation scheduling, flexibility absolute refresh interval provided. maximum eight Auto Refresh commands issued LPSDRAM maximum absolute interval between Auto Refresh commands 8tREF.
3.13
Power-Down Entry command (PDEN)
LPSDRAM caused enter Power-Down mode from Idle driving either:
High (other signals Don't Care), RAS, High with Low.
Power-Down mode continues long remains Low.
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Commands
M65KG526AB
3.14
Power-Down Exit command (PDEX)
LPSDRAM exits from Power-Down mode driving High.
3.15
Deep Power-Down Entry command (DPDEN)
device placed Deep Power-Down mode driving Low, with High (see Figure Deep Power-Down Entry command waveforms). banks must precharged idle state before entering Deep Power-Down mode. After command execution, device remains Deep Power-Down mode while low. Deep Power-Down Exit (DPDEX) M65KG512AB exits Deep Power-Down mode asserting High. special sequence then required before device take command into account: Maintain Operation status conditions minimum 200µs, Issue Precharge Banks command (see Section 3.9: Precharge Selected Bank/Precharge Banks command (PRE/PALL) details), Once banks precharged after minimum delay satisfied, issue more Auto Refresh commands, Issue Mode Register command initialize Mode Register bits, Issue Extended Mode Register command initialize Extended Mode Register bits.
Deep Power-Down mode exit sequence illustrated Figure Deep Power-Down Exit waveforms.
3.16
Device Deselect command (DESL)
When Chip Enable, High cross point Clock rising edge with VREF, input signals ignored device internal status held.
3.17
Operation command (NOP)
device placed Operation mode, driving CAS, High, with High. long this command input cross point Clock rising edge with VREF level, address data input ignored device internal status held.
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M65KG526AB Table Commands(1)(2)
Command Mode Register Extended Mode Register Bank (Row) Activate Read Read with Auto Precharge Burst Read Terminate Write Write with Auto Precharge Precharge Selected Bank Precharge Banks Self-Refresh Entry(8) Self Refresh Exit Auto Refresh(8) Power-Down Entry(8) Symbol KEn-1 EMRS READ READA WRIT WRITA PALL SELF SELFX PDEN V(6) X(7) V(6) X(7)
Commands
A0-A9, A11-A12 MR/EMR Data(3) MR/EMR Data(3)
Address Column Address Column VIL(4) VIH(4) VIL(6) VIH(7) VIL(4) VIH(5)
Power-Down Exit Deep Power-down Entry(8) Deep Power-down Exit
PDEX DPDEN DPDEX
Don't Care (VIL VIH); Valid Address Input. Clock Enable must stable least clock cycle. data value written Mode Register Extended Mode Register, respectively. Low, VIL, when issuing command, remains active operation. High, VIH, when issuing command, automatic precharge cycle performed operation reverts Idle mode. Low, VIL, when issuing command, only bank selected BA0-BA1 precharged (BA0-BA1 should valid). High, VIH, when issuing command, banks precharged BA0-BA1 Don't Care. banks must idle before executing this command.
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Commands Table
M65KG526AB Minimum delay between commands concurrent Auto Precharge Mode
command READ READA Minimum delay between commands concurrent Auto Precharge mode(1) BL/2 Latency (rounded BL/2 BL/2 tWTR BL/2 Unit
From command
READA
WRITE WRITEA READ READA
WRITEA
WRITE WRITEA
Burst Length.
Table
Burst Type Definition
Burst length words Sequential 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 Interleaved 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 Burst length words Burst length words
Burst length words Start addr. (A0SequenInterA3) tial leaved
Sequential 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
Interleaved 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
Sequential 0-1-2-.D-E-F 1-2-3.D-E-F-0 2-3-4.E-F-0-1 3-4-5.F-0-1-2 4-5-6.0-1-2-3 5-6-7.1-2-3-4 6-7-8.2-3-4-5 7-8-9.3-4-5-6 8-9-A.4-5-6-7 9-A-B.5-6-7-8 A-B-C.6-7-8-9 B-C-D.7-8-9-A C-D-E.8-9-A-B D-E-F.9-A-B-C E-F-0.A-B-C-D F-0-1.B-C-D-E
Interleaved 0-1-2-.D-E-F 1-0-3-.C-F-E 2-3-0- .F-C-D 3-2-1-.E-D-C 4-5-6-.9-A-B 5-4-7.8-B-A 6-7-4-.B-8-9 7-6-5-.A-9-8 8-9-A.5-6-7 9-8-A.4-7-6 A-B-8.7-4-5 B-A-9.6-5-4 C-D-E.1-2-3 D-C-F.0-3-2 E-F-C.3-0-1 F-E-D.2-1-0
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M65KG526AB Figure Simplified command state diagram
Commands
Extended Mode Register
Self Refresh
Mode Register
IDLE
Auto Refresh
Power-Down
Deep Power-Down
ACTIVE
PDEN PDEX
Active Power-Down
rite rech arge
Write
Read
recha
WRITE
Read
READ
WRITEA
atio
WRITEA
READA
POWER-ON
Precharge
Precharge
Automatic Sequence Manual Input Deep Power-Down Exit Sequence
ai11204b
READA
atio
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Operating modes
M65KG526AB
Operating modes
There operating modes that control memory. Each these composed sequence commands (see Table Operating modes summary).
Power-Up
LPSDRAM powered initialized well determined manner: After applying power VDDQ initial pause least 200µs required before signals toggled. Precharge command must then issued banks. Until command issued UDQM/LDQM must held High make sure that DQ0-DQ15 remain high impedance. after precharging banks, Mode Register Extended Mode Register must issuing Mode Register command Extended Mode Register command, respectively. minimum pause tMRD must respected after each register command. After registers configured, more auto Refresh cycles must executed before device ready normal operation.
third fourth steps swapped. Refer Figure detailed description Power-Up waveforms.
Burst Read
M65KG512AB switched Burst Read mode issuing Bank (Row) Activate command bank addresses read from, followed Read command (see Section 3.3: Bank(Row) Activate command (ACT) Section 3.4: Read command (READ) details). Burst Read accompanied Auto Precharge cycle depending state Address Input. High (set `1') when Burst Read command issued, Burst Read operation will followed Auto Precharge cycle. (set `0'), will remain active subsequent accesses. Burst Read operations performed word level only. Different Burst Types (sequential interleaved), Burst Lengths words) programmed using Mode Register bits. Only Latency clock cycles available. Refer Section 5.1, Section 3.1: Mode Register command (MRS), details Mode Register bits program them. Burst Read starts 2tCK after Clock rising edge where Read command latched, where Clock period access time from Data Strobe, UDQS/LDQS, output simultaneously with data. tRPRE prior first rising edge data strobe, UDQS/LDQS signals from High-Z state. This pulse referred Read Preamble. burst data then output synchronized with rising falling edge data strobe. UDQS/LDQS become High-Z next clock cycle after Burst Read completed. tRPST from last falling edge data strobe, pins become High-Z. This period referred Read Postamble.
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M65KG526AB
Operating modes
Table Table Table Figure Figure detailed description Burst Read operation characteristics. Burst Read terminated issuing Burst Read Terminate command (see Section 3.6: Burst Read Terminate command (BST) Section Figure 15.: Burst Terminate during Read operation). interval between Burst Read Burst Read Burst Read Burst Write commands described Figure Figure Figure
Burst Write
M65KG512AB switched Burst Write mode issuing Bank (Row) Activate command bank addresses written followed Write command (see Section 3.3: Bank(Row) Activate command (ACT) Section 3.7: Write command (WRIT) details). Burst Write accompanied Auto Precharge cycle depending state Address Input. High (set `1') when Write command issued, Write operation will followed Auto Precharge cycle. (set `0'), Auto Precharge selected will remain active subsequent accesses. Burst Write operations performed either byte word level. Latency Burst Write operations fixed clock cycle. UDQS/LDQS input strobe input data UDQM/LDQM select byte written. UDQS/LDQS must tWPRE prior their first rising edge; changed High-Z tWPST after their last falling edge. These periods time referred Write Preamble Write Postamble, respectively. Table Table Figure Figure Figure detailed description Burst Write waveforms characteristics. interval between Burst Write Burst Write commands described Figure Figure Figure Figure
Self Refresh
Self Refresh mode, data contained LPSDRAM memory array retained refreshed. size memory array refreshed programmed Extended Mode Register. Only data contained part array selected Self Refresh will retained refreshed. this respect, this power saving feature. Self Refresh mode entered exited issuing Self Refresh Entry Self Refresh Exit command, respectively (see Section Commands). When this mode, device clocked more. When Automatic Temperature Compensated Self Refresh mode (ATCSR) enabled, internal refresh adjusted according temperature order reduce power consumption.
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Operating modes
M65KG526AB
Auto Refresh
This command performs auto refresh memory array. bank addresses refreshed internally determined internal refresh controller. Issuing Auto Refresh command, caused device execute auto refresh (see Section Commands).
Power-Down
Power-Down mode, current reduced active standby current (IDD3P). Power-Down mode initiated issuing Power-Down Entry command. tPDEN clock cycle) after cycle when this command issued, LPSDRAM enters into Power-Down mode. Power-Down mode, power consumption reduced deactivating input initial circuit. There internal refresh when device Power-Down mode. device exit from Power-Down tPDEX cycle minimum) after issuing Power-Down Exit command. Section Commands details Power-Down Entry Exit commands.
Deep Power-Down
Deep Power-Down mode, power consumption reduced standby current (IDD7). Before putting device Deep Power-Down mode banks must Idle have been precharged. Deep Power-Down mode entered exited issuing Deep Power-Down Entry Deep Power-Down Exit command. Section Commands details Power-Down Entry Exit commands.
Table
Operating modes
KEn-1 VIL(2) VIL(2) A10, A0-A9 Start Column Address Start Column Address BA0-BA1 Bank Select Bank Select
Operating mode Burst Read Burst Write Self Refresh Auto Refresh Power-Down Deep Power-Down
Don't Care VIH. Burst Read Write operation followed Auto Precharge cycle. VIH, Burst Read Write operation followed Auto Precharge cycle bank selected BA0-BA1.
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M65KG526AB
Registers description
Registers description
Mobile mode registers, Mode Register Extended Mode register.
Mode Register description
Mode Register used select Latency, Burst Type, Burst Length device:
Latency defines number clock cycles after which first data will output during Burst Read operation. Burst Type specifies order which burst data will addressed. This order programmable either sequential interleaved (see Table Burst Type Definition). Burst Length number words that will output input during Burst Read Write operation. configured words.
Mode Register must programmed Power-Up sequence prior issuing command. loaded issuing Section 3.1: Mode Register command (MRS), with BA0-BA1 `00' select Mode Register. Table Mode Register definition shows available Mode Register configurations. Table
Address bits A12-A7 A6-A4
Mode Register definition
Mode Register MR6-MR4 Register description Latency Bits (Read Operations) Burst Type Interleaved words words words words Value 000000 Clock Cycles Description
Other configurations reserved Sequential
A2-A0
MR2-MR0
Burst Length
Other configurations reserved BA1-BA0
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Registers description
M65KG526AB
Extended Mode Register description
Extended Mode Register used program low-power Self Refresh operation device:
Partial Array Self Refresh Driver Strength Automatic Temperature Compensated Self Refresh.
loaded issuing Section 3.2: Extended Mode Register command (EMRS) with BA0-BA1 `01' select Extended Mode Register. Table Extended Mode Register definition shows available Extended Mode Register configurations. Table
Address bits A12-A10 A8-A7
Extended Mode Register definition
Mode Register EMR9 Description Value Enabled Reserved Description
Automatic Temperature Compensated Self Refresh Bits
Full Strength Strength Strength Strength
A6-A5
EMR6-EMR5
Driver Strength Bits
A4-A3
Banks Bank Bank (BA1=0) Bank (BA0
A2-A0
EMR2-EMR0
Partial Array Self Refresh Bits
Other configurations reserved BA1-BA0
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M65KG526AB
Maximum rating
Maximum rating
Stressing device above ratings listed Table Absolute maximum ratings, cause permanent damage device. These stress ratings only operation device these other conditions above those indicated Operating sections this specification implied. Exposure Absolute Maximum Rating conditions extended periods affect device reliability. Refer also STMicroelectronics SURE Program other relevant quality documents.
Table
Symbol
Absolute maximum ratings
Value Parameter Temperature range option 8(1) -0.5 -0.5 Unit
Junction Temperature Temperature range option 9(1) Storage Temperature Input Output Voltage Supply Voltage Short Circuit Output Current Power Dissipation
TSTG VDD, VDDQ
Table Ordering Information Scheme.
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parameters
M65KG526AB
parameters
This section summarizes operating measurement conditions, characteristics device. parameters characteristics Tables that follow, derived from tests performed under Measurement Conditions summarized Table Operating measurement conditions. Designers should check that operating conditions their circuit match measurement conditions when relying quoted parameters. Table
Symbol VDDQ(2) VREF(3) Supply voltage Input/Output supply voltage Load capacitance Input pulses voltages Input pulses voltages Input output timing ref. voltages Input differential voltage Input differential cross point voltage Input signal slew rate
Operating measurement conditions(1)
M65KG512AB Parameter VDDQ/2 VDDQ/2 with VDD=VDDQ V/ns Units
voltages referenced VSS. VDDQ must equal VDD. Generated internally.
Figure
measurement waveform
Clock Timing Reference Voltage Output Transition Timing Reference Voltage VDDQ VREF Input Transition Timing Voltage Input Signal Slew Rate
AI10238
VREF
26/54
M65KG526AB Figure measurement load circuit
parameters
Output
AI12451
Table
Symbol CI1(1)
Capacitance
M65KG512AB Parameter Signal Input capacitance other input pins Data capacitance DQ0-DQ15, UDQS/LDQS, LDQM/UDQM Delta Input capacitance other input pins 0.25 Unit
CIO(1)(2) CDI1(1) CDI2(1)
VDDQ MHz; VOUT VDDQ/2; VOUT Data Output disabled.
Table
Symbol VIH(2) VIL(3)
Characteristics
Parameter Input leakage current Output leakage current Input High voltage Input voltage Output voltage Output High voltage Input voltage level inputs Input differential cross point voltage inputs Input differential voltage inputs Test Condition(1) VDDQ VOUT VDDQ, DQ0-DQ15 disabled. IOUT IOUT -100 0.9VDDQ -0.3 0.4VDDQ 0.5VDDQ 0.4VDDQ VDDQ+0.3 0.6VDDQ VDDQ+0.6 -2.0 -1.5 0.8VDDQ -0.3 M65KG512AB Unit VDDQ+0.3 0.2VDDQ 0.1VDDQ
VDDQ VSSQ maximum value (pulse width ns). minimum value -0.5 (pulse width ns).
27/54
parameters Table characteristics 2(1)
M65KG526AB
M65KG512AB Symbol Parameter Test Condition 85°C 105°C Unit IDD1(2) IDD2P IDD2PS IDD2N Operating current Precharge Standby current Power-Down mode Burst length bank active tRC(min), VIL(max), tCK(min) VIL(max), (min), (min), tCK(min), Input signals changed once clock cycles. 10.0 90.0 90.0 Table
Precharge Standby current PowerDown mode
IDD2NS IDD3P IDD3PS IDD3N Active Standby current Power-Down mode
(min), Input signals stable VIL(max), tCK(min) VIL(max), (min), (min), tCK(min), Input signals changed once clock cycles. (min), Input signals stable (min), banks active, Burst Length tRRC tRRC (min)
Active Standby current Power-Down mode
IDD3NS IDD4(2) IDD5(3) IDD6 IDD7
Burst Mode current Auto Refresh current Self Refresh current
Standby current Deep (see Section 4.7: Deep PowerPower-down mode Down)
VDDQ 1.9V, VSSQ IDD1 IDD4 depend output loading cycle rates. Specified values measured with output open. Addresses change only once during tCK.
28/54
M65KG526AB Table Self Refresh current (IDD6) normal operating mode
Memory array(1) Temperature banks banks
parameters
banks
Unit
VDDQ VSSQ
Table
Symbol tAC(2) tAS(3)
characteristics(1)
M65KG512AB Parameter Data Output access time from Address Control Input setup time Address Control Input hold time Clock Cycle Time Autoprecharge write recovery precharge time UDQS/LDQS access time from Data Output LDQM/UDQM inputs pulse width UDQS/LDQS High-Z Time from UDQS/LDQS Low-Z time from UDQS/LDQS Data Output skew Data Input UDQM/LDQM setup time Data Input UDQM/LDQM hold time Addresses control pulse width Data Output High-Z time from Data Output Low-Z time from Data LDQS/UDQS Output hold time from Data hold skew factor Active Time (Bank (Row) Activate Bank Precharge) Cycle Time (Bank (Row) Activate Bank Activate Auto Refresh mode) Cycle Time (Auto Refresh Bank Active Auto Refresh mode) Delay Time, from Active active Delay Time, from Active Bank active tHP-tQHS 0.75 120000 tWR+tRP 1.75 0.65 Unit
tDAL tDQSCK(2) tDIPW tDQSHZ(4) tDQSLZ(6) tDQSQ(3) tDS(3) tDH(3) tIPW tOHZ(4) tOLZ(5) tQHS tRAS tRFC tRCD tRRD
29/54
parameters Table
Symbol tREF tSRE tSREX
M65KG526AB
characteristics(1) (continued)
M65KG512AB Precharge time Average Periodic Refresh time Self Refresh Exit Time Write Preamble setup time Parameter 22.5 Unit
tWPRES
above timings measured according test conditions shown Table Operating measurement conditions with driver strength "Full Strength" (EMR5 EMR6 `00'). These timings define signal transition delays from cross point, that when signal crosses VREF. timing reference level VREF. tOHZ tDQSHZ define transition time from Low-Z High-Z DQ0-DQ15 UDQS/LDQS, Burst Read operation, respectively. They specify when data outputs stop being driven. tOLZ tDQSLZ define transition time from High-Z Low-Z DQ0-DQ15 UDQS/LDQS, Burst Read operation. They specify when data outputs begin driven.
Table
characteristics(1)
M65KG512AB
Symbol
Parameter
133MHz
166MHz 1.75 tWR+tRP tHP-tQHS
Unit
tAC(2) tAS(3) tAH(3) tDQSCK(2) tDIPW tDQSHZ(4) tDQSLZ(6) tDQSQ(3) tDS(3) tDH(3) tDAL tIPW tOHZ(4) tOLZ(5) tQHS tRAS
Data Output access time from Address Control Input setup time Address Control Input hold time Clock Cycle Time UDQS/LDQS access time from Data Output LDQM/UDQM inputs pulse width UDQS/LDQS High-Z Time from UDQS/LDQS Low-Z time from UDQS/LDQS Data Output skew Data Input UDQM/LDQM setup time Data Input UDQM/LDQM hold time Data Input Valid Precharge command Addresses control pulse width Data Output High-Z from Data Output Low-Z from Data LDQS/UDQS Output hold time from Data hold skew factor Active Time (Bank (Row) Activate Bank Precharge)
0.65 2tCK+22.5 tHP-tQHS 0.75 120000
0.65 120000
30/54
M65KG526AB Table characteristics(1) (continued)
parameters
M65KG512AB Symbol Parameter 133MHz tRFC tRCD tRRD Cycle Time (Bank (Row) Activate Bank Activate Auto Refresh mode) Cycle Time (Auto Refresh Bank Active Auto Refresh mode) Delay Time, from Active active Delay Time, from Active Bank active Precharge time tREF Average Periodic Refresh time tSREX Self Refresh Exit Time Write Preamble setup time 1.95 1.95 37.5 22.5 166MHz Unit
tSRE
tWPRES
above timings measured according test conditions shown Table Operating measurement conditions with driver strength "Full Strength" (EMR5 EMR6 `00'). These timings define signal transition delays from cross point, that when signal crosses VREF. timing reference level VREF. tOHZ tDQSHZ define transition time from Low-Z High-Z DQ0-DQ15 UDQS/LDQS, Burst Read operation, respectively. They specify when data outputs stop being driven. tOLZ tDQSLZ define transition time from High-Z Low-Z DQ0-DQ15 UDQS/LDQS, Burst Read operation. They specify when data outputs begin driven.
Table
characteristics measured clock period
M65KG512AB
Symbol
Parameter
133MHz
166MHz
Unit
tBSTW(1) tBSTZ(1) tCHW tCLW tCKE tDMD tDSC tDQSS
Burst Read Terminate Command Write Command Delay Time Burst Read Terminate Command Data Output Hi-Z Clock High Pulse Width Clock Pulse Width Clock Enable pulse width UDQM/LDQM Data Input Latency LDQS/UDQS cycle time Write Command First UDQS/LDQS latching transition
0.45 0.45 0.75 1.25 0.55 0.55
0.55 0.55 1.25
0.45 0.45 0.75
31/54
parameters Table characteristics measured clock period (continued)
M65KG512AB Symbol Parameter 133MHz tDSS(4) tDSH(4) tDQSH tDQSL tDPE tDPX tMRD tPROZ(1) tRPD tRWD tRPRE tRPST tSRE tWPD tWRD tWCD UDQS/LDQS Falling Edge Setup Time UDQS/LDQS Falling Edge Hold Time from UDQS/LDQS High Pulse Width UDQS/LDQS Pulse Width tPDEN Power-Down Entry Time tPDEX Power-Down Exit Time Mode Register Cycle Time tHZP Precharge Command Data Output High-Z Delay Time from Read Precharge Command (same Bank) Delay Time from Read Write Command (all data output) Read Preamble Time Read Postamble Time tSREX Self Refresh Exit Time =-30 0.35 0.35 BL/2(2) 3+BL/2
M65KG526AB
166MHz 0.35 0.35 BL/2(2) 3+BL/2
Unit
3+BL/2
3+BL/2
Delay Time from Write Precharge Command (same Bank) Delay Time from Write Read Command (all data input) Write Command Data Input Latency Write Recovery Time Internal Write Read command Delay Write Preamble Data Strobe Pulse Width (Write Postamble) =-30 =-30
2+BL/2
2+BL/2
0.25 0.25
tWTR tWPRE tWPST(4)
Latency equals clock cycles. stands Burst Length. stands Burst Length. transition Low-Z High-Z occur when device outputs become floating. specific reference voltage given this document.
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M65KG526AB Figure Definition command address inputs timings
Command (RAS, CAS, Addresses
parameters
ai12455
Figure
Definition Read timings
Command
READ tOLZ(max) tOLZ(min) Hi-Z tOHZ(min) tOHZ(max)
DQ0-DQ15 (output) tDQSHZ(max) tDQSLZ(min) Hi-Z UDQS, LDQS tDQSLZ(max) tDQSHZ(min) Hi-Z
ai12456b
Figure
Definition Read timings
tAC(max) tAC(min) Hi-Z DQ0-DQ15 (Output) tDQSCK tDQSQ Hi-Z UDQS, LDQS tDSC
ai12457
Hi-Z
Hi-Z
33/54
parameters Figure
tRRD Command
M65KG526AB
Consecutive Bank(Row) Activate command
Address
BA0-BA1 Bank Active Bank Active
ai11210
Bank Active
Precharge Bank
above figure shows consecutive Bank(Row) Activate commands issued different banks. tRRD delay must respected between consecutive Bank(Row) Activate commands (ACT) different banks. destination already active, bank must precharged close row; command then issued after command. Consecutive commands same bank must issued interval separated Precharge command (PRE).
Figure Read followed Read same bank
Command
READ
READ
Address
Column Column
BA0-BA1 Read from Column DQ0-DQ15 Read from Column DOA0 DOA1 DOB0 DOB1 DOB2 DOB3
UDQS, LDQS
Bank Active Note: Burst Length Latency Bank Bank
Data Read from Column
Data Read from Column
ai11205
consecutive READ command must issued after minimum delay interrupt previous Read operation. issue consecutive READ different row, precharge bank (PRE) interrupt previous Read operation. after command, issue command. consecutive READ command issued tRCD after command.
34/54
M65KG526AB Figure Read followed Read different bank
parameters
Command
READ
READ
Address
Column Column
BA0-BA1 Read from Read from Column Column DQ0-DQ15 DOA0 DOA1 DOB0 DOB1 DOB2 DOB3
UDQS/ LDQS Bank Active Note: Burst Length Latency Bank Active Read from Read from Bank Bank Data Read from Bank Data Read from Bank
ai11206
consecutive Read operation targets active row, second READ command must issued after minimum delay interrupt previous Read operation. consecutive Read operation targets idle row, precharge bank (PRE) without interrupting previous Read operation. after command, issue command. consecutive READ command issued tRCD after command.
Figure Read with Auto Precharge
tRAS tRCD Command READA tRPD (min)
UDQS, LDQS tDQSCK DQ0-DQ15
Note: Burst Length
Start Internal Auto Precharge cycle
ai10586
35/54
parameters Figure Read followed Auto Precharge waveforms
tCHW tRAS tCLW
M65KG526AB
Address LDQM/ UDQM tDQSLZ LDQS/ UDQS tDQSQ DQ0-DQ15 Hi-Z
tRPRE
tRPST
tRCD
tAC, tDQSCK
tDQSHZ
Bank(Row) Activate Bank
Read from Bank
Precharge Bank
Bank(Row) Activate Bank
AI11212b
Burst Length words, Latency clock cycles.
36/54
M65KG526AB Figure Read operation (Burst lengths latency
tRCD Command READ
parameters
A0-A12 BA0-BA1
Address
Column Address tRPRE tRPST
UDQS, LDQS(1) tDQSCK DQ0-DQ15(1)
UDQS, LDQS(2)
DQ0-DQ15(2)
UDQS, LDQS(2)
DQ0-DQ15(2)
Notes: Burst Length Burst Length Burst Length cases, Latency
ai10552
Figure Burst Terminate during Read operation
t0.5 t1.5 t2.5 t3.5 t4.5 t5.5
Command
READ
tBSTZ
UDQS, LDQS
DQ0-DQ15
ai10585
37/54
parameters Figure Write followed Write same bank
M65KG526AB
Command
WRIT
WRIT
Address
Column Column
BA0-BA1
DQ0-DQ15
DIA0 DIA1 DIB0 DIB1 DIB2 DIB3
UDQS, LDQS
Bank Active Note: Burst Length Bank Bank
Data Written Column
Data Written Column
ai11207
consecutive WRIT command must issued after minimum delay interrupt previous Write operation. issue consecutive WRITE different row, precharge bank (PRE) interrupt previous Write operation. after command, issue command. consecutive WRIT command issued tRCD after command.
38/54
M65KG526AB Figure Write followed Write different bank
parameters
Command
tRCD
WRIT
WRIT
Address
Column Column
BA0-BA1
DQ0-DQ15
DIA0 DIA1
DIB0 DIB1 DIB2 DIB3
UDQS/ LDQS Bank Active Note: Burst Length Bank Active Data Read from Bank Data Read from Bank
ai11208b
consecutive Write operation targets active row, second WRIT command must issued after minimum delay interrupt previous Write operation. consecutive Write operation targets idle row, precharge bank (PRE) without interrupting previous Write operation. after command, issue command. consecutive WRIT command issued tRCD after command.
Figure Write operation with Auto Precharge
tRAS(min) tRCD Command WRITEA
UDQM, LDQM tWPD UDQS, LDQS
DQ0-DQ15
Start Internal Auto Precharge cycle
Note: Burst Length
ai10587c
39/54
parameters Figure Write with Auto Precharge Waveforms
tCHW tRAS tCLW
M65KG526AB
Address LDQM/ UDQM tDQSS LDQS/ UDQS tWPRE DQ0-DQ15 Hi-Z
IN+2 IN+3
tDIPW
tDQSL
tWPST tDSH
tRCD
tDIPW
tDQSH
Bank Active
Write Bank
Precharge Bank
Bank Active
AI11213d
Burst Length words, Latency clock cycle.
40/54
M65KG526AB Figure Write operation (Burst lengths latency
tRCD Command WRITE
parameters
A0-A12 BA0-BA1
Address
Column Address tWPRE
UDQS, LDQS(1) tWPRES DQ0-DQ15(1) tWPST UDQS, LDQS(2)
DQ0-DQ15(2)
UDQS, LDQS(2)
DQ0-DQ15(2)
Notes: Burst Length Burst Length Burst Length cases, Latency
ai10553
41/54
42/54
tCLW High tDQSS tDQSL tWPRE Hi-Z tWPST Hi-Z Lower Byte Read Upper Byte Read Upper Byte Write Upper Byte Write Lower Byte Write Read from Bank Upper Byte Read Upper Byte Read
AI11218b
tCHW
Burst Length words.
parameters
Address
LDQM
Figure Write waveforms (data masking using LDQM/UDQM)
UDQM
LDQS/ UDQS
DQ0-DQ7
DQ8-DQ15
M65KG526AB
Bank/Row Activate Read Bank from Bank
M65KG526AB
parameters
Figure Mode Register/Extended Mode Register commands waveforms
High tMRD
BA0-BA1
Address
Data
LDQM/ UDQM
LDQS/ Hi-Z UDQS
DQ0-DQ15 (OUT)
Hi-Z
Precharge (optionnal) Mode Register Bank Active Read Bank Precharge Bank
AI11214b
program Extended Mode Register, must respectively, Extended Mode Register Data. Data value written Mode Register.
43/54
parameters
M65KG526AB
Figure Read followed Write using Burst Read Terminate command (BST)
Command
READ
tBSTW tBSTZ)
WRIT
UDQM, LDQM tBSTZ DQ0-DQ15
UDQS, LDQS Data Output Note: Burst Length Latency (CL) Data Input
ai11209b
Write operation performed same bank than Read operation, Burst Read Terminate command (BST) must issued terminate Read operation.The WRIT command then issued tBSTW (StBSTW) after command. Write operation performed same bank different row, bank must precharged interrupt Read operation. after Precharge command, issue command. WRIT command then issued tRCD after command. Write operation performed different bank active row, sequence identical described Note Write operation performed different bank idle row, bank must precharged independently from Read operation. after Precharge command, issue command. WRIT command then issued tRCD after command.
44/54
M65KG526AB Figure Write followed Read (Write completed)
parameters
Command
WRIT
tWRDmin
READ
UDQM, LDQM
DQ0-DQ15
UDQS, LDQS Data Input Note: Burst Length Latency (CL) tWRD BL/2 clock cycles Data Output
ai10838b
Read operation performed same bank than Write operation, READ command should performed tWRD after WRIT command complete Write operation. Read operation performed same bank different row, bank must precharged tWPD after Write operation. after Precharge command, issue command. READ command then issued tRCD after command. Read operation performed different bank active row, sequence identical described Note Read operation performed different bank idle row, bank must precharged independently from Write operation. after Precharge command, issue command. WRIT command then issued tRCD after command.
45/54
parameters Figure Write followed Read same Bank (Write Interrupted)
M65KG526AB
Command
WRIT
READ
UDQM, LDQM
DQ0-DQ15
UDQS, LDQS Data Input Masked Note: Burst Length Latency (CL)
ai10839
Data Output
UDQM/LDQM must input clock cycle prior READ command prevent invalid data from being written. READ command input next cycle after WRIT command, UDQM/LDQM necessary. Read operation issued different same bank, idle different bank, Precharge command (PRE) must issued before READ command. this case, Read operation does interrupt Write operation. Read operation issued different bank, active row, sequence identical described Note
46/54
M65KG526AB
High Clock Cycle needed tMRD tMRD Refresh Cycles needed
Figure Power-Up sequence
Address High
Data
Data
LDQM/ UDQM
DQ0-DQ15 Hi-Z tRFC Auto Refresh tRFC Bank(Row) Activate
AI11211b
Data data values written Mode Register Extended Mode Register, respectively.
Precharge Banks Mode Extended Mode Register Register Auto Refresh
parameters
47/54
parameters Figure Auto Refresh command waveforms
High tm+1 tm+2 tm+3 tm+4 tm+5 tm+6
M65KG526AB
tm+7
tm+8
tm+9
Address LDQM/ UDQM
LDQS/ UDQS DQ0-DQ15 (OUT)
Hi-Z Hi-Z
DQ0-DQ15 (IN)
Hi-Z Precharge (optional) Auto Refresh tRFC Bank Active Read from Bank
AI11215b
Burst Length words, Latency clock cycles.
48/54
M65KG526AB Figure Self Refresh Entry Exit commands waveforms
tCKE tn+1 tn+2
parameters
tm+1 tm+2
tm+3 tm+4
tm+5
Address
LDQM/ UDQM Hi-Z
UDQS/ LDQS DQ0-DQ15 (OUT) DQ0-DQ15 (IN)
Hi-Z Hi-Z Precharge (optional) Self Refresh Entry Self Refresh Exit tSRE Bank Active Read Bank
ai11216c
Burst Length words.
49/54
parameters Figure Deep Power-Down Entry command waveforms
M65KG526AB
UDQM/ LDQM DQ0-DQ15 Hi-Z Precharge Banks Deep Power-Down Entry
ai10847b
BA0, address bits (except A10) `Don't Care'. Upper Lower Data Input Mask signals, UDQM LDQM Low, VIL.
50/54
M65KG526AB
Clock Cycle needed Refresh Cycles needed tMRD tMRD
High Level nedeed
Figure Deep Power-Down Exit waveforms
Address
Data
Data
High
LDQM/ UDQM
DQ0-DQ15 Hi-Z tRFC Auto Refresh tRFC Bank/Row Activate
AI11217b
200µs
Data data values written Mode Register Extended Mode Register, respectively.
Precharge Banks Mode Extended Mode Auto Refresh Register Register
parameters
Deep Power-Down Exit
51/54
Part numbering
M65KG526AB
Part numbering
Table
Example:
Ordering Information Scheme
M65KG512AB
Device Type Low-Power SDRAM
Architecture Bare
Operating Voltage VDDQ LPSDRAM, Array Organization Banks Mbit
Number Chip Enable Inputs Chip Enable
Version B-Die
Speed 7.5ns (Clock frequency MHz) 6.0ns (Clock frequency MHz)
Delivery Form Wafer form
Temperature Range °C(1)
Only available with speed class MHz.
list available options (Speed, Package, etc.) further information aspect this device, please contact Sales Office nearest you.
52/54
M65KG526AB
Revision history
Revision history
Table
Date 31-Jan-2006
Document revision history
Revision Initial release. Speed class 166MHz added. Temperature range 85°C changed 85°C, associated speed class 7.5ns (133MHZ). Temperature range 105°C added both 6.0ns (166MHz) 7.5ns (133MHz). Figure Simplified command state diagram updated. Ambient temperature changed junction temperature Table Absolute maximum ratings, Table characteristics Table Self Refresh current (IDD6) normal operating mode, Table characteristics Table characteristics Table characteristics measured clock period, updated accordingly. Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure updated. speed classes temperature range options added Table Ordering Information Scheme. Section 2.10: Lower/Upper Data Input Mask (LDQM, UDQM) Section 2.11: Lower/Upper Data Read/Write Strobe Input/Output (LDQS, UDQS) modified. Section 3.3: Bank(Row) Activate command (ACT) Section 3.5: Read with Auto Precharge command (READA) updated. Column address updated Section 3.7: Write command (WRIT), Section 4.2: Burst Read Section 4.3: Burst Write. Interval between Auto Refresh commands modified Section 3.12: Auto Refresh command (REF). Table updated Note removed. Section 4.2: Burst Read, Section 4.4: Self Refresh Section 4.5: Auto Refresh updated. tSRE added Table Table Figure Figure Figure Figure Figure updated. Changes
04-Sep-2006
01-Feb-2007
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M65KG526AB
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512Mbit banks supply, power SDRAM 512Mbit Synchronous Dynamic Org

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