N-CHANNEL 9.2m DPAK/IPAK STripFETIII Power MOSFET Type STD50N03L
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STD50N03L STD50N03L-1
N-CHANNEL 9.2m DPAK/IPAK STripFETIII Power MOSFET
Type STD50N03L STD50N03L-1
VDSS
RDS(on) 10.5m 10.5m
RDS(on)*Qg industry's benchmark Conduction losses reduced Switching losses reduced threshold device
IPAK
DPAK
Description
This product utilizes latest advanced design rules ST's proprietary STripFETtechnology. This suitable most demanding DC-DC converter application where high efficiency achieved.
Internal schematic diagram
Applications
Switching applications
Order codes
Part number STD50N03L STD50N03L-1 Marking D50N03L D50N03L Package DPAK IPAK Packaging Tape reel Tube
October 2006
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www.st.com
Contents
STD50N03L STD50N03L-1
Contents
Electrical ratings Electrical characteristics
Electrical characteristics (curves)
Test circuit
Package mechanical data Packaging mechanical data Revision history
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STD50N03L STD50N03L-1
Electrical ratings
Electrical ratings
Table
Symbol
Absolute maximum ratings
Parameter Drain-source voltage (VGS Gate-source voltage Drain current (continuous) 25°C Drain current (continuous) TC=100°C Drain current (pulsed) Total dissipation 25°C Derating factor Value Unit W/°C
PTOT EAS(3) Tstg
Single pulse avalanche energy Operating junction temperature Storage temperature
Limited wire bonding Pulse width limited safe operating area Starting 25°C, =20A, =15V
Table
Symbol RthJ-Case RthJ-Amb
Thermal data
Parameter Thermal resistance junction-case Thermal resistance junction-ambient Maximum lead temperature soldering purpose Value Unit °C/W °C/W
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Electrical characteristics
STD50N03L STD50N03L-1
Electrical characteristics
(TCASE=25°C unless otherwise specified) Table
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS Gate body leakage current (VDS Gate threshold voltage Static drain-source resistance Test conditions 250µA, VGS= 30V, Tc=125°C ±20V VDS= VGS, 250µA VGS= 10V, VGS= 0.012 10.5 0.019 Min.
±100
Typ.
Max.
Unit
Table
Symbol Ciss Coss Crss QOSS
Dynamic
Parameter Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Output charge Test conditions =25V, f=1MHz, VGS=0 VDD= 15V, (see Figure f=1MHz Gate Bias Bias=0 Test signal Level=20mV open drain Min. Typ. 1434 10.4 12.6 Max. Unit
Gate input resistance
QOSS=COSS*D Vin; COSS= Cgd. Appendix
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STD50N03L STD50N03L-1
Electrical characteristics
Table
Symbol td(on) td(off)
Switching times
Parameter Turn-on delay time Rise time Test conditions VDD=15V, 25A, 4.7, VGS= 4.5V (see Figure VDD= 15V, 25A, 4.7, VGS= 4.5V (see Figure Min. Typ. Max. Unit
Turn-off delay time Fall time
Table
Symbol ISDM(1) VSD(2) IRRM IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward voltage Reverse recovery time Reverse recovery charge Reverse recovery current Reverse recovery time Reverse recovery charge Reverse recovery current ISD= 20A, VGS=0 ISD= 40A, di/dt 100A/µs, VDD= 25°C (see Figure ISD= 40A, di/dt 100A/µs, VDD= 10V, 150°C (see Figure 15.6 26.4 18.1 Test conditions Min. Typ. Max. Unit
Pulse width limited safe operating area Pulsed: pulse duration=300µs, duty cycle 1.5%
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Electrical characteristics
STD50N03L STD50N03L-1
Figure
Electrical characteristics (curves)
Safe operating area Figure Thermal impedance
Figure
Output characteristics
Figure
Transfer characteristics
Figure
Normalized BVDSS temperature
Figure
Static drain-source resistance
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STD50N03L STD50N03L-1 Figure Gate charge gate-source voltage Figure
Electrical characteristics Capacitance variations
Figure
Normalized gate threshold voltage temperature
Figure Normalized resistance temperature
Figure Source-drain diode forward characteristics
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Test circuit
STD50N03L STD50N03L-1
Test circuit
Figure Gate charge test circuit
Figure Switching times test circuit resistive load
Figure Test circuit inductive load Figure Unclamped Inductive load test switching diode recovery times circuit
Figure Unclamped inductive waveform
Figure Switching time waveform
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STD50N03L STD50N03L-1
Buck converter
Appendix
Buck converter
Figure Power losses estimation
power losses associated with FETs Synchronous Buck converter estimated using equations shown table below. formulas give good approximation, sake performance comparison, different pairs devices affect converter efficiency. However very important parameter, working temperature, considered. real device behavior really dependent heat generated inside devices removed allow safer working junction temperature. side (SW2) device requires:
Very RDS(on) reduce conduction losses Small Qgls reduce gate charge losses Small Coss reduce losses output capacitance Small reduce losses during turn-on Cgd/Cgs ratio lower than Vth/Vgg ratio especially with drain source voltage avoid cross conduction phenomenon; Small allow higher gate current peak limit voltage feedback gate Small have faster commutation reduce gate charge losses
high side (SW1) device requires:
RDS(on) reduce conduction losses.
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Buck converter Table Power losses
High side switching (SW1)
STD50N03L STD50N03L-1
side switch (SW2)
Pconduction
DS(on)SW1
DS(on)SW2
Pswitching
gsth(SW1) gd(SW1)
Zero Voltage Switching
Recovery
applicable
rr(SW2)
Pdiode Conduction applicable
Vf(SW2) deadtime gls(SW2)
oss(SW2)
Pgate(QG)
g(SW1)
PQoss
oss(SW1)
Dissipated during turn-on
Table
Paramiters meaning
Meaning Duty-cycle Post threshold gate charge Third quadrant gate charge state losses On-off transition losses Conduction reverse recovery diode losses Gate drive losses Output capacitance losses
Parameter Qgsth Qgls Pconduction Pswitching Pdiode Pgate PQoss
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STD50N03L STD50N03L-1
Package mechanical data
Package mechanical data
order meet environmental requirements, offers these devices ECOPACK® packages. These packages have Lead-free second level interconnect category second level interconnect marked package inner label, compliance with JEDEC Standard JESD97. maximum ratings related soldering conditions also marked inner label. ECOPACK trademark. ECOPACK specifications available www.st.com
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Package mechanical data
STD50N03L STD50N03L-1
TO-251 (IPAK) MECHANICAL DATA
DIM. MIN. 0.45 0.48 15.9 0.95 16.3 0.017 0.019 0.236 0.252 0.173 0.626 0.354 0.031 0.031 0.64 TYP. MAX. 0.85 0.012 0.037 0.023 0.023 0.244 0.260 0.181 0.641 0.370 0.047 0.039 MIN. 0.086 0.035 0.027 0.025 0.204 inch TYP. MAX. 0.094 0.043 0.051 0.031 0.212 0.033
0068771-E
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STD50N03L STD50N03L-1
Package mechanical data
DPAK MECHANICAL DATA
DIM. MIN. (L1) 0.03 0.64 0.45 0.48 2.28 9.35 0.023 0.008 10.1 0.173 0.368 0.039 0.110 0.031 0.039 0.252 0.185 0.090 0.181 0.397 MAX. 0.23 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.200 0.260 TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 inch
0068772-F
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Packaging mechanical data
STD50N03L STD50N03L-1
Packaging mechanical data
DPAK FOOTPRINT
dimensions millimeters
TAPE REEL SHIPMENT
REEL MECHANICAL DATA
DIM. 12.8 20.2 16.4 22.4 18.4 13.2 MIN. MAX. 0.059 0.504 0.520 0.795 0.645 0.724 1.968 0.881 BULK 2500 inch MIN. MAX. 12.992
TAPE MECHANICAL DATA
DIM.
BASE 2500
MIN. 10.4 1.65 2.55
15.7 16.3
inch MIN. MAX. 0.267 0.275 0.409 0.417 0.476 0.059 0.063 0.059 0.065 0.073 0.291 0.299 0.100 0.108 0.153 0.161 0.311 0.319 0.075 0.082 1.574
0.618 0.641
MAX. 10.6 12.1 1.85 2.75
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STD50N03L STD50N03L-1
Revision history
Revision history
Table
Date 31-Jul-2006 27-Oct-2006
Revision history
Revision Initial release. Modified Figure Safe operating area page Changes
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STD50N03L STD50N03L-1
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