N-channel 0.009 DPAK gate charge STripFETII Power MOSFET Type STD

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N-channel 0.009 DPAK gate charge STripFETII Power MOSFET Type STD

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STD40NF3LL
N-channel 0.009 DPAK gate charge STripFETII Power MOSFET
Type STD40NF3LL
VDSS
RDS(on) <0.011
Logic level device Optimal RDS(on) trade-off Conduction losses reduced Switching losses reduced threshold drive
DPAK
Description
This application specific Power MOSFET third generation STMicroelectronics unique "Single Feature SizeTM" strip-based process. resulting transistor shows best trade-off between on-resistance gate charge. When used high side buck regulators, gives best performance terms both conduction switching losses. This extremely important motherboards where fast switching high efficiency paramount importance.
Internal schematic diagram
Applications
Switching application
Order codes
Part number STD40NF3LLT4 Marking D40NF3LL@ Package DPAK Packaging Tape reel
February 2007
1/13
www.st.com
Contents
STD40NF3LL
Contents
Electrical ratings Electrical characteristics
Electrical characteristics (curves)
Test circuit
Package mechanical data Packing mechanical data Revision history
2/13
STD40NF3LL
Electrical ratings
Electrical ratings
Table
Symbol VDGR ID(1)
Absolute maximum ratings
Parameter Drain-source voltage (VGS Drain-gate voltage (RGS Gate- source voltage Drain current (continuous) 25°C Drain current (continuous) 100°C Drain current (pulsed) Total dissipation 25°C Derating Factor Value 0.53 Max. operating junction temperature Unit W/°C V/ns
Ptot
dv/dt
Peak diode recovery voltage slope Single pulse avalanche energy Storage temperature
Tstg
Current limited package Pulse width limited safe operating area. 40A, di/dt 350A/µs, V(BR)DSS, TJMAX Starting 20A,
Table
Rthj-case Rthj-amb
Thermal data
Thermal resistance junction-case Thermal resistance junction-ambient Maximum lead temperature soldering purpose 1.88 °C/W °C/W
3/13
Electrical characteristics
STD40NF3LL
Electrical characteristics
(TCASE=25°C unless otherwise specified) Table
Symbol V(BR)DSS
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS Gate-body leakage current (VDS Gate threshold voltage Static drain-source resistance Test conditions 250µA, rating rating, 125°C ±16V VGS, 250µA 10V, 4.5V, 0.0090 0.0115 0.0110 0.0135 Min. ±100 Typ. Max. Unit
IDSS
IGSS VGS(th) RDS(on)
Table
Symbol Ciss Coss Crss td(on) td(off)
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Total gate charge Gate-source charge Gate-drain charge Test conditions 15V, Min. Typ. 1650 Max. Unit
25V, 1MHz,
15V, =4.5V (see Figure 15V, 20A, 4.5V, (see Figure
Pulsed: Pulse duration duty cycle 1.5%.
4/13
STD40NF3LL
Electrical characteristics
Table
Symbol ISDM IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward voltage 40A, Test conditions Min. Typ. Max. Unit
Reverse recovery time 40A, di/dt 100A/µs, Reverse recovery charge 15V, 150°C Reverse recovery current (see Figure
Pulse width limited safe operating area. Pulsed: Pulse duration duty cycle 1.5%
5/13
Electrical characteristics
STD40NF3LL
Figure
Electrical characteristics (curves)
Safe operating area Figure Thermal impedance
Figure
Output characteristics
Figure
Transfer characteristics
Figure
Transconductance
Figure
Static drain-source resistance
6/13
STD40NF3LL Figure Gate charge gate-source voltage Figure
Electrical characteristics Capacitance variations
Figure
Normalized gate threshold voltage temperature
Figure Normalized resistance temperature
Figure Source-drain diode forward characteristics
Figure Normalized breakdown voltage temperature
7/13
Test circuit
STD40NF3LL
Test circuit
Figure Gate charge test circuit
Figure Switching times test circuit resistive load
Figure Test circuit inductive load Figure Unclamped Inductive load test switching diode recovery times circuit
Figure Unclamped inductive waveform
Figure Switching time waveform
8/13
STD40NF3LL
Package mechanical data
Package mechanical data
order meet environmental requirements, offers these devices ECOPACK® packages. These packages have Lead-free second level interconnect. category second level interconnect marked package inner label, compliance with JEDEC Standard JESD97. maximum ratings related soldering conditions also marked inner label. ECOPACK trademark. ECOPACK specifications available www.st.com
9/13
Package mechanical data
STD40NF3LL
DPAK MECHANICAL DATA
DIM. MIN. (L1) 0.03 0.64 0.45 0.48 2.28 9.35 0.023 0.008 10.1 0.173 0.368 0.039 0.110 0.031 0.039 0.252 0.185 0.090 0.181 0.397 MAX. 0.23 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.200 0.260 TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 inch
0068772-F
10/13
STD40NF3LL
Packing mechanical data
Packing mechanical data
DPAK FOOTPRINT
dimensions millimeters
TAPE REEL SHIPMENT
REEL MECHANICAL DATA
DIM. 12.8 20.2 16.4 22.4 18.4 13.2 MIN. MAX. 0.059 0.504 0.520 0.795 0.645 0.724 1.968 0.881 BULK 2500 inch MIN. MAX. 12.992
TAPE MECHANICAL DATA
DIM.
BASE 2500
MIN. 10.4 1.65 2.55
15.7 16.3
inch MIN. MAX. 0.267 0.275 0.409 0.417 0.476 0.059 0.063 0.059 0.065 0.073 0.291 0.299 0.100 0.108 0.153 0.161 0.311 0.319 0.075 0.082 1.574
0.618 0.641
MAX. 10.6 12.1 1.85 2.75
11/13
Revision history
STD40NF3LL
Revision history
Table
Date 21-Jun-2004 11-Jul-2006 20-Feb-2007
Revision history
Revision Changes datasheet according DSG/CT/2C13 marking:D40NF3LL@ template, content change Typo mistake page
12/13
STD40NF3LL
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N-channel 0.009 DPAK gate charge STripFETII Power MOSFET Type STD

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