SST88VP1107 SST79LF008 Notebook System Controller with Mbit Firmw

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SST88VP1107 SST79LF008 Notebook System Controller with Mbit Firmw

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All-in-OneMemory
SST88VP1107
SST79LF008 Notebook System Controller with Mbit Firmware Flash
FEATURES:
All-in-OneMemory: Managed Memory Subsystem Code Data Single Package Execute-in-place (XIP) Non-volatile area area Pseudo-NOR(PNORTM) area High-speed Pseudo-NOR (High-speed PNOR) area area Memory-mapped (mATA) NAND Disk area Factory Default Memory Configuration KByte (fixed) High-speed PNOR KByte (re-configurable) PNOR MByte (re-configurable) MByte (re-configurable) mATA MByte (re-configurable) Simple Host Interface Standard PSRAM interface areas 16-bit with required WAIT function Asynchronous/Synchronous Single-access Read/Write cycles Synchronous operation 80MHz Page Mode Burst Mode support Highspeed PNOR, PNOR, areas Burst length Words 4Mbit Built-in SuperFlash® Standard interface operation Fast erase program with SuperFlash Immediately available upon power-up Active deep power-down mode Configurable High-speed PNOR PNOR Full address range emulated using cache NAND non-volatile storage Configurable memory area size optimize NAND usage code data storage Built-in cache controller provides cache coherence without host intervention Configurable cache size optimum performance usage Dynamic Paging optimum memory usage Static Paging minimum access latency Built-in NAND controller provides Flash File System (FFS) without host intervention Standard PSRAM MWord (128Mbit) host Memory-Mapped (mATA) NAND Disk Area Gbit data storage host Standard protocol with cycles decoded memory space Built-in NAND controller performs NAND Disk function Fast Asynchronous Access Time NOR: High-speed PNOR: initial, page access PNOR: initial, page access RAM: initial, page access mATA: Read/Write Performance NOR: Read: MBytes/sec, Write: KBytes/sec High-speed PNOR (cache-hit): Read: MBytes/sec, Write: MBytes/sec PNOR (cache-hit): Read:120 MBytes/sec, Write:130 MBytes/sec RAM: Read:120 MBytes/sec, Write: MBytes/sec mATA: Read: MBytes/sec, Write: MBytes/sec Protection Security Area Secure Boot capability Word unique enhanced security KWord hardware bottom boot block protection KWord Time Programmable (OTP) protected areas 64-bit password protection Superior NAND Flash Management Superior data integrity through robust hardware Corrects random errors NAND Built-in Microcontroller with intelligent firmware Flash File System embedded SuperFlash Periodic Refresh ensure NAND data integrity Wear-leveling prolong product life Multi-tasking technology boost NAND flash performance Efficient Power Management Unit Immediate disabling unused circuitry Fast boot time from power-down Power Consumption Active Mode current: (typical) Stand-by Mode curent: (typical) Deep Power-down mode current: (typical) 1.8V 3.0V Power Supplies Host Interface Voltage Selection Through VDDQ 1.8V 3.0V Temperature Range +70°C commercial operation -25°C +85°C wireless operation Package Available 80-Ball Low-Profile Ball Grid Array (LBGA) 10x13mm non-Pb (lead-free) devices RoHS Compliant
©2007 Silicon Storage Technology, Inc. S71354(01)-00-000 07/07
logo, SuperFlash, FlashFlex registered trademarks Silicon Storage Technology, Inc. These specifications subject change without notice.
All-in-OneMemory SST88VP1107
Area
Direct Mapped Dedicated KWord (4Mb) SuperFlash Performance-critical Code Data Standard Interface Operation Immediately Available upon Power-On Available Deep Power-Down Mode Asynchronous Single-access Read/Write Mode access time Synchronous Single-access Read/Write Mode 80MHz cycles initial latency Read cycles initial latency Write Super Fast Word Program (typical) Super Fast Sector-Erase Capability Uniform KWord sectors Sector-Erase Time: (typical) Super Fast Block-Erase Capability Uniform KWord blocks Block-Erase Time: (typical) Area-Erase Capability Area-Erase Time: (typical) Erase-Suspend /-Resume Capability Read while Erase-Suspend Program while Erase-Suspend JEDEC Standard Compliant Flash EEPROM command sets Optional Two-Cycle Command Mode End-of-Write detection Supports both toggle bits data polling Secure Boot Capability Hardware Bottom Boot Block Protection through NWP# Input KWord bottom boot-block protection KWord user-programmable areas
Word Security-ID SST: Word User: Word Volatile Non-volatile Block Protection 64-bit Password Protection Superior Reliability with SuperFlash Endurance: Minimum 100,000 cycles (typical) Greater than years data retention
Pseudo-NORArea
Emulates memory using PSRAM NAND Offers access Area size configurable MWord Built-in cache controller Flash File System Automatically loads on-demand page from NAND flash cache Improved NAND Reliability with Cache Minimizes Read Disturb Errors Extends Write Endurance Standard PSRAM Interface Operation with Required Wait Function Uniform KWord cache page size Four configurable regions regions combined total size MWord Each region size MWord Each region served configurable PSRAM cache zone Four configurable PSRAM cache zones Four cache zones combined total size MWord Each cache zone size MWord Cache zone Host-configurable Options Cache Operations Static Dynamic Paging modes Asynchronous Single-access Read/Write Mode access time Asynchronous Page-Read Mode page read time Synchronous Burst Read/Write Mode 80MHz cycles initial latency Read cycles initial latency Write
©2007 Silicon Storage Technology, Inc.
S71354(01)-00-000
07/07
All-in-OneMemory SST88VP1107
High-Speed Pseudo-NOR Area
Emulating High-speed Memory Using SRAM NAND without Host Intervention Offers access Area size configurable MWord Built-in cache controller Flash File System Automatically loads on-demand page from NAND flash cache Improved NAND Reliability with Cache Minimizes Read Disturb Errors Extends Write Endurance Standard PSRAM Interface Operation with Wait Function Embedded KWord High-speed SRAM Cache Uniform KWord Cache Page Size Configurable Region MWord Region served cache zone highspeed SRAM Cache zone Host-configurable Options Cache Operations Static dynamic paging modes Asynchronous Single-access Read/Write Mode access time Asynchronous Page Read Mode page read time Synchronous Burst Read/Write Mode 80MHz cycles initial latency Read cycles initial latency Write
Area
Standard PSRAM Interface Operation Served portion PSRAM used PNOR Cache Zones MWord (128Mbit) space Asynchronous Single-access Read/Write Mode access time Asynchronous Page-Read Mode page read time Synchronous Burst Read/Write Mode cycles Initial latency Read cycles Initial latency Write
Memory-Mapped NAND Disk Area
Standard Protocol with Cycles Decoded Memory Space Task File Registers Memory-Mapped Built-in NAND controller performs NAND Disk Function MWord Gbit) mass storage space Asynchronous Single-access Read/Write Mode access time Synchronous Single-Access Read/Write Mode 80MHz cycles Initial latency Read/Write Word address space Task File Registers Word address space Data Registers Performance optimized Controller Fast Wake-up Time Standby Read/Write: (typical)
©2007 Silicon Storage Technology, Inc.
S71354(01)-00-000
07/07
All-in-OneMemory SST88VP1107
PRODUCT DESCRIPTION
SST88VP1107 reliable, high-performance, singlepackage, managed memory subsystem code data storage that easy use. Designed embedded applications including mobile phones portable consumer electronics, this product provides all-in-one memory solution through unique capability configure various memory resources. Providing code storage (NOR), data storage (NAND), system (PSRAM) functions single bus, SST88VP1107 well suited manufacturers need high density memory with enhanced performance, superior quality, reliability. All-in-OneMemory includes boot Flash, NAND controller, Cache controller, high-speed SRAM, PSRAM, NAND Flash memory Multi Chip Package (MCP). embedded Flash offers fast boot time, provides many advanced data protection features secure boot code protection. dedicated, performanceoptimized NAND controller provides efficient data integrity, defect management, wear-leveling combining robust hardware Error Correction Code (ECC) sophisticated Flash File System (FFS) embedded SuperFlash® memory. built-in cache controller provides both static dynamic paging modes, with controller-managed, cache-coherence operations. SST88VP1107 utilizes advantages both NAND flash memories attain faster Read, Program, Erase operations. This unified code data storage solution allows host configure memory-area cache sizes optimum memory utilization. All-in-OneMemory highly configurable. host device define variety memory configurations using following areas: direct mapped high-performance Mbit boot memory area, directly addressable Pseudo-NOR memory areas emulated NAND, directly addressable host memory area, performance optimized mass storage area. Through advanced data protection features, All-inOneMemory provides robust embedded security. boot area comes pre-programmed with Word unique security greater system security, program additional Word which creates unique Word security addition, boot area offers added security through KWord hardware bottom bootblock protection, KWord Time Programmable (OTP) secure areas, volatile block protection, non-volatile block protection, password protection. SST88VP1107 offers built-in Flash File System (FFS) that makes NAND flash memory management transparent host system. This eliminates need
©2007 Silicon Storage Technology, Inc. S71354(01)-00-000 07/07
software host, reduces software development effort time. also provides efficient defect management effective wear-leveling algorithms ensure even NAND flash media, which extend longevity storage device. hardware Error Correction Code (ECC) module ensures superior data integrity reliability using advanced algorithm correct random errors both NAND flash. built-in cache High-speed PNOR PNOR areas improves reliability these areas. Having cache front NAND flash helps reduce read disturb errors minimizing repeated direct read access page NAND flash. built-in cache also helps extend endurance storage device minimizing direct write access NAND flash. SST88VP1107 offered both commercial wireless temperature ranges 80-Ball LBGA package. Figure assignments Table descriptions.
All-in-OneMemory SST88VP1107
FUNCTIONAL BLOCKS
All-in-OneMemory Boot Cache Controller Embedded Flash File System
Host
Host
Controller
High-Speed SRAM
PSRAM
NAND Flash Interface
Controller
Buffer
NAND Flash
1354 B1.0
FIGURE
1-1: Functional Block Diagram
©2007 Silicon Storage Technology, Inc.
S71354(01)-00-000
07/07
All-in-OneMemory SST88VP1107
ASSIGNMENTS
assignments SST88VP1107 shown Figure below. descriptions Table 2-1. active signals have suffix "#." buffer types listed Table 2-2.
VIEW (balls facing down)
SCIDI
VDDP VDDN SCICLK
VSSIO DQ15 DQ14 VSSIO SCIDO
HRST# VREG DQ13 DQ11
NWP# WAIT RY/CRST# DQ12
VSSIO VSSIO DQ10
VDDQ VDDP
CE1# CE2# CE0# CE3# ADV# CE4#
1354 80-lbga-LBS P1.0
FIGURE
2-1: Assignments 80-ball LBGA
©2007 Silicon Storage Technology, Inc.
S71354(01)-00-000
07/07
All-in-OneMemory SST88VP1107
Descriptions
pins functions each shown Table 2-1. TABLE
Symbol Host Interface HRST# RY/CRST# Clock Input Synchronous Mode Hardware Reset Input (active low) Ready/CPU Reset#. Indicates host system that device power-up initialization reset. host this output signal Ready signal host Reset signal. logic high state indicates that device ready normal operations. Active high when used Ready signal active when used Reset. Chip Enable area (active low) Chip Enable High-speed PNOR, PNOR, areas 3-Chip-Enable mode. (factory default) Must tied high 3-Chip-Enable Mode (factory default). Used other Chip Enable Modes. (active low) Must tied high 3-Chip-Enable Mode (factory default). Used other Chip Enable Modes. (active low) Chip Enable memory-mapped (mATA) area (active low) Host Configuration Register Enable (active high) Address Valid (active low) Output Enable (active low) Write Enable (active low) Upper Byte Select (active low) Lower Byte Select (active low) Write Protect Input area. Protects Bottom Boot Block from Erase/Program operations (active low) WAIT signal. When asserted, indicates host system that output data valid during read operations that input data will latched device during write operations. mATA areas, WAIT output signal should ignored Asynchronous Mode. polarity WAIT output signal configured (default active high). mATA area Interrupt Request Host
2-1: Descriptions
Location Type Type Name Functions
CE0# CE1# CE2# CE3#
CE4# ADV# NWP# WAIT
©2007 Silicon Storage Technology, Inc.
S71354(01)-00-000
07/07
All-in-OneMemory SST88VP1107
Fact Sheet TABLE
Symbol DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
2-1: Descriptions (Continued)
Location Type Type Bi-directional Host Data [15:0] Host Address [25:0]. This word address Name Functions
©2007 Silicon Storage Technology, Inc.
S71354(01)-00-000
07/07
All-in-OneMemory SST88VP1107
Fact Sheet TABLE
Symbol Debug Interface SCICLK SCIDI SCIDO Misc. VREG Power PWR1 Internal voltage regulator output. external ceramic capacitor (4.7µF) must connected between this system ground. Power Host Interface (1.8V/3.0V) Power PSRAM (1.8V) Power NAND Flash (3.0V) Power core logic (3.0V) core logic
T2-1.1 1354(01)
2-1: Descriptions (Continued)
Location Type (PD) (PU) Type I_PD1 I_PU1 Name Functions Serial Interface Clock Input use. Reserved use. Reserved Serial Interface Data Input use. Reserved Serial Interface Data Output use. Reserved
Power Ground VDDQ VDDP VDDN VSSIO Power Power Power Power Ground Ground PWR1 PWR1 PWR1 PWR1 PWR1 PWR1
TABLE
2-2: Input/Output (I/O) Buffer Types
Buffer Type I_PU1 I_PD1 PWR1 Description Input buffer1 Input buffer with internal pull-up Input buffer with internal pull-down Output buffer buffer Output buffer with tri-state Power Ground
T2-2.0 1354(01)
configured input without internal pull-up pull-down resistor must left unconnected.
©2007 Silicon Storage Technology, Inc.
S71354(01)-00-000
07/07
All-in-OneMemory SST88VP1107
DEVICE ELEMENTS
All-in-OneMemory contains boot flash, microcontroller, embedded flash file system (FFS), cache controller, controller, PSRAM, NAND flash integrated LBGA package. This device five different memory areas: NOR, High-speed Pseudo-NOR (Highspeed PNOR), Pseudo-NOR (PNOR), RAM, memorymapped (mATA). host memory write data read data from, these five different memory areas. default configuration chip enables with Highspeed PNOR, PNOR, sharing chip enable. Refer Figure All-in-OneMemory block diagram. All-in-OneMemory interfaces with host system through standard PSRAM interface, supporting both asynchronous read/write synchronous read/write operations. area directly mapped flash available boot access immediately after power-up initialization. Similarly, area directly mapped partition internal PSRAM. High-speed PNOR PNOR areas, two-way associative cache controller moves pages between NAND flash high-speed SRAM High-speed PNOR, PSRAM PNOR area. This built-in cache controller supports both static dynamic paging modes. mATA area, All-in-OneMemory converts standard protocols into flash media data control signals performs Flash File System operations translate host logical address NAND physical address. components that contribute All-in-OneMemory operations described Sections 3.16.
Boot
boot flash used store boot code time-critical code data. boot area available host access immediately after power-up initialization, supports minimum page size KWord.
Embedded Flash File System (FFS)
embedded Flash File System (FFS) integral part All-in-OneMemory flash memory, handling data transfers from NAND flash. controllerembedded flash memory stores firmware FFS, allows quicker firmware upgrades, required. performs following tasks: Translates host side operations into flash memory Read Write operations Increases longevity providing wear-leveling evenly distribute Write actions across entire NAND memory Performs NAND flash bad-block management Keeps track data structure Manages system security selected protection zones
Cache Controller
built-in cache controller manages access Highspeed PNOR PNOR areas. cache controller uses two-way associative caching scheme improve cache rate. cache controller supports both static dynamic paging modes with Word page size. cache coherence operations complete managed cache controller without host intervention. However, host issue page flush cache commands through device control interface, required.
Microcontroller Unit (MCU)
32-bit Microcontroller Unit manages internal operations All-in-OneMemory translating host commands into data control signals required internal memory operations.
Controller
controller interface high-speed SRAM PSRAM memories.
Host Interface
Write operations, host interface receives control signals data from host directs them host-selected memory area. Read operations, host interface receives control signals from host drives data from host-selected memory area host bus.
High-speed SRAM
KWord cache zone, Zone serves High-speed PNOR area. KWord high-speed SRAM used cache Zone cache zone.
©2007 Silicon Storage Technology, Inc.
S71354(01)-00-000
07/07
All-in-OneMemory SST88VP1107
PSRAM
PSRAM divided into partitions whose size configurable host. partition cache PNOR area cache zones which served four size-configurable cache zones-Zone through Zone other partition available host system RAM.
3.15 Power Management Unit (PMU)
Power Management Unit (PMU) handles power consumption All-in-OneMemory. dramatically reduces power consumption automatically putting circuitry that being used operation into standby mode.
Controller
controller supports standard protocols, receives commands from host interface. This controller moves data from host interface buffer Write commands, from buffer host interface Read commands.
3.16 Serial Communication Interface (SCI)
additional manufacturing flexibility, used device configuration error reporting. This consists active signals: SCICLK, SCIDI, SCIDO. strongly recommends providing access device interface system level during development manufacturing.
3.10 Buffer
contributor mATA area performance SRAM buffer. This Word buffer optimizes data transfers from NAND flash media, beginning transfer when buffer contains Words.
3.11 NAND Flash Interface
multi-tasking NAND flash interface enables fast, sustained write performance allowing multiple Read, Program, Erase operations several flash media chips planes.
3.12 Error Correction Code (ECC)
hardware Error Correction Code (ECC) module utilizes advanced algorithm which corrects random errors both NAND flash.
3.13 NAND Flash
NAND flash used non-volatile storage media High-speed PNOR, PNOR, mATA areas. size each area configurable host.
3.14 Direct Memory Access (DMA)
SST88VP1107 uses internal engine instant data transfer between NAND flash High-speed SRAM, PSRAM, buffer. This implementation eliminates microcontroller overhead associated with traditional firmware-based approach results increased data transfer rates.
©2007 Silicon Storage Technology, Inc.
S71354(01)-00-000
07/07
All-in-OneMemory SST88VP1107
SYSTEM INTERFACE
Figure simplified interface diagram that shows All-in-OneMemory connected host through standard PSRAM interface. complete list interface signals, detailed description their functions, please Table 2-1.
1.8V/3V VDDQ WAIT RY/CRST# ADV# A[25:0] D[15:0] CE[4:0]# NWP# HRST# VSSIO
1.8V VDDP
VDDN
SST88VP1107
VREG 4.7µF
1354 F2-2.0
FIGURE
4-1: All-in-OneMemory System Interface Diagram
©2007 Silicon Storage Technology, Inc.
S71354(01)-00-000
07/07
All-in-OneMemory SST88VP1107
PRODUCT ORDERING INFORMATION
1107 XXXX Environmental Attribute non-Pb (pure Package Modifier balls Package Type LBGA Operation Temperature Commercial: +70°C Wireless: -25°C +85°C Endurance 100,000 Cycles Frequency PSRAM Density Mbit NAND Flash Density Gbit Function/Core PSRAM Host Interface Voltage 3.6V Product Series All-in-OneMemory
Environmental suffix denotes non-Pb solder. non-Pb solder devices "RoHS Compliant".
Valid Combinations
Valid combinations SST88VP1107 SST88VP1107-80-5C-LBSE SST88VP1107-80-5W-LBSE Note: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2007 Silicon Storage Technology, Inc.
S71354(01)-00-000
07/07
All-in-OneMemory SST88VP1107
PACKAGE DIAGRAMS
VIEW
13.0 ±0.1
BOTTOM VIEW
0.50 0.05 (80X)
10.0 ±0.1
CORNER
CORNER
DETAIL VIEW
1.31 ±0.09
SIDE VIEW
SEATING PLANE
0.15 0.40 0.05
Note:
Although many dimensions similar those JEDEC Publication MO-210, this specific package registered. linear dimensions millimeters. Coplanarity: 0.15 Ball opening size 0.05
80-lbga-LBS-10x13-0.0
FIGURE
6-1: 80-Ball Low-Profile Ball Grid Array (LBGA) 10mm 13mm Package Code:
TABLE
6-1: Revision History
Description Date 2007
Number
Initial Release
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2007 Silicon Storage Technology, Inc. S71354(01)-00-000 07/07

SST88VP1107 SST79LF008 Notebook System Controller with Mbit Firmw

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