SST49LF008A SST49LF008A8 Firmware Intel Chipsets FEATURES:

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Mbit Firmware
SST49LF008A
SST49LF008A8 Firmware Intel Chipsets
FEATURES:
Firmware Intel Chipsets Mbit SuperFlash memory array code/data storage 1024K Flexible Erase Capability Uniform KByte Sectors Uniform KByte overlay blocks KByte Boot Block protection Chip-Erase Mode Only Single 3.0-3.6V Read Write Operations Superior Reliability Endurance:100,000 Cycles (typical) Greater than years Data Retention Power Consumption Active Read Current: (typical) Standby Current: (typical) Fast Sector-Erase/Byte-Program Operation Sector-Erase Time: (typical) Block-Erase Time: (typical) Chip-Erase Time: (typical) Byte-Program Time: (typical) Chip Rewrite Time: seconds (typical) Single-pulse Program Erase Internal timing generation Operational Modes Firmware Interface (FWH) Mode In-System operation Parallel Programming (PP) Mode fast production programming Firmware Hardware Interface Mode 5-signal communication interface supporting byte Read Write clock frequency operation TBL# pins provide hardware write protect entire chip and/or Boot Block Block Locking Register blocks Standard Command Data# Polling Toggle End-of-Write detection pins system design flexibility pins multi-chip selection Parallel Programming (PP) Mode 11-pin multiplexed address 8-pin data interface Supports fast In-System PROM programming manufacturing CMOS Compatibility Packages Available 32-lead PLCC 32-lead TSOP (8mm 14mm) 40-lead TSOP (10mm 20mm) Non-Pb (lead-free) packages available non-Pb (lead-free) devices RoHS compliant
PRODUCT DESCRIPTION
SST49LF008A flash memory devices designed read-compatible with Intel 82802 Firmware (FWH) device PC-BIOS application. These devices provide protection storage update code data addition adding system design flexibility through five general purpose inputs. interface modes supported SST49LF008A: Firmware (FWH) Interface mode in-system programming Parallel Programming (PP) mode fast factory programming PC-BIOS applications. SST49LF008A flash memory devices manufactured with SST's proprietary, high performance SuperFlash technology. split-gate cell design thick-oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST49LF008A devices significantly improve performance reliability, while lowering power consumption.
©2006 Silicon Storage Technology, Inc. S71161-11-000 3/06
SST49LF008A devices write (Program Erase) with single 3.0-3.6V power supply. They less energy during Erase Program than alternative flash memory technologies. total energy consumed function applied voltage, current time application. Since given voltage range, SuperFlash technology uses less current program shorter Erase time, total energy consumed during Erase Program operation less than alternative flash memory technologies. SST49LF008A products provide maximum ByteProgram time µsec. entire memory erased programmed byte-by-byte typically seconds when using status detection features such Toggle Data# Polling indicate completion Program operation. SuperFlash technology provides fixed Erase Program times independent number Erase/ Program cycles performed. Therefore system software
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. Intel registered trademark Intel Corporation. These specifications subject change without notice.
Mbit Firmware SST49LF008A
Data Sheet hardware does have calibrated correlated cumulated number Erase/Program cycles necessary with alternative flash memory technologies, whose Erase Program time increase with accumulated Erase/ Program cycles. protect against inadvertent write, SST49LF008A devices employ hardware software data (SDP) protection schemes. offered with typical endurance 100,000 cycles. Data retention rated greater than years. meet high density, surface mount requirements, SST49LF008A devices offered 32-lead TSOP package. addition, SST49LF008A offered 32lead PLCC 40-lead TSOP packages. Figures assignments Table descriptions.
TABLE CONTENTS
PRODUCT DESCRIPTION LIST FIGURES LIST TABLES. FUNCTIONAL BLOCK DIAGRAM ASSIGNMENTS DEVICE MEMORY DESIGN CONSIDERATIONS PRODUCT IDENTIFICATION MODE SELECTION FIRMWARE (FWH) MODE Device Operation Firmware Interface Cycles. Abort Mechanism Response Invalid Fields. Device Memory Hardware Write Protection Reset. Write Operation Status Detection Data# Polling (DQ7) Toggle (DQ6) Multiple Device Selection REGISTERS General Purpose Inputs Register Block Locking Registers Write Lock Lock Down JEDEC Registers
©2006 Silicon Storage Technology, Inc. S71161-11-000 3/06
Mbit Firmware SST49LF008A
Data Sheet PARALLEL PROGRAMMING MODE Device Operation Reset. Read Byte-Program Operation Sector-Erase Operation Block-Erase Operation Chip-Erase Write Operation Status Detection Data Protection SOFTWARE COMMAND SEQUENCE ELECTRICAL SPECIFICATIONS Characteristics Characteristics (FWH Mode). Characteristics Mode) PRODUCT ORDERING INFORMATION. PACKAGING DIAGRAMS
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
LIST FIGURES
FIGURE Functional Block Diagram FIGURE Assignments 32-lead TSOP (8mm 14mm) FIGURE Assignments 32-lead PLCC FIGURE Assignments 40-lead TSOP FIGURE Device Memory SST49LF008A FIGURE Single-Byte Read Waveforms FIGURE Write Waveforms FIGURE Waveform. FIGURE Reset Timing Diagram FIGURE Output Timing Parameters. FIGURE Input Timing Parameters FIGURE Reset Timing Diagram Mode) FIGURE Read Cycle Timing Diagram Mode) FIGURE Write Cycle Timing Diagram Mode) FIGURE Data# Polling Timing Diagram Mode) FIGURE Toggle Timing Diagram Mode) FIGURE Byte-Program Timing Diagram Mode) FIGURE Sector-Erase Timing Diagram Mode) FIGURE Block-Erase Timing Diagram Mode) FIGURE Chip-Erase Timing Diagram Mode) FIGURE Software Entry Read Mode) FIGURE Software Exit Reset Mode) FIGURE Input/Output Reference Waveforms Mode) FIGURE Test Load Example Mode) FIGURE Byte-Program Algorithm. FIGURE Wait Options FIGURE Software Product Command Flowcharts FIGURE Erase Command Sequence. FIGURE 32-lead Plastic Lead Chip Carrier (PLCC) Package Code: FIGURE 32-lead Thin Small Outline Package (TSOP) 14mm Package Code: FIGURE 40-lead Thin Small Outline Package (TSOP) 10mm 20mm Package Code:
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
LIST TABLES
TABLE Description. TABLE Product Identification TABLE Read Cycle TABLE Write Cycle TABLE General Purpose Inputs Register. TABLE Block Locking Registers SST49LF008A. TABLE Block Locking Register Bits TABLE Operation Modes Selection Mode) TABLE Software Command Sequence TABLE Operating Characteristics (All Interfaces) TABLE Recommended System Power-up Timings TABLE Impedance TABLE Reliability Characteristics. TABLE Clock Timing Parameters. TABLE Read/Write Cycle Timing Parameters, =3.0-3.6V (FWH Mode) TABLE Input/Output Specifications, =3.0-3.6V (FWH Mode) TABLE Reset Timing Parameters, =3.0-3.6V (FWH Mode) TABLE Interface Measurement Condition Parameters TABLE Read Cycle Timing Parameters, =3.0-3.6V Mode) TABLE Program/Erase Cycle Timing Parameters, =3.0-3.6V Mode) TABLE Reset Timing Parameters, =3.0-3.6V Mode) TABLE Revision History
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
FUNCTIONAL BLOCK DIAGRAM
TBL# INIT#
X-Decoder
FWH[3:0] FWH4 ID[3:0] FGPI[4:0] R/C# A[10:0] DQ[7:0]
SuperFlash Memory
Interface
Address Buffers Latches Y-Decoder
Control Logic
Buffers Data Latches
Programmer Interface
RST#
1161 B1.2
FIGURE Functional Block Diagram
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
ASSIGNMENTS
(VSS) (IC) (FGPI4) R/C# (CLK) (VDD) RST# (RST#) (FGPI3) (FGPI2) (FGPI1) (FGPI0) (WP#) (TBL#)
Standard Pinout View
1161 32-tsop P1.0
(INIT#) (FWH4) (VDD) (RES) (RES) (RES) (RES) (FWH3) (VSS) (FWH2) (FWH1) (FWH0) (ID0) (ID1) (ID2) (ID3)
Designates Mode
FIGURE Assignments 32-lead TSOP (8mm 14mm)
RST# (RST#)
A7(FGPI1) (FGPI0) (WP#) (TBL#) (ID3) (ID2) (ID1) (ID0) (FWH0)
(VDD)
(FGPI2)
(FGPI3)
(FGPI4)
R/C# (CLK)
(IC) (VSS) (VDD) (INIT#) (FWH4) (RES)
32-lead PLCC View
(FWH1) (FWH2) (FWH3) (RES) (RES) (RES) (VSS)
1161 32-plcc P2.3
Designates Mode
FIGURE Assignments 32-lead PLCC
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
(NC) (IC) (NC) (NC) (NC) (NC) (FGPI4) (NC) R/C# (CLK) (NC) RST# (RST#) (NC) (NC) (FGPI3) (FGPI2) (FGPI1) (FGPI0) (WP#) (TBL#)
Standard Pinout View
(FWH4) (INIT#) (NC) (RES) (RES) (RES) (RES) (NC) (FWH3) (FWH2) (FWH1) (FWH0) (ID0) (ID1) (ID2) (ID3)
Designates Mode
1232 40-tsop P1.0
FIGURE Assignments 40-lead TSOP
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Data Sheet TABLE Description
Interface Symbol A10-A0 Name Address Type1 Functions Inputs low-order addresses during Read Write operations. Addresses internally latched during Write cycle. programming interface, these addresses latched R/C# share same pins high-order address inputs. output data during Read cycles receive input data during Write cycles. Data internally latched during Write cycle. outputs tri-state when high. gate data output buffers control Write operations This determines which interface operational. When held high, programmer mode enabled when held low, mode enabled. This must setup power-up before return from reset change during device operation. This internally pulled- down with resistor between 20-100 This second reset in-system use. This internally combined with RST# pin; this RST# driven low, identical operation exhibited. These four pins part mechanism that allows multiple parts attached same bus. strapping these pins used identify component.The boot device must have ID[3:0]=0000 recommended that subsequent devices should sequential up-count strapping. These pins internally pulled-down with resistor between 20-100 These individual inputs used additional board flexibility. state these pins read through GPI_REG register. These inputs should their desired state before start clock cycle during which read attempted, should remain place until Read cycle. Unused pins must floated. When low, prevents programming Boot Block sectors memory. When TBL# high disables hardware write protection block sectors. This cannot left unconnected. Communications provide clock input control unit Input Communications reset operation device When low, prevents programming highest addressable blocks. When high disables hardware write protection these blocks. This cannot left unconnected. Select Programming interface, this determines whether address pins pointing addresses, column addresses. These pins must left unconnected. provide power supply (3.0-3.6V) Circuit ground reference) pins must grounded. Unconnected pins
T1.4 1161
DQ7-DQ0
Data
Output Enable Write Enable Interface Configuration
INIT#
Initialize
ID[3:0]
Identification Inputs
FGPI[4:0] General Purpose Inputs
TBL#
Block Lock
FWH[3:0] I/Os FWH4 RST# Clock Input Reset Write Protect
R/C#
Row/Column Select
Reserved Power Supply Ground Connection
Input, Output
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
DEVICE MEMORY
TBL#
Block Block Block Block Block Block Block Block
0FFFFFH
Boot Block
0F0000H 0EFFFFH 0E0000H 0DFFFFH 0D0000H 0CFFFFH 0C0000H 0BFFFFH 0B0000H 0AFFFFH 0A0000H 09FFFFH 090000H 08FFFFH
Block 0~14
080000H 07FFFFH Block 070000H 06FFFFH Block 060000H 05FFFFH Block 050000H 04FFFFH Block 040000H 03FFFFH Block 030000H 02FFFFH Block Block 020000H 01FFFFH 010000H 00FFFFH Block KByte) 002000H 001000H 000000H
KByte Sector
KByte Sector KByte Sector KByte Sector
1161 F08.0
FIGURE Device Memory SST49LF008A
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
DESIGN CONSIDERATIONS
recommends high frequency ceramic capacitor placed close possible between less than away from device. Additionally, frequency electrolytic capacitor from should placed within pin. socket programming purposes additional 1-10 next each socket. RST# must remain stable entire duration Erase operation. must remain stable entire duration Erase Program operations non-Boot Block sectors. write data Boot Block sectors, TBL# must also remain stable entire duration Erase Program operations.
mode, device configured interface with host using Intel's Firmware proprietary protocol. Communication between Host SST49LF008A occurs 4-bit communication signals, [3:0] FWH4. mode, device programmed 11bit address 8-bit data parallel signals. address inputs multiplexed column selected control signal R/C# pin. column addresses mapped higher internal addresses, addresses mapped lower internal addresses. Device Memory Figure address assignments.
FIRMWARE (FWH) MODE Device Operation
PRODUCT IDENTIFICATION
product identification mode identifies device SST49LF008A manufacturer SST. TABLE Product Identification
JEDEC Address Location FFBC0000H FFBC0001H
T2.7 1161
mode uses 5-signal communication interface, FWH[3:0] FWH4, control operations SST49LF008A. Operations such Memory Read Memory Write uses Intel propriety protocol. JEDEC Standard (Software Data Protection) Byte-Program, Sector-Erase Block-Erase command sequences incorporated into memory cycles. Chip-Erase only available Mode. device enters standby mode when FWH4 high internal operation progress. device ready mode when FWH4 activity bus.
Byte Manufacturer's Device SST49LF008A 0001H 0000H
Data
Firmware Interface Cycles
Addresses data transferred from SST49LF008A series "fields," where each field contains bits data. SST49LF008A supports only singlebyte Read Write, fields clock cycle length. Field sequences contents strictly defined Read Write operations. Addresses this section refer addresses seen from SST49LF008A's "point view," some calculation will required translate these actual locations memory (and vice versa) multiple memory devices used bus. Tables list field sequences Read Write cycles.
MODE SELECTION
SST49LF008A flash memory devices operate distinct interface modes: Firmware Interface (FWH) mode Parallel Programming (PP) mode. (Interface Configuration pin) used interface mode selection. logic High, device mode; while Low, device mode. selection must configured prior device operation. internally pulled down connected.
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Data Sheet TABLE Read Cycle
Clock Cycle Field Name START Field Contents FWH[3:0]1 1101 FWH[3:0] Direction Comments FWH4 must active (low) part respond. Only last start field (before FWH4 transitions high) should recognized. START field contents indicate memory Read cycle. Indicates which device should respond. IDSEL select) field matches value ID[3:0], then that particular device will respond whole cycle. These seven clock cycles make 28-bit memory address. YYYY nibble entire address. Addresses transferred most-significant nibble first. field this size indicates many bytes will transferred during multi-byte operations. SST49LF008A will only support single-byte operation. IMSIZE=0000b this clock cycle, master (Intel ICH) driven then float `1's then floats bus, prior next clock cycle. This first part "turnaround cycle." SST49LF008A takes control during this cycle. During next clock cycle, will driving "sync data." During this clock cycle, will generate "readysync" (RSYNC) indicating that least-significant nibble least-significant byte will available during next clock cycle. YYYY least-significant nibble least-significant data byte. YYYY most-significant nibble least-significant data byte. this clock cycle, SST49LF008A driven ones then floats prior next clock cycle. This first part "turnaround cycle." master (Intel ICH) resumes control during this cycle.
T3.3 1161
IDSEL
0000 1111
IMADDR
YYYY
IMSIZE
0000 byte)
TAR0
1111
then Float
TAR1 RSYNC
1111 (float) 0000 (READY)
Float then
DATA DATA TAR0
YYYY YYYY 1111
then Float Float then
TAR1
1111 (float)
Field contents valid rising edge present clock cycle.
FWH4 FWH[3:0]
IMADDR RSYNC DATA
1161 F09.0
FIGURE Single-Byte Read Waveforms
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Data Sheet TABLE Write Cycle
Clock Cycle Field Name START Field Contents FWH[3:0]1 1110 FWH[3:0] Direction Comments FWH4 must active (low) part respond. Only last start field (before FWH4 transitions high) should recognized. START field contents indicate memory Read cycle. Indicates which SST49LF008A device should respond. IDSEL select) field matches value ID[3:0], then that particular device will respond whole cycle. These seven clock cycles make 28-bit memory address. YYYY nibble entire address. Addresses transferred most-significant nibble first. This size field indicates many bytes will transferred during multi-byte operations. only supports single-byte writes. IMSIZE=0000b This field least-significant nibble data byte. This data either data programmed into flash memory valid flash command. This field most-significant nibble data byte. this clock cycle, master (Intel ICH) driven then float `1's then floats prior next clock cycle. This first part "turnaround cycle." SST49LF008A takes control during this cycle. During next clock cycle will driving "sync" data. SST49LF008A outputs values 0000, indicating that received data flash command. this clock cycle, SST49LF008A driven then float `1's then floats prior next clock cycle. This first part "turnaround cycle." master (Intel ICH) resumes control during this cycle.
T4.4 1161
IDSEL
0000 1111
IMADDR
YYYY
IMSIZE
0000 byte)
DATA
YYYY
DATA TAR0
YYYY 1111
then Float
TAR1
1111 (float)
Float then
RSYNC TAR0
0000 1111
then Float
TAR1
1111 (float)
Float then
Field contents valid rising edge present clock cycle.
FWH4 FWH[3:0]
IMADDR DATA RSYNC 1161 F10.0
FIGURE Write Waveforms
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Abort Mechanism
FWH4 driven more clock cycles during cycle, cycle will terminated device will wait ABORT command. host drive FWH[3:0] with `1111b' (ABORT command) return device Ready mode. abort occurs during Write operation, data incorrectly altered.
TBL# internally OR'ed with Boot Block Locking register. When TBL# low, Boot Block hardware write protected regardless state WriteLock Boot Block Locking register. Clearing Write-Protect register when TBL# will have functional effect, even though register indicate that block longer locked. internally OR'ed with Block Locking register. When low, blocks hardware write protected regardless state Write-Lock corresponding Block Locking registers. Clearing Write-Protect register when will have functional effect, even though register indicate that block longer locked.
Response Invalid Fields
During operations, will explicitly indicate that received invalid field sequences. response specific invalid fields sequences follows: Address range: address sequence fields long bits), only last five address fields bits) will decoded SST49LF008A. Address special function directing reads writes flash core (A22=1) register space (A22=0). Invalid IMSIZE field: receives invalid size field during Read Write operation, device will reset operation will attempted. SST49LF008A will generate kind response this situation. Invalidsize fields Read/Write cycle anything 0000b.
Reset
INIT# RST# initiates device reset. INIT# RST# pins have same function internally. required drive INIT# RST# pins during system reset ensure proper initialization. During Read operation, driving INIT# RST# pins deselects device places output drivers, FWH[3:0], high-impedance state. reset signal must held minimal duration time TRSTP. reset latency will occur reset procedure performed during Program Erase operation. Table Reset Timing Parameters more information. device reset during active Program Erase will abort operation memory contents become invalid data being altered corrupted from incomplete Erase Program operation.
Device Memory Hardware Write Protection
Boot Lock (TBL#) Write Protect (WP#) pins provided hardware write protection device memory SST49LF008A. TBL# used write protect boot sectors KByte) highest flash memory address range SST49LF008A. write protects remaining sectors flash memory. active signal TBL# prevents Program Erase operations boot sectors. When TBL# held high, write protection boot sectors then determined Boot Block Locking register. serves same function remaining sectors device memory. TBL# pins write protection functions operate independently another. Both TBL# pins must their required protection states prior starting Program Erase operation. logic level change occurring TBL# during Program Erase operation could cause unpredictable results. TBL# pins cannot left unconnected.
Write Operation Status Detection
SST49LF008A device provides software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-of-Write detection mode incorporated into Read cycle. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid.
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Data# Polling (DQ7)
When SST49LF008A device internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. Note that even though have valid data immediately following completion internal Write operation, remaining data outputs still invalid: valid data entire data will appear subsequent successive Read cycles after interval During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Proper status will given using Data# Polling address invalid range.
General Purpose Inputs Register
GPI_REG (General Purpose Inputs Register) passes state FGPI[4:0] pins power-up SST49LF008A. recommended that FGPI[4:0] pins desired state before FWH4 brought beginning cycle, remain that state until cycle. There default value since this pass-through register. register boot device appears FFBC0100H GByte system memory map, will appear elsewhere device boot device. Register available read when device Erase/Program operation. Table GPI_REG bits function. TABLE General Purpose Inputs Register
Toggle (DQ6)
During internal Program Erase operation, consecutive attempts read will produce alternating `0's `1's, i.e., toggling between When internal Program Erase operation completed, toggling will stop.
Function Reserved FGPI[4] Reads status general purpose input FGPI[3] Reads status general purpose input FGPI[2] Reads status general purpose input FGPI[1] Reads status general purpose input FGPI[0] Reads status general purpose input 32-PLCC
32-TSOP 40-TSOP
Multiple Device Selection
four pins, ID[3:0], allow multiple devices attached same using different strapping system. When SST49LF008A used boot device, ID[3:0] must strapped 0000, subsequent devices should sequential up-count strapping (i.e. 0001, 0010, 0011, etc.). SST49LF008A will compare strapping values, there mismatch, device will ignore remainder cycle into standby mode. further information regarding device mapping paging, please refer Intel 82801(ICH) Controller documentation. Since there support Mode, program multiple devices stand-alone PROM programmer recommended.
T5.3 1161
Block Locking Registers
SST49LF008A provides software controlled lock protection through Block Locking registers. Block Locking Registers read/write registers accessible through standard addressable memory locations specified Table Unused register locations will read 00H.
REGISTERS
There three types registers available SST49LF008A, General Purpose Inputs register, Block Locking registers JEDEC registers. These registers appear their respective address location GByte system memory map. Unused register locations will read 00H. Attempts read write registers during internal Write operations will ignored.
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Data Sheet TABLE Block Locking Registers SST49LF008A1
Register T_BLOCK_LK T_MINUS01_LK T_MINUS02_LK T_MINUS03_LK T_MINUS04_LK T_MINUS05_LK T_MINUS06_LK T_MINUS07_LK T_MINUS08_LK T_MINUS09_LK T_MINUS10_LK T_MINUS11_LK T_MINUS12_LK T_MINUS13_LK T_MINUS14_LK T_MINUS15_LK
Default value power
Block Size
Protected Memory Address Range 0FFFFFH 0F0000H 0EFFFFH 0E0000H 0DFFFFH 0D0000H 0CFFFFH 0C0000H 0BFFFFH 0B0000H 0AFFFFH 0A0000H 09FFFFH 090000H 08FFFFH 080000H 07FFFFH 070000H 06FFFFH 060000H 05FFFFH 050000H 04FFFFH 040000H 03FFFFH 030000H 02FFFFH 020000H 01FFFFH -010000H 00FFFFH 000000H
Memory Register Address FFBF0002H FFBE0002H FFBD0002H FFBC0002H FFBB0002H FFBA0002H FFB90002H FFB80002H FFB70002H FFB60002H FFB50002H FFB40002H FFB30002H FFB20002H FFB10002H FFB00002H
T6.4 1161
TABLE Block Locking Register Bits
Reserved [7.2] 000000 000000 000000 000000 Lock-Down Write-Lock Lock Status Full Access Write Locked (Default State Power-Up) Locked Open (Full Access Locked Down) Write Locked Down
T7.3 1161
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Write Lock
Write-Lock bit, controls lock state described Table default Write status blocks after powerup write locked. When Block Locking register set, Program Erase operations corresponding block prevented. Clearing Write-Lock will unprotect block. Write-Lock must cleared prior starting Program Erase operation since sampled beginning operation. Write-Lock functions conjunction with hardware Write Lock TBL# Boot Block. When TBL# low, overrides software locking scheme. Boot Block Locking register does indicate state TBL# pin. Write-Lock functions conjunction with hardware blocks When low, overrides software locking scheme. Block Locking register does indicate state pin.
PARALLEL PROGRAMMING MODE Device Operation
Commands used initiate memory operation functions device. data portion software command sequence latched rising edge WE#. During software command sequence address latched falling edge R/C# column address latched rising edge R/C#.
Reset
RST# initiates device reset.
Read
Read operation SST49LF008A device controlled OE#. output control used gate data from output pins. Refer Read cycle timing diagram, Figure further details.
Lock Down
Lock-Down bit, controls Block Locking register described Table When interface mode, default Lock Down status blocks upon power-up locked down. Once Lock-Down set, future attempted changes that Block Locking register will ignored. Lock-Down only cleared upon device reset with RST# INIT# power down. Current Lock Down status particular block determined reading corresponding Lock-Down bit. Once block's Lock-Down set, Write-Lock bits that block longer modified, block locked down current state write accessibility.
Byte-Program Operation
SST49LF008A device programmed byte-bybyte basis. Before programming, must ensure that sector, which byte which being programmed exists, fully erased. Byte-Program operation initiated executing four-byte command load sequence Software Data Protection with address (BA) data last byte sequence. During Byte-Program operation, address (A10-A0) latched falling edge R/C# column Address (A21-A11) latched rising edge R/C#. data latched rising edge WE#. Program operation, once initiated, will completed, within Figure Program operation timing diagram, Figure timing waveforms, Figure flowchart. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands written during internal Program operation will ignored.
JEDEC Registers
JEDEC registers boot device appear FFBC0000H FFBC0001H GByte system memory map, will appear elsewhere device boot device. Register available read when device Erase/Program operation. Unused register location will read 00H. Refer relevant application note details. Table device code.
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Sector-Erase Operation
Sector-Erase operation allows system erase device sector-by-sector basis. sector architecture based uniform sector size KByte. SectorErase operation initiated executing six-byte command load sequence Software Data Protection with Sector-Erase command (30H) sector address (SA) last cycle. internal Erase operation begins after sixth pulse. End-of-Erase determined using either Data# Polling Toggle methods. Figure Sector-Erase timing waveforms. commands written during Sector-Erase operation will ignored.
Write Operation Status Detection
SST49LF008A device provides software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-of-Write detection mode enabled after rising edge which initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid. Data# Polling (DQ7) When SST49LF008A device internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. Note that even though have valid data immediately following completion internal Write operation, remaining data outputs still invalid: valid data entire data will appear subsequent successive Read cycles after interval During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth pulse Program operation. Sector- ChipErase, Data# Polling valid after rising edge sixth pulse. Figure Data# Polling timing diagram Figure flowchart. Proper status will given using Data# Polling address invalid range. Toggle (DQ6) During internal Program Erase operation, consecutive attempts read will produce alternating `0's `1's, i.e., toggling between When internal Program Erase operation completed, toggling will stop. device then ready next operation. Toggle valid after rising edge fourth pulse Program operation. Sector-, Block- Chip-Erase, Toggle valid after rising edge sixth pulse. Figure Toggle timing diagram Figure flowchart.
Block-Erase Operation
Block-Erase Operation allows system erase device KByte uniform block size SST49LF008A. Block-Erase operation initiated executing six-byte command load sequence Software Data Protection with Block-Erase command (50H) block address. internal Block-Erase operation begins after sixth pulse. End-of-Erase determined using either Data# Polling Toggle methods. Figure timing waveforms. commands written during Block-Erase operation will ignored.
Chip-Erase
SST49LF008A device provides Chip-Erase operation only Mode, which allows user erase entire memory array `1's state. This useful when entire device must quickly erased. Chip-Erase operation initiated executing sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H last byte sequence. internal Erase operation begins with rising edge sixth WE#. During internal Erase operation, only valid read Toggle Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands written during Chip-Erase operation will ignored.
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Data Sheet TABLE Operation Modes Selection Mode)
Mode Read Program Erase Reset Write Inhibit Product Identification RST# DOUT High High Z/DOUT High Z/DOUT Manufacturer's (BFH) Device Address Sector Block address, Chip-Erase A18-A1=VIL, A0=VIL A18-A1=VIL, A0=VIH
T8.6 1161
VIH, other value. Device SST49LF008A
Data Protection
SST49LF008A device provides both hardware software features protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down.
Software Data Protection (SDP) SST49LF008A provides JEDEC approved Software Data Protection scheme data alteration operation, i.e., Program Erase. Program operation requires inclusion series three-byte sequences. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte load sequence. SST49LF008A device shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode, within TRC.
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
SOFTWARE COMMAND SEQUENCE
TABLE Software Command Sequence
Command Sequence Byte-Program Sector-Erase Block-Erase Chip-Erase6 Software Entry7,8 Software Exit9 Software Exit9 1st1 Write Cycle Addr2 5555H 5555H 5555H 5555H 5555H 5555H Data 2AAAH 5555H
T9.6 1161
2nd1 Write Cycle Addr2 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH
3rd1 Write Cycle 5555H 5555H 5555H 5555H 5555H
4th1 Write Cycle Data Data 5555H 5555H 5555H
5th1 Write Cycle Addr2 2AAAH 2AAAH 2AAAH
6th1 Write Cycle Data
Data Addr2
Data Addr2
Data Addr2 SAX4
5555H
Mode uses consecutive Write cycles complete command sequence; Mode uses consecutive cycles complete command sequence. Address format A14-A0 (Hex), Addresses A21-A15 VIH, other value, Command sequence Mode. Program Byte address Sector-Erase Address Block-Erase Address Chip-Erase supported Mode only Manufacturer's BFH, read with A0=0, With A19-A1 49LF008A Device 5AH, read with device does remain Software Product mode powered down. Both Software Exit operations equivalent.
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
ELECTRICAL SPECIFICATIONS
specifications Interface signals (FWH[3:0], CLK, FWH4, RST#) defined Section 4.2.2 Local Specification, Rev. 2.1. Refer Table voltage current specifications. Refer tables pages through timing specifications Clock, Read/Write, Reset operations. Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VDD+0.5V Transient Voltage (<20 Ground Potential1 -2.0V VDD+2.0V Package Power Dissipation Capability (TA=25°C) 1.0W Surface Mount Solder Reflow Temperature2 260°C seconds Output Short Circuit Current3
violate processor chipset limitations INIT# pin. Excluding certain with-Pb 32-PLCC units, packages 260°C capable both non-Pb with-Pb solder versions. Certain with-Pb 32-PLCC package types capable 240°C seconds; please consult factory latest information. Outputs shorted more than second. more than output shorted time. This note applies non-PCI outputs.
OPERATING RANGE
Range Commercial Ambient Temp +85°C 3.0-3.6V
CONDITIONS TEST1
Input Rise/Fall Time Output Load Figures
interface signals load test conditions
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Characteristics
TABLE Operating Characteristics (All Interfaces)
Limits Symbol Parameter Active Current Units Test Conditions1 LCLK (FWH mode) Address Input mode)=VILT/VIHT f=33 (FWH mode) 1/TRC Mode) other inputs=VIL outputs open, VDD=VDD Note3 LCLK (FWH mode) Address Input mode)=VILT/VIHT f=33 (FWH mode) 1/TRC Mode) LFRAME#=0.9 VDD, f=33 MHz, CE#=0.9 VDD, VDD=VDD Max, other inputs LCLK (FWH mode) Address Input mode)=VILT/VIHT f=33 (FWH mode) 1/TRC Mode) LFRAME#=VIL, f=33 MHz, VDD=VDD other inputs VIN=GND VDD, VDD=VDD VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD VDD=VDD VDD=VDD IOL=1500µA, VDD=VDD IOH=-500 VDD=VDD
T10.10 1161
Read Write2 Standby Current (FWH Interface)
IRY4
Ready Mode Current (FWH Interface)
VIHI5 VILI5
Input Current [3:0] pins Input Leakage Current Output Leakage Current INIT# Input High Voltage INIT# Input Voltage Input Voltage Input High Voltage Output Voltage Output High Voltage -0.5 -0.5
VDD+0.5
VDD+0.5
Test conditions apply mode. active while Erase Program progress. Mode: VIH; mode: 1/TRC min, LFRAME# VIH, VIL. device Ready Mode when activity bus. violate processor chipset specification regarding INIT# voltage.
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Data Sheet TABLE Recommended System Power-up Timings
Symbol TPU-READ1 TPU-WRITE
Parameter Power-up Read Operation Power-up Write Operation
Minimum
Units
T11.2 1161
This parameter measured only initial qualification after design process change that could affect this parameter
TABLE Impedance (VDD=3.3V, TA=25 Mhz, other pins open)
Parameter CI/O1
Description Capacitance Input Capacitance Inductance
Test Condition VI/O
Maximum
T12.4 1161
LPIN2
This parameter measured only initial qualification after design process change that could affect this parameter. Refer spec.
TABLE Reliability Characteristics
Symbol NEND TDR1 ILTH1
Parameter Endurance Data Retention Latch
Minimum Specification 10,000
Units Cycles Years
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T13.3 1161
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE Clock Timing Parameters
Symbol TCYC THIGH TLOW Parameter Cycle Time High Time Time Slew Rate (peak-to-peak) RST# INIT# Slew Rate Units V/ns mV/ns
T14.1 1161
Tcyc Thigh
1161 F11.0
Tlow p-to-p (minimum)
FIGURE Waveform
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Characteristics (FWH Mode)
TABLE Read/Write Cycle Timing Parameters, =3.0-3.6V (FWH Mode)
Symbol TCYC TVAL1 TSCE TOFF Parameter Clock Cycle Time Data Time Clock Rising Clock Rising Data Hold Time Clock Rising Data Valid Byte Programming Time Sector-Erase Time Block-Erase Time Chip-Erase Time Clock Rising Active (Float Active Delay) Clock Rising Inactive (Active Float Delay) Units
T15.3 1161
Minimum maximum times have different loads. spec.
TABLE Input/Output Specifications, =3.0-3.6V (FWH Mode)
Limits Symbol IOH(AC) Parameter Switching Current High -17.1(VDD-VOUT) Equation (Test Point) IOL(AC) Switching Current 26.7 VOUT Equation V/ns V/ns Units Test Conditions VOUT 0.3VDD 0.3VDD VOUT 0.9VDD 0.7VDD VOUT <VDD VOUT=0.7VDD >VOUT 0.6VDD 0.6VDD VOUT 0.1VDD 0.18VDD VOUT VOUT=0.18VDD VDD+4 VDD+1 0.2VDD-0.6VDD load 0.6VDD-0.2VDD load
T16.3 1161
(Test Point) slewr2 slewf2 Clamp Current High Clamp Current Output Rise Slew Rate Output Fall Slew Rate -25+(VIN+1)/0.015 25+(VIN-VDD-1)/0.015
spec. specification output load used.
TABLE Reset Timing Parameters, =3.0-3.6V (FWH Mode)
Symbol TPRST TKRST TRSTP TRSTF TRST
Parameter stable Reset Clock Stable Reset RST# Pulse Width RST# Output Float RST# High FWH4 RST# reset during Sector-/Block-Erase Program
Units
T17.5 1161
TRSTE
There will latency TRSTE reset procedure performed during Program Erase operation.
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
TPRST
TKRST
RST#/INIT#
TRSTP
TRSTE TRSTF TRST Sector-/Block-Erase Program operation aborted
FWH[3:0]
FWH4
1161 F12.0
FIGURE Reset Timing Diagram
VTEST TVAL
[3:0] (Valid Output Data)
[3:0] (Float Output Data)
TOFF
1161 F13.0
FIGURE Output Timing Parameters
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
[3:0] (Valid Input Data) Inputs Valid VTEST
VMAX
1161 F14.0
FIGURE Input Timing Parameters TABLE Interface Measurement Condition Parameters
Symbol
Value V/ns
Units
T18.3 1161
VTL1 VTEST VMAX1 Input Signal Edge Rate
input test environment done with overdrive over VIL. Timing parameters must with more overdrive than this. VMAX specified maximum peak-to-peak waveform allowed measuring input timing. Production testing different voltage values, must correlate results back these parameters.
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Characteristics Mode)
TABLE Read Cycle Timing Parameters, =3.0-3.6V Mode)
Symbol TRST TOLZ TOHZ Parameter Read Cycle Time RST# High Address Setup R/C# Address Set-up Time R/C# Address Hold Time Address Access Time Output Enable Access Time Active Output High High-Z Output Output Hold from Address Change Units
T19.2 1161
TABLE Program/Erase Cycle Timing Parameters, =3.0-3.6V Mode)
Symbol TRST TCWH TOES TOEH TOEP TOET TWPH TIDA TSCE Parameter RST# High Address Setup R/C# Address Setup Time R/C# Address Hold Time R/C# Write Enable High Time High Setup Time High Hold Time Data# Polling Delay Toggle Delay Pulse Width Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time Byte Programming Time Sector-Erase Time Block-Erase Time Chip-Erase Time Units
T20.2 1161
TABLE Reset Timing Parameters, =3.0-3.6V Mode)
Symbol TPRST TRSTP TRSTF TRST1 TRSTE TRSTC Parameter stable Reset RST# Pulse Width RST# Output Float RST# High Address Setup RST# reset during Sector-/Block-Erase Program RST# reset during Chip-Erase Units
T21.1 1161
There will reset latency TRSTE TRSTC reset procedure performed during Program Erase operation.
©2006 Silicon Storage Technology, Inc. S71161-11-000 3/06
Mbit Firmware SST49LF008A
TPRST
Addresses
Address
R/C#
RST#
TRSTP
TRSTE Sector-/Block-Erase Program operation aborted Chip-Erase aborted
TRSTC TRSTF TRST
DQ7-0
1161 F15.0
FIGURE Reset Timing Diagram Mode)
RST#
TRSTP TRST
Address Column Address Address Column Address
Addresses
R/C#
TOLZ TOHZ
Data Valid High-Z 1161 F16.0
DQ7-0
High-Z
FIGURE Read Cycle Timing Diagram Mode)
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
TRSTP
RST# Addresses
TRST Address Column Address
R/C#
TCWH TOEH
TOES
TWPH
DQ7-0
Data Valid 1161 F17.0
FIGURE Write Cycle Timing Diagram Mode)
Addresses
Column
R/C#
TOEP
1161 F18.0
FIGURE Data# Polling Timing Diagram Mode)
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Addresses
Column
R/C#
TOET
1161 F19.0
FIGURE Toggle Timing Diagram Mode)
Four-Byte Code Byte-Program Addresses 5555 R/C# 2AAA 5555
TWPH
Internal Program Starts
DQ7-0
Data
Byte-Program Address
1161 F20.0
FIGURE Byte-Program Timing Diagram Mode)
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Six-Byte code Sector-Erase Operation
Addresses 5555 R/C# 2AAA 5555 5555 2AAA
TWPH
DQ7-0
Internal Erasure Starts
Sector Address
1161 F21.0
FIGURE Sector-Erase Timing Diagram Mode)
Six-Byte code Block-Erase Operation
Addresses 5555 R/C# 2AAA 5555 5555 2AAA
TWPH
DQ7-0
Internal Erasure Starts
Block Address
1161 F22.0
FIGURE Block-Erase Timing Diagram Mode)
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Six-Byte code Chip-Erase Operation
Addresses 5555 R/C# 2AAA 5555 5555 2AAA 5555
TSCE TWPH
DQ7-0
Internal Erasure Starts
1161 F23.0
FIGURE Chip-Erase Timing Diagram Mode)
Three-byte sequence Software Entry Addresses 5555 2AAA 5555 0000 0001
R/C#
TWPH DQ7-0
1161 F24.2
TIDA
Device
Device SST49LF008A
FIGURE Software Entry Read Mode)
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Three-Byte Sequence Software Exit Reset
Addresses 5555 R/C# 2AAA 5555
DQ7-0 TWPH TIDA
1161 F25.0
FIGURE Software Exit Reset Mode)
VIHT
INPUT
REFERENCE POINTS
OUTPUT
VILT
1161 F26.0
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD). Input rise fall times (10% 90%)
Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE Input/Output Reference Waveforms Mode)
TESTER
1161 F27.0
FIGURE Test Load Example Mode)
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Start
Write data: Address: 5555H
Write data: Address: 2AAAH
Write data: Address: 5555H
Load Byte Address/Byte Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
1161 F28.0
FIGURE Byte-Program Algorithm
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Internal Timer ByteProgram/Erase Initiated
Toggle ByteProgram/Erase Initiated
Data# Polling ByteProgram/Erase Initiated
Wait TBP, TSCE,
Read byte
Read
Program/Erase Completed
Read same byte
true data?
Does match?
Program/Erase Completed
Program/Erase Completed
1161 F29.0
FIGURE Wait Options
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Software Product Entry Command Sequence
Software Product Exit Reset Command Sequence
Write data: Address: 5555H
Write data: Address: 5555H
Write data: Address:
Write data: Address: 2AAAH
Write data: Address: 2AAAH
Wait TIDA
Write data: Address: 5555H
Write data: Address: 5555H
Return normal operation
Wait TIDA
Wait TIDA
Read Software
Return normal operation
1161 F30.0
FIGURE Software Product Command Flowcharts
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Chip-Erase Command Sequence Write data: Address: 5555H
Block-Erase Command Sequence Write data: Address: 5555H
Sector-Erase Command Sequence Write data: Address: 5555H
Write data: Address: 2AAAH
Write data: Address: 2AAAH
Write data: Address: 2AAAH
Write data: Address: 5555H
Write data: Address: 5555H
Write data: Address: 5555H
Write data: Address: 5555H
Write data: Address: 5555H
Write data: Address: 5555H
Write data: Address: 2AAAH
Write data: Address: 2AAAH
Write data: Address: 2AAAH
Write data: Address: 5555H
Write data: Address:
Write data: Address:
Wait Options
Wait Options
Wait Options
Chip erased
Block erased
Sector erased
1161 F31.0
FIGURE Erase Command Sequence
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
PRODUCT ORDERING INFORMATION
Device Speed Suffix1 Suffix2 Suffix3 Environmental Attribute non-Pb Package Modifier leads leads Package Type PLCC TSOP (type 14mm) TSOP (type 10mm 20mm) Operating Temperature Commercial +85°C Minimum Endurance 10,000 cycles Serial Access Clock Frequency Version Second Version Device Density Mbit Voltage Range 3.0-3.6V Product Series Firmware Intel Chipsets
SST49LF00xA
Environmental suffix denotes non-Pb solder. non-Pb solder devices "RoHS Compliant".
Valid combinations SST49LF008A SST49LF008A-33-4C-WHE SST49LF008A-33-4C-NHE SST49LF008A-33-4C-EIE
Note: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
PACKAGING DIAGRAMS
VIEW
Optional Identifier .048 .042 .495 .485 .453 .447
SIDE VIEW
.112 .106 .020 MAX. .029 .023 .040 .030
BOTTOM VIEW
.042 .048 .595 .553 .585 .547 .032 .026
.021 .013 .400 .530 .490
.050 .015 Min. .050 .095 .075 .140 .125 .032 .026
Note: Complies with JEDEC publication MS-016 dimensions, although some dimensions more stringent. linear dimensions inches (max/min). Dimensions include mold flash. Maximum allowable mold flash .008 inches. Coplanarity: mils.
32-plcc-NH-3
FIGURE 32-lead Plastic Lead Chip Carrier (PLCC) Package Code:
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Identifier
1.05 0.95 0.50
8.10 7.90
0.27 0.17
12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80
0.15 0.05
0.70 0.50 Note: Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (max/min). Coplanarity: Maximum allowable mold flash 0.15 package ends, 0.25 between leads.
32-tsop-WH-7
FIGURE 32-lead Thin Small Outline Package (TSOP) 14mm Package Code:
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
1.05 0.95 Identifier 0.50
10.10 9.90
0.27 0.17
18.50 18.30 DETAIL 1.20 max. 0.70 0.50 20.20 19.80
0.15 0.05
Note: Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (max/min). Coplanarity: Maximum allowable mold flash 0.15 package ends, 0.25 between leads. 0.70 0.50
40-tsop-EI-7
FIGURE 40-lead Thin Small Outline Package (TSOP) 10mm 20mm Package Code:
©2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
Mbit Firmware SST49LF008A
Data Sheet TABLE Revision History
Revision Draft Changes Date July 2001
2002 Data Book Changed Transient Voltage from -1.0V +1.0V -2.0V +2.0V match Intel spec requirement. Added footnote Transient Voltage. Updated footnote Output Short Circuit Current. Updated Data# Polling description Corrected values Table page General Purpose Inputs Register Added note Table page Operating Characteristics Added 40-lead TSOP SST49LF008A only Corrected Test Conditions Table page 2004 Data Book Updated document status Data Sheet Removed Mbit Mbit devices refer Product Data Sheet S71161(01) Removed 32-PLCC (NH/NHE) Package associated MPNs Mbit device refer Product Data Sheet S71161(03). Clarified Solder Temperature Profile under "Absolute Maximum Stress Ratings" page Removed Mbit WH/WHE device refer Product Data Sheet S71161(03) Added statement that non-Pb devices RoHS compliant Features section Updated Surface Mount Solder Reflow Temperature information Removed leaded part numbers Applied formatting
June 2003 2003 2004 2004
2006
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2006 Silicon Storage Technology, Inc. S71161-11-000 3/06

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