SST39LF080 SST39VF080 SST39LF/VF0803.0 2.7V (x8) memories Da
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Mbit (x8) Multi-Purpose Flash
SST39LF080 SST39VF080
SST39LF/VF0803.0 2.7V (x8) memories
Data Sheet
FEATURES:
Organized Single Voltage Read Write Operations 3.0-3.6V SST39LF080 2.7-3.6V SST39VF080 Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption (typical values MHz) Active Current: (typical) Standby Current: (typical) Auto Power Mode: (typical) Sector-Erase Capability Uniform KByte sectors Block-Erase Capability Uniform KByte blocks Fast Read Access Time: SST39LF080 SST39VF080 Latched Address Data Fast Erase Byte-Program: Sector-Erase Time: (typical) Block-Erase Time: (typical) Chip-Erase Time: (typical) Byte-Program Time: (typical) Chip Rewrite Time: seconds (typical) SST39LF/VF080 Automatic Write Timing Internal Generation End-of-Write Detection Toggle Data# Polling CMOS Compatibility JEDEC Standard Flash EEPROM Pinouts command sets Packages Available 40-lead TSOP (10mm 20mm) 48-ball TFBGA (6mm 8mm)
PRODUCT DESCRIPTION
SST39LF/VF080 devices CMOS Multi-Purpose Flash (MPF) manufactured with SST's proprietary, high-performance CMOS SuperFlash technology. split-gate cell design thick-oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST39LF080 write (Program Erase) with 3.0-3.6V power supply. SST39VF080 write (Program Erase) with 2.7-3.6V power supply. They conform JEDEC standard pinouts memories. Featuring high performance Byte-Program, SST39LF/ VF080 devices provide typical Byte-Program time µsec. devices Toggle Data# Polling indicate completion Program operation. protect against inadvertent write, they have on-chip hardware Software Data Protection schemes. Designed, manufactured, tested wide spectrum applications, these devices offered with guaranteed typical endurance 10,000 cycles. Data retention rated greater than years. SST39LF/VF080 devices suited applications that require convenient economical updating program, configuration, data memory. system applications, they significantly improve performance reliability, while lowering power consumption. They inherently less energy during Erase Program than alter©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07 logo SuperFlash registered trademarks Silicon Storage Technology, Inc. trademark Silicon Storage Technology, Inc. These specifications subject change without notice.
native flash technologies. total energy consumed function applied voltage, current, time application. Since given voltage range, SuperFlash technology uses less current program shorter erase time, total energy consumed during Erase Program operation less than alternative flash technologies. They also improve flexibility while lowering cost program, data, configuration storage applications. SuperFlash technology provides fixed Erase Program times, independent number Erase/Program cycles that have occurred. Therefore system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. meet high density, surface mount requirements, SST39LF/VF080 offered 40-lead TSOP 48ball TFBGA packages. Figures assignments.
Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet
Device Operation
Commands used initiate memory operation functions device. Commands written device using standard microprocessor write sequences. command written asserting while keeping low. address latched falling edge CE#, whichever occurs last. data latched rising edge CE#, whichever occurs first. SST39LF/VF080 also have Auto Power mode which puts device near standby mode after data been accessed with valid Read operation. This reduces active read current from typically typically Auto Power mode reduces typical active read current range mA/MHz Read cycle time. device exits Auto Power mode with address transition control signal transition used initiate another Read cycle, with access time penalty. Note that device does enter Auto Power mode after power-up with held steadily until first address transition driven high.
operation, host free perform additional tasks. commands issued during internal Program operation ignored.
Sector/Block-Erase Operation
Sector- Block-) Erase operation allows system erase device sector-by-sector block-byblock) basis. SST39LF/VF080 offer both Sector-Erase Block-Erase mode. sector architecture based uniform sector size KByte. Block-Erase mode based uniform block size KByte. SectorErase operation initiated executing six-byte command sequence with Sector-Erase command (30H) sector address (SA) last cycle. Block-Erase operation initiated executing six-byte command sequence with Block-Erase command (50H) block address (BA) last cycle. sector block address latched falling edge sixth pulse, while command (30H 50H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. End-ofErase operation determined using either Data# Polling Toggle methods. Figures timing waveforms. commands issued during Sectoror Block-Erase operation ignored.
Read
Read operation SST39LF/VF080 controlled OE#, both have system obtain data from outputs. used device selection. When high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either high. Refer Read cycle timing diagram further details (Figure
Chip-Erase Operation
SST39LF/VF080 provide Chip-Erase operation, which allows user erase entire memory array state. This useful when entire device must quickly erased. Chip-Erase operation initiated executing sixbyte command sequence with Chip-Erase command (10H) address 5555H last byte sequence. Erase operation begins with rising edge sixth CE#, whichever occurs first. During Erase operation, only valid read Toggle Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands issued during Chip-Erase operation ignored.
Byte-Program Operation
SST39LF/VF080 programmed byte-by-byte basis. Before programming, sector where byte exists must fully erased. Program operation accomplished three steps. first step three-byte load sequence Software Data Protection. second step load byte address byte data. During ByteProgram operation, addresses latched falling edge either WE#, whichever occurs last. data latched rising edge either WE#, whichever occurs first. third step internal Program operation which initiated after rising edge fourth CE#, whichever occurs first. Program operation, once initiated, will completed within Figures controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program
Write Operation Status Detection
SST39LF/VF080 provide software means detect completion write (Program Erase) cycle, order optimize system Write cycle time. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-of-Write detection mode enabled after rising edge WE#, which initiates internal Program Erase operation.
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
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Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid.
Data Protection
SST39LF/VF080 provide both hardware software features protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down.
Data# Polling (DQ7)
When SST39LF/VF080 internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. Note that even though have valid data immediately following completion internal Write operation, remaining data outputs still invalid: valid data entire data will appear subsequent successive Read cycles after interval During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth CE#) pulse Program operation. Sector-, Block- Chip-Erase, Data# Polling valid after rising edge sixth CE#) pulse. Figure Data# Polling timing diagram Figure flowchart.
Software Data Protection (SDP)
SST39LF/VF080 provide JEDEC approved Software Data Protection scheme data alteration operations, i.e., Program Erase. Program operation requires inclusion three-byte sequence. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte sequence. SST39LF/VF080 devices shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode within TRC.
Toggle (DQ6)
During internal Program Erase operation, consecutive attempts read will produce alternating i.e., toggling between When internal Program Erase operation completed, will stop toggling. device then ready next operation. Toggle valid after rising edge fourth CE#) pulse Program operation. Sector-, Block-, Chip-Erase, Toggle valid after rising edge sixth CE#) pulse. Figure Toggle timing diagram Figure flowchart.
Common Flash Memory Interface (CFI)
SST39LF/VF080 also contain information describe characteristics device. order enter Query mode, system must load three-byte sequence, similar Software Entry command. last byte cycle this command loads (CFI Query command) address 5555H. Once device enters Query mode, system read data addresses given Tables through system must write Exit command return Read mode from Query mode.
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet
Product Identification
Product Identification mode identifies device SST39LF080 SST39VF080 manufacturer SST. This mode accessed software operations. Users Software Product Identification operation identify part (i.e., using device when using multiple manufacturers same socket. details, Table software operation, Figure Software Entry Read timing diagram Figure Software Entry command sequence flowchart. TABLE PRODUCT IDENTIFICATION
Address Manufacturer's Device SST39LF/VF080 0001H
T1.3 1146
Product Identification Mode Exit/ Mode Exit
order return standard Read mode, Software Product Identification mode must exited. Exit accomplished issuing Software Exit command sequence, which returns device Read operation. This command also used reset device Read mode after inadvertent transient condition that apparently causes device behave abnormally, e.g., read correctly. Please note that Software Exit/ Exit command ignored during internal Program Erase operation. Table software command codes, Figure timing waveform Figure flowchart.
Data
0000H
FUNCTIONAL BLOCK DIAGRAM
X-Decoder
SuperFlash Memory
Memory Address
Address Buffer Latches Y-Decoder
1146 B1.2
Control Logic
Buffers Data Latches
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
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Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet
Standard Pinout View
1146 F01.3
FIGURE Assignments 40-lead TSOP
VIEW (balls facing down)
1146 48-tfbga P2.2
FIGURE Assignments 48-ball TFBGA
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet TABLE DESCRIPTION
Symbol AMS1-A0 DQ7-DQ0 Name Address Inputs Data Input/output Functions provide memory addresses. During Sector-Erase AMS-A12 address lines will select sector. During Block-Erase AMS-A16 address lines will select block. output data during Read cycles receive input data during Write cycles. Data internally latched during Write cycle. outputs tri-state when high. activate device when low. gate data output buffers. control Write operations. provide power supply voltage: 3.0-3.6V SST39LF080 2.7-3.6V SST39VF080
Chip Enable Output Enable Write Enable Power Supply Ground Connection
Unconnected pins.
T2.4 1146
Most significant address SST39LF/VF080
TABLE OPERATION MODES SELECTION
Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode Table
T3.4 1146
DOUT High High DOUT High DOUT
Address Sector Block address, Chip-Erase
VIH, other value.
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
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Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet TABLE SOFTWARE COMMAND SEQUENCE
Command Sequence Byte-Program Sector-Erase Block-Erase Chip-Erase Software Entry4,5 Query Entry4 Software Exit Exit6/ Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H 5555H Data 2AAAH 5555H
T4.4 1146
Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Data
Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H Data
Write Cycle Addr1 5555H 5555H 5555H Data Data
Write Cycle Addr1 2AAAH 2AAAH 2AAAH Data
Write Cycle Addr1 SAX3
Data
5555H
Software Exit6/ Exit
Address format A14-A0 (Hex), Addresses A19-A15 VIH, other value, Command sequence SST39LF/VF080. Program Byte address Sector-Erase; uses AMS-A12 address lines Block-Erase; uses AMS-A16 address lines Most significant address SST39LF/VF080 device does remain Software Product mode powered down. With AMS-A1 Manufacturer's BFH, read with SST39LF/VF080 Device D8H, read with Both Software Exit operations equivalent
TABLE QUERY IDENTIFICATION STRING1 SST39LF/VF080
Address Data Data Query Unique ASCII string "QRY"
Primary command Address Primary Extended Table Alternate command (00H none exists) Address Alternate extended Table (00H none exits)
T5.4 1146
Refer publication more details.
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
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Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet TABLE SYSTEM INTERFACE INFORMATION SST39LF/VF080
Address Data 27H1 30H1 Data (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: millivolts (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: millivolts (00H pin) (00H pin) Typical time Byte-Program Typical time size buffer program (00H supported) Typical time individual Sector/Block-Erase Typical time Chip-Erase Maximum time Byte-Program times typical Maximum time buffer program times typical Maximum time individual Sector/Block-Erase times typical Maximum time Chip-Erase times typical
T6.2 1146
0030H SST39LF080 0027H SST39VF080
TABLE DEVICE GEOMETRY INFORMATION SST39LF/VF080
Address Data Data Device size Bytes (14H MByte) Flash Device Interface description; 0000H x8-only asynchronous interface Maximum number bytes multi-byte write (00H supported) Number Erase Sector/Block sizes supported device Sector Information Number sectors; 256B sector size) sectors (00FFH 255) Bytes KByte/sector (0010H Block Information Number blocks; 256B block size) blocks (000FH Bytes KByte/block (0100H 256)
T7.0 1146
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VDD+0.5V Transient Voltage (<20 Ground Potential -2.0V VDD+2.0V Voltage Ground Potential -0.5V 13.2V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current1
Outputs shorted more than second. more than output shorted time.
OPERATING RANGE SST39LF080
Range Commercial Ambient Temp +70°C 3.0-3.6V
OPERATING RANGE SST39VF080
Range Commercial Industrial Ambient Temp +70°C -40°C +85°C 2.7-3.6V 2.7-3.6V
CONDITIONS TEST
Input Rise/Fall Time Output Load SST39LF080 Output Load SST39VF080 Figures
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet TABLE OPERATING CHARACTERISTICS 3.0-3.6V SST39LF080 2.7-3.6V SST39VF0801
Limits Symbol Parameter Power Supply Current Read2 Program Erase IALP VILC VIHC Standby Current Auto Power Input Leakage Current Output Leakage Current Input Voltage Input Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Output Voltage Output High Voltage VDD-0.2 0.7VDD VDD-0.3 Units Test Conditions Address input=VILT/VIHT, f=1/TRC VDD=VDD CE#=VIL, OE#=WE#=VIH, I/Os open CE#=WE#=VIL, OE#=VIH CE#=VIHC, VDD=VDD CE#=VILC, VDD=VDD inputs=VSS VDD, WE#=VIHC VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD VDD=VDD VDD=VDD IOL=100 VDD=VDD IOH=-100 VDD=VDD
T8.7 1146
Typical conditions Active Current shown front data sheet page average values 25°C (room temperature), devices. 100% tested. Values conditions. Multi-Purpose Flash Power Rating application note further information.
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
Parameter Power-up Read Operation Power-up Program/Erase Operation
Minimum
Units
T9.1 1146
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE CAPACITANCE 25°C, Mhz, other pins open)
Parameter CI/O
Description Capacitance Input Capacitance
Test Condition VI/O
Maximum
T10.0 1146
CIN1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE RELIABILITY CHARACTERISTICS
Symbol NEND TDR1 ILTH1
Parameter Endurance Data Retention Latch
Minimum Specification 10,000
Units Cycles Years
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T11.2 1146
This parameter measured only initial qualification after design process change that could affect this parameter. NEND endurance rating qualified 10,000 cycle minimum whole device. sector- block-level rating would result higher minimum specification.
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet
CHARACTERISTICS
TABLE READ CYCLE TIMING PARAMETERS 3.0-3.6V SST39LF080 2.7-3.6V SST39VF080
SST39LF080-55 Symbol Parameter TCLZ1 TOLZ1 TCHZ TOH1
SST39VF080-70
SST39VF080-90 Units
T12.4 1146
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change
TOHZ1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TOES TOEH TWPH1 TCPH1 TDH1 TIDA1 TSCE Parameter Byte-Program Time Address Setup Time Address Hold Time Setup Time Hold Time High Setup Time High Hold Time Pulse Width Pulse Width Pulse Width High Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time Sector-Erase Block-Erase Chip-Erase Units
T13.0 1146
This parameter measured only initial qualification after design process change that could affect this parameter.
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet
ADDRESS AMS-0 HIGH-Z DQ7-0 TCLZ DATA VALID TCHZ HIGH-Z DATA VALID TOLZ TOHZ
1146 F02.2
FIGURE Read Cycle Timing Diagram
INTERNAL PROGRAM OPERATION STARTS ADDRESS AMS-0 5555 DQ7-0 DATA BYTE (ADDR/DATA)
1146 F03.2
2AAA
5555
ADDR
TWPH
FIGURE Controlled Program Cycle Timing Diagram
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet
INTERNAL PROGRAM OPERATION STARTS ADDRESS AMS-0 5555 DQ7-0 DATA BYTE (ADDR/DATA) TCPH 2AAA 5555 ADDR
1146 F04.2
FIGURE Controlled Program Cycle Timing Diagram
ADDRESS AMS-0 TOEH TOES
DATA
DATA#
DATA#
DATA
1146 F05.2
FIGURE Data# Polling Timing Diagram
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet
ADDRESS AMS-0 TOEH TOES
READ CYCLES WITH SAME OUTPUTS
1146 F06.2
FIGURE Toggle Timing Diagram
SIX-BYTE CODE CHIP-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
DQ7-0
1146 F08.3
FIGURE Controlled Chip-Erase Timing Diagram
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
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Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet
SIX-BYTE CODE BLOCK-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA
DQ7-0
1146 F09.3
FIGURE Controlled Block-Erase Timing Diagram
SIX-BYTE CODE SECTOR-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA
DQ7-0
1146 F10.3
FIGURE Controlled Sector-Erase Timing Diagram
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet
THREE-BYTE SEQUENCE SOFTWARE ENTRY ADDRESS A14-0 5555 2AAA 5555 0000 0001
TWPH DQ7-0
Note:
TIDA
Device
1146 F11.4
Device SST39LF/VF080
FIGURE Software Entry Read
THREE-BYTE SEQUENCE QUERY ENTRY ADDRESS A14-0 5555 2AAA 5555
TWPH DQ7-0
1146 F12.0
TIDA
FIGURE Query Entry Read
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet
THREE-BYTE SEQUENCE SOFTWARE EXIT RESET
ADDRESS A14-0
5555
2AAA
5555
DQ7-0
TIDA
TWHP
1146 F13.0
FIGURE Software Exit/CFI Exit
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet
VIHT
INPUT
REFERENCE POINTS
OUTPUT
VILT
1146 F14.1
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD). Input rise fall times (10% 90%)
Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE Input/Output Reference Waveforms
TESTER
1146 F15.1
FIGURE Test Load Example
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet
Start
Load data: Address: 5555H
Load data: Address: 2AAAH
Load data: Address: 5555H
Load Byte Address/Byte Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
1146 F16.1
FIGURE Byte-Program Algorithm
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet
Internal Timer Program/Erase Initiated
Toggle Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE,
Read byte
Read
Program/Erase Completed
Read same byte
true data?
Does match? Program/Erase Completed
Program/Erase Completed
1146 F17.0
FIGURE Wait Options
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet
Query Entry Command Sequence
Software Product Entry Command Sequence
Software Exit/CFI Exit Command Sequence
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address:
Load data: Address: 2AAAH
Load data: Address: 2AAAH
Load data: Address: 2AAAH
Wait TIDA
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address: 5555H
Return normal operation
Wait TIDA
Wait TIDA
Wait TIDA
Read data
Read Software
Return normal operation
1146 F18.1
FIGURE Software ID/CFI Command Flowcharts
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet
Chip-Erase Command Sequence Load data: Address: 5555H
Sector-Erase Command Sequence Load data: Address: 5555H
Block-Erase Command Sequence Load data: Address: 5555H
Load data: Address: 2AAAH
Load data: Address: 2AAAH
Load data: Address: 2AAAH
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address: 2AAAH
Load data: Address: 2AAAH
Load data: Address: 2AAAH
Load data: Address: 5555H
Load data: Address:
Load data: Address:
Wait TSCE
Wait
Wait
Chip erased
Sector erased
Block erased
1146 F19.1
FIGURE Erase Command Sequence
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet
PRODUCT ORDERING INFORMATION
XXXX Environmental Attribute non-Pb Package Modifier leads balls Package Type TFBGA (0.8mm pitch, 8mm) TSOP (type 10mm 20mm) Temperature Range Commercial +70°C Industrial -40°C +85°C Minimum Endurance 10,000 cycles Read Access Speed Device Density Mbit Voltage 3.0-3.6V 2.7-3.6V Product Series Multi-Purpose Flash
Valid combinations SST39LF080 SST39LF080-55-4C-EI SST39LF080-55-4C-EIE SST39LF080-55-4C-B3K SST39LF080-55-4C-B3KE
Valid combinations SST39VF080 SST39VF080-70-4C-EI SST39VF080-70-4C-EIE SST39VF080-90-4C-EI SST39VF080-90-4C-EIE SST39VF080-70-4I-EI SST39VF080-70-4I-EIE SST39VF080-90-4I-EI SST39VF080-90-4I-EIE SST39VF080-70-4C-B3K SST39VF080-70-4C-B3KE SST39VF080-90-4C-B3K SST39VF080-90-4C-B3KE SST39VF080-70-4I-B3K SST39VF080-70-4I-B3KE SST39VF080-90-4I-B3K SST39VF080-90-4I-B3KE
Note: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet
PACKAGING DIAGRAMS
1.05 0.95 Identifier 0.50
10.10 9.90
0.27 0.17
18.50 18.30 DETAIL 1.20 max. 0.70 0.50 20.20 19.80
0.15 0.05
Note: Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (max/min). Coplanarity: Maximum allowable mold flash 0.15 package ends, 0.25 between leads. 0.70 0.50
40-tsop-EI-7
FIGURE 40-lead Thin Small Outline Package (TSOP) 10mm 20mm Package Code:
©2007 Silicon Storage Technology, Inc.
S71146-07-EOL
6/07
Mbit Multi-Purpose Flash SST39LF080 SST39VF080
Data Sheet
VIEW
8.00 0.20
BOTTOM VIEW
5.60 0.80 0.45 0.05 (48X)
0.80 CORNER 4.00 6.00 0.20
SIDE VIEW
1.10 0.10
CORNER
SEATING PLANE 0.35 0.05
0.12
Note:
Complies with JEDEC Publication MO-210, variant 'AB-1', although some dimensions more stringent. linear dimensions millimeters. Coplanarity: 0.12 Ball opening size 0.38 0.05 48-tfbga-B3K-6x8-450mic-4
FIGURE 48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) Package Code:
TABLE REVISION HISTORY
Number Description Date 2002 2003
2002 Data Book package longer offered SST39LF/VF016 Part number changes page additional information Changes Table page Added footnote power usage Typical conditions Changed IALP test onditions Clarified test conditions Power Supply Current Read parameters Corrected Read Current from Corrected Program Erase Current from Removed Mbit parts (SST39LF/VF016); refer SST39VF1681/1682 (S71243) 2004 Data Book Updated package diagram Life Data Sheet devices S71146
2003 2003 June 2007
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2007 Silicon Storage Technology, Inc. S71146-07-EOL 6/07
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