SST36VF3203 SST36VF3204 SST36VF3201C 1602C32Mb (x8/x16) Concurren
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Mbit (x8/x16) Concurrent SuperFlash
SST36VF3203 SST36VF3204
SST36VF3201C 1602C32Mb (x8/x16) Concurrent SuperFlash
FEATURES:
Organized Dual Bank Architecture Concurrent Read/Write Operation Mbit Bottom Sector Protection smaller bank) SST36VF3203: Mbit Mbit Mbit Sector Protection smaller bank) SST36VF3204: Mbit Mbit Single 2.7-3.6V Read Write Operations Superior Reliability Endurance: 100,000 cycles (typical) Greater than years Data Retention Power Consumption: Active Current: typical Standby Current: typical Auto Power Mode: typical Hardware Sector Protection/WP# Input Protects KWord smaller bank driving unprotects driving high Hardware Reset (RST#) Resets internal state machine reading array data Byte# Selects 8-bit 16-bit mode Sector-Erase Capability Uniform KWord sectors Chip-Erase Capability Block-Erase Capability Uniform KWord blocks Erase-Suspend Erase-Resume Capabilities Security Feature SST: bits User: Bytes Fast Read Access Time Latched Address Data Fast Erase Program (typical): Sector-Erase Time: Block-Erase Time: Chip-Erase Time: Program Time: Automatic Write Timing Internal Generation End-of-Write Detection Toggle Data# Polling Ready/Busy# CMOS Compatibility Conforms Common Flash Memory Interface (CFI) JEDEC Standards Flash EEPROM Pinouts command sets Packages Available 48-ball TFBGA (6mm 8mm) 48-lead TSOP (12mm 20mm) non-Pb (lead-free) devices RoHS compliant
PRODUCT DESCRIPTION
SST36VF320x CMOS Concurrent Read/Write Flash Memory manufactured with SST's proprietary, high performance CMOS SuperFlash technology. split-gate cell design thick-oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. devices write (Program Erase) with 2.7-3.6V power supply conform JEDEC standard pinouts x8/x16 memories. Featuring high performance Word-Program, these devices provide typical Program time µsec Toggle Bit, Data# Polling, RY/BY# detect completion Program Erase operation. protect against inadvertent write, devices have on-chip hardware Software Data Protection schemes. Designed, manufactured, tested wide spectrum applications, these devices offered with guaranteed endurance 10,000 cycles. Data retention rated greater than years. These devices suited applications that require convenient economical updating program, configuration, data memory. system applications, devices significantly improve performance reliability, while lowering power consumption. Since given voltage range, SuperFlash technology uses less current program shorter erase time, total energy consumed during Erase Program operation less than alternative flash technologies. These devices also improve flexibility while lowering cost program, data, configuration storage applications.
©2005 Silicon Storage Technology, Inc. S71270-03-000 7/06
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. trademark Silicon Storage Technology, Inc. These specifications subject change without notice.
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
Data Sheet SuperFlash technology provides fixed Erase Program times, independent number Erase/Program cycles that have occurred. Therefore system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. meet high-density, surface-mount requirements, these devices offered 48-ball TFBGA 48-lead TSOP packages. Figures assignments.
Read Operation
Read operation controlled OE#; both have system obtain data from outputs. used device selection. When high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either high. Refer Read cycle timing diagram further details (Figure
Program Operation Device Operation
Memory operation functions initiated using standard microprocessor write sequences. command written asserting while keeping low. address latched falling edge CE#, whichever occurs last. data latched rising edge CE#, whichever occurs first. These devices programmed word-by-word byte-by-byte basis depending state BYTE# pin. Before programming, must ensure that sector which being programmed fully erased. Program operation accomplished three steps: Software Data Protection initiated using three-byte load sequence. Address data loaded. During Program operation, addresses latched falling edge either WE#, whichever occurs last. data latched rising edge either WE#, whichever occurs first. internal Program operation initiated after rising edge fourth CE#, whichever occurs first. Program operation, once initiated, will completed typically within Figures controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands issued during internal Program operation ignored.
Auto Power Mode
These devices also have Auto Lower Power mode which puts them near standby mode within after data been accessed with valid Read operation. This reduces active Read current typically. While low, devices exit Auto Power mode with address transition control signal transition used initiate another Read cycle, with access time penalty.
Concurrent Read/Write Operation
dual bank architecture these devices allows Concurrent Read/Write operation whereby user read from bank while programming erasing other bank. example, reading system code bank while updating data other bank. CONCURRENT READ/WRITE STATE
Bank Read Read Write Write Operation Operation Bank Operation Write Read Operation Read Write
Note: purposes this table, write means perform Blockor Sector-Erase Program operations applicable appropriate bank.
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
Sector- (Block-) Erase Operation
These devices offer both Sector-Erase Block-Erase operations. These operations allow system erase devices sector-by-sector block-by-block) basis. sector architecture based uniform sector size KWord. Block-Erase mode based uniform block size KWord. Sector-Erase operation initiated executing six-byte command sequence with SectorErase command (50H) sector address (SA) last cycle. Block-Erase operation initiated executing six-byte command sequence with Block-Erase command (30H) block address (BA) last cycle. sector block address latched falling edge sixth pulse, while command (30H 50H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. commands issued during Sector- Block-Erase operation ignored except Erase-Suspend EraseResume. Figures timing waveforms.
Erase-Suspend/Erase-Resume Operations
Erase-Suspend operation temporarily suspends Sector- Block-Erase operation thus allowing data read from memory location, program data into sector/block that suspended Erase operation. operation executed issuing one-byte command sequence with Erase-Suspend command (B0H). device automatically enters read mode more than after Erase-Suspend command been issued. (TES maximum latency equals µs.) Valid data read from sector block that suspended from Erase operation. Reading address location within erasesuspended sectors/blocks will output toggling "1". While Erase-Suspend mode, Program operation allowed except sector block selected Erase-Suspend. Software Entry command also executed. resume Sector-Erase Block-Erase operation which been suspended, system must issue Erase-Resume command. operation executed issuing one-byte command sequence with Erase Resume command (30H) address last byte sequence.
Chip-Erase Operation
devices provide Chip-Erase operation, which allows user erase sectors/blocks state. This useful when device must quickly erased. Chip-Erase operation initiated executing sixbyte command sequence with Chip-Erase command (10H) address 555H last byte sequence. Erase operation begins with rising edge sixth CE#, whichever occurs first. During Erase operation, only valid Read Toggle Data# Polling. commands issued during Chip-Erase operation ignored. Table command sequence, Figure timing diagram, Figure flowchart. When low, attempt Chip-Erase will ignored.
Write Operation Status Detection
These devices provide hardware software means detect completion Write (Program Erase) cycle order optimize system Write cycle time. hardware detection uses Ready/Busy# (RY/ BY#) output pin. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-of-Write detection mode enabled after rising edge WE#, which initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Ready/Busy# (RY/ BY#), Data# Polling (DQ7), Toggle (DQ6) Read simultaneous with completion Write cycle. this occurs, system erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection erroneous result occurs, software routine should include loop read accessed location additional times. both Reads valid, then Write cycle completed, otherwise rejection valid.
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
Ready/Busy# (RY/BY#)
devices include Ready/Busy# (RY/BY#) output signal. RY/BY# open drain output that indicates whether Erase Program operation progress. Since RY/BY# open drain output, allows several devices tied parallel external pull-up resistor. After rising edge final pulse command sequence, RY/BY# status valid. When RY/BY# actively pulled low, indicates that Erase Program operation progress. When RY/BY# high (Ready), devices read left standby mode.
Toggle Bits (DQ6 DQ2)
During internal Program Erase operation, consecutive attempts read will produce alternating "1"s "0"s, i.e., toggling between When internal Program Erase operation completed, will stop toggling. device then ready next operation. toggle valid after rising edge fourth CE#) pulse Program operations. Sector-, Block-, Chip-Erase, toggle (DQ6) valid after rising edge sixth CE#) pulse. will Read operation attempted Erase-suspended Sector/Block. Program operation initiated sector/block selected Erase-Suspend mode, will toggle. additional Toggle available DQ2, which used conjunction with check whether particular sector being actively erased erase-suspended. Table shows detailed status information. Toggle (DQ2) valid after rising edge last CE#) pulse Write operation. Figure Toggle timing diagram Figure flowchart. TABLE WRITE OPERATION STATUS
Status Normal Standard Operation Program Standard Erase EraseSuspend Mode Read From Erase Suspended Sector/Block Read From Non-Erase Suspended Sector/Block Program DQ7# Toggle Toggle Toggle Toggle Toggle RY/BY#
Byte/Word (BYTE#)
device includes BYTE# control whether device data pins operate x16. BYTE# logic (VIH) device data configuration: data pins DQ0-DQ15 active controlled OE#. BYTE# logic "0", device data configuration: only data pins DQ0-DQ7 active controlled OE#. remaining data pins DQ8DQ14 Hi-Z, while DQ15 used address input Least Significant address bus.
Data# Polling (DQ7)
When devices internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth CE#) pulse Program operation. Sector-, Block-, Chip-Erase, Data# Polling valid after rising edge sixth CE#) pulse. Figure Data# Polling (DQ7) timing diagram Figure flowchart.
Data
Data
Data
DQ7#
Toggle
T1.1 1270
Note: DQ7, DQ6, require valid address when reading status information. address must bank where operation progress order read operation status. address pointing different bank (not busy), device will output array data.
Data Protection
devices provide both hardware software features protect nonvolatile data from inadvertent writes.
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
Hardware Data Protection
Noise/Glitch Protection: pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down.
Software Data Protection (SDP)
These devices provide JEDEC standard Software Data Protection scheme data alteration operations, i.e., Program Erase. Program operation requires inclusion three-byte sequence. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte sequence. devices shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode within TRC. contents DQ15-DQ8 VIH, other value during command sequence.
Hardware Block Protection
devices provide hardware block protection which protects outermost KWord smaller bank. block protected when held low. When held Block-Erase command issued protected black, data outermost KWord/16 KByte section will protected. rest block will erased. Tables Block-Protection location. user disable block protection driving high. This allows data erased programmed into protected sectors. must held high prior issuing Write command remain stable until after entire Write operation completed. left floating, internally held high pull-up resistor, Boot Block unprotected, enabling Program Erase operations that block.
Common Flash Memory Interface (CFI)
These devices also contain information describe characteristics devices. order enter Query mode, system must write three-byte sequence, same Software Entry command with (CFI Query command) address BKX555H last byte sequence. order enter Query mode, system also one-byte sequence with BKX55H Address Data Bus. Figure Entry Read timing diagram. Once device enters Query mode, system read data addresses given Tables through system must write Exit command return Read mode from Query mode.
Hardware Reset (RST#)
RST# provides hardware method resetting devices read array data. When RST# held least TRP, in-progress operation will terminate return Read mode (see Figure output pins High-Z. When internal Program/Erase operation progress, minimum period TRHR required after RST# driven high before valid Read take place (see Figure 15). Erase operation that been interrupted needs reinitiated after device resumes normal operation mode ensure data integrity.
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
Security
SST36VF320x devices offer 136-word Security space. Secure space divided into segments-one 128-bit factory programmed segment 128-word (256-byte) user-programmed segment. first segment programmed locked with unique, 128-bit number. user segment left un-programmed customer program desired. program user segment Security user must Security Program command. End-of-Write status checked reading toggle bits. Data# Polling used Security End-of-Write detection. Once programming complete, should locked using User Program Lock-Out. This disables future corruption this space. Note that regardless whether locked, neither segment erased. Secure space queried executing three-byte command sequence with Query command (88H) address 555H last byte sequence. Figure timing diagram. exit this mode, Exit command should executed. Refer Table more details.
address from same bank without issuing Software Entry command. Software Entry command written address within bank that Read Mode Erase-Suspend mode. Software Entry command written while device programming erasing other bank. TABLE PRODUCT IDENTIFICATION
Address Manufacturer's Device SST36VF3203 SST36VF3204
Note: Bank Address (A20-A18)
Data 00BFH 7354H 7353H
T2.1 1270
BKX0000H BKX0001H BKX0001H
Product Identification Mode Exit/CFI Mode Exit
order return standard Read mode, Software Product Identification mode must exited. Exit accomplished issuing Software Exit command sequence, which returns device Read mode. This command also used reset device Read mode after inadvertent transient condition that apparently causes device behave abnormally, e.g., read correctly. Please note that Software Exit/CFI Exit command ignored during internal Program Erase operation. Table software command code, Figure timing waveform Figure flowchart.
Product Identification
Product Identification mode identifies devices manufacturer. details, Table software operation, Figure Software Entry Read timing diagram Figure Software Entry command sequence flowchart. addresses indicate bank address. When addressed bank switched Product Identification mode, possible read another
FUNCTIONAL BLOCK DIAGRAM
Memory Address
Address Buffers KWord KByte Sector Protection) SuperFlash Memory Bank
BYTE# RST# RY/BY#
1270 B01.0
SuperFlash Memory Bank Control Logic Buffers DQ15/A-1
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
Data Sheet TABLE SST36VF3203, BOTTOM DUAL-BANK MEMORY ORGANIZATION
SST36VF3203 Block Bank BA10 BA11 BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19 BA20 BA21 BA22 BA23 BA24 BA25 BA26 BA27 Bank BA28 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BA37 BA38 BA39 BA40 BA41 Block Size Address Range 000000H-003FFFH 004000H-00FFFFH 010000H-01FFFFH 020000H-02FFFFH 030000H-03FFFFH 040000H-04FFFFH 050000H-05FFFFH 060000H-06FFFFH 070000H-07FFFFH 080000H-08FFFFH 090000H-09FFFFH 0A0000H-0AFFFFH 0B0000H-0BFFFFH 0C0000H-0CFFFFH 0D0000H-0DFFFFH 0E0000H-0EFFFFH 0F0000H-0FFFFFH 100000H-10FFFFH 110000H-11FFFFH 120000H-12FFFFH 130000H-13FFFFH 140000H-14FFFFH 150000H-15FFFFH 160000H-16FFFFH 170000H-17FFFFH 180000H-18FFFFH 190000H-19FFFFH 1A0000H-1AFFFFH 1B0000H-1BFFFFH 1C0000H-1CFFFFH 1D0000H-1DFFFFH 1E0000H-1EFFFFH 1F0000H-1FFFFFH 200000H-20FFFFH 210000H-21FFFFH 220000H-22FFFFH 230000H-23FFFFH 240000H-24FFFFH 250000H-25FFFFH 260000H-26FFFFH 270000H-27FFFFH 280000H-28FFFFH 290000H-29FFFFH Address Range 000000H-001FFFH 002000H-007FFFH 008000H-00FFFFH 010000H-017FFFH 018000H-01FFFFH 020000H-027FFFH 028000H-02FFFFH 030000H-037FFFH 038000H-03FFFFH 040000H-047FFFH 048000H-04FFFFH 050000H-057FFFH 058000H-05FFFFH 060000H-067FFFH 068000H-06FFFFH 070000H-077FFFH 078000H-07FFFFH 080000H-087FFFH 088000H-08FFFFH 090000H-097FFFH 098000H-09FFFFH 0A0000H-0A7FFFH 0A8000H-0AFFFFH 0B0000H-0B7FFFH 0B8000H-0BFFFFH 0C0000H-0C7FFFH 0C8000H-0CFFFFH 0D0000H-0D7FFFH 0D8000H-0DFFFFH 0E0000H-0E7FFFH 0E8000H-0EFFFFH 0F0000H-0F7FFFH 0F8000H-0FFFFFH 100000H-107FFFH 108000H-10FFFFH 110000H-117FFFH 118000H-11FFFFH 120000H-127FFFH 128000H-12FFFFH 130000H-137FFFH 138000H-13FFFFH 140000H-147FFFH 148000H-14FFFFH
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
Data Sheet TABLE SST36VF3203, BOTTOM DUAL-BANK MEMORY ORGANIZATION (CONTINUED)
SST36VF3203 Block BA42 BA43 BA44 BA45 BA46 BA47 BA48 BA49 BA50 BA51 Bank BA52 BA53 BA54 BA55 BA56 BA57 BA58 BA59 BA60 BA61 BA62 BA63 Block Size Address Range 2A0000H-2AFFFFH 2B0000H-2BFFFFH 2C0000H-2CFFFFH 2D0000H-2DFFFFH 2E0000H-2EFFFFH 2F0000H-2FFFFFH 300000H-30FFFFH 310000H-31FFFFH 320000H-32FFFFH 330000H-33FFFFH 340000H-34FFFFH 350000H-35FFFFH 360000H-36FFFFH 370000H-37FFFFH 380000H-38FFFFH 390000H-39FFFFH 3A0000H-3AFFFFH 3B0000H-3BFFFFH 3C0000H-3CFFFFH 3D0000H-3DFFFFH 3E0000H-3EFFFFH 3F0000H-3FFFFFH Address Range 150000H-157FFFH 158000H-15FFFFH 160000H-167FFFH 168000H-16FFFFH 170000H-177FFFH 178000H-17FFFFH 180000H-187FFFH 188000H-18FFFFH 190000H-197FFFH 198000H-19FFFFH 1A0000H-1A7FFFH 1A8000H-1AFFFFH 1B0000H-1B7FFFH 1B8000H-1BFFFFH 1C0000H-1C7FFFH 1C8000H-1CFFFFH 1D0000H-1D7FFFH 1D8000H-1DFFFFH 1E0000H-1E7FFFH 1E8000H-1EFFFFH 1F0000H-1F7FFFH 1F8000H-1FFFFFH
T3.0 1270
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
Data Sheet TABLE SST36VF3204, DUAL-BANK MEMORY ORGANIZATION
SST36VF3204 Block BA10 BA11 BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19 BA20 Bank BA21 BA22 BA23 BA24 BA25 BA26 BA27 BA28 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BA37 BA38 BA39 BA40 BA41 BA42 Block Size Address Range 000000H-00FFFFH 010000H-01FFFFH 020000H-02FFFFH 030000H-03FFFFH 040000H-04FFFFH 050000H-05FFFFH 060000H-06FFFFH 070000H-07FFFFH 080000H-08FFFFH 090000H-09FFFFH 0A0000H-0AFFFFH 0B0000H-0BFFFFH 0C0000H-0CFFFFH 0D0000H-0DFFFFH 0E0000H-0EFFFFH 0F0000H-0FFFFFH 100000H-10FFFFH 110000H-11FFFFH 120000H-12FFFFH 130000H-13FFFFH 140000H-14FFFFH 150000H-15FFFFH 160000H-16FFFFH 170000H-17FFFFH 180000H-18FFFFH 190000H-19FFFFH 1A0000H-1AFFFFH 1B0000H-1BFFFFH 1C0000H-1CFFFFH 1D0000H-1DFFFFH 1E0000H-1EFFFFH 1F0000H-1FFFFFH 200000H-20FFFFH 210000H-21FFFFH 220000H-22FFFFH 230000H-23FFFFH 240000H-24FFFFH 250000H-25FFFFH 260000H-26FFFFH 270000H-27FFFFH 280000H-28FFFFH 290000H-29FFFFH 2A0000H-2AFFFFH Address Range 000000H-007FFFH 008000H-00FFFFH 010000H-017FFFH 018000H-01FFFFH 020000H-027FFFH 028000H-02FFFFH 030000H-037FFFH 038000H-03FFFFH 040000H-047FFFH 048000H-04FFFFH 050000H-057FFFH 058000H-05FFFFH 060000H-067FFFH 068000H-06FFFFH 070000H-077FFFH 078000H-07FFFFH 080000H-087FFFH 088000H-08FFFFH 090000H-097FFFH 098000H-09FFFFH 0A0000H-0A7FFFH 0A8000H-0AFFFFH 0B0000H-0B7FFFH 0B8000H-0BFFFFH 0C0000H-0C7FFFH 0C8000H-0CFFFFH 0D0000H-0D7FFFH 0D8000H-0DFFFFH 0E0000H-0E7FFFH 0E8000H-0EFFFFH 0F0000H-0F7FFFH 0F8000H-0FFFFFH 100000H-107FFFH 108000H-10FFFFH 110000H-117FFFH 118000H-11FFFFH 120000H-127FFFH 128000H-12FFFFH 130000H-137FFFH 138000H-13FFFFH 140000H-147FFFH 148000H-14FFFFH 150000H-157FFFH
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
Data Sheet TABLE SST36VF3204, DUAL-BANK MEMORY ORGANIZATION (CONTINUED)
SST36VF3204 Block BA43 BA44 Bank BA45 BA46 BA47 BA48 BA49 BA50 BA51 BA52 BA53 BA54 BA55 Bank BA56 BA57 BA58 BA59 BA60 BA61 BA62 BA63 Block Size Address Range 2B0000H-2BFFFFH 2C0000H-2CFFFFH 2D0000H-2DFFFFH 2E0000H-2EFFFFH 2F0000H-2FFFFFH 300000H-30FFFFH 310000H-31FFFFH 320000H-32FFFFH 330000H-33FFFFH 340000H-34FFFFH 350000H-35FFFFH 360000H-36FFFFH 370000H-37FFFFH 380000H-38FFFFH 390000H-39FFFFH 3A0000H-3AFFFFH 3B0000H-3BFFFFH 3C0000H-3CFFFFH 3D0000H-3DFFFFH 3E0000H-3EFFFFH 3F0000H-3FBFFFH 3FC000H-3FFFFFH Address Range 158000H-15FFFFH 160000H-167FFFH 168000H-16FFFFH 170000H-177FFFH 178000H-17FFFFH 180000H-187FFFH 188000H-18FFFFH 190000H-197FFFH 198000H-19FFFFH 1A0000H-1A7FFFH 1A8000H-1AFFFFH 1B0000H-1B7FFFH 1B8000H-1BFFFFH 1C0000H-1C7FFFH 1C8000H-1CFFFFH 1D0000H-1D7FFFH 1D8000H-1DFFFFH 1E0000H-1E7FFFH 1E8000H-1EFFFFH 1F0000H-1F7FFFH 1F8000H-1FDFFFH 1FE000H-1FFFFFH
T4.0 1270
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
VIEW (balls facing down)
BYTE#
NOTE*
DQ14 DQ13 DQ12
1270 48-tfbga P1.0
RST#
RY/BY# DQ10 DQ11
Note* DQ15/A-1
FIGURE ASSIGNMENTS 48-BALL TFBGA (6MM 8MM)
RST# RY/BY#
Standard Pinout View
BYTE# DQ15/A-1 DQ14 DQ13 DQ12 DQ11 DQ10
1270 48-tsop P02.0
FIGURE ASSIGNMENTS 48-LEAD TSOP (12MM 20MM)
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
Data Sheet TABLE DESCRIPTION
Symbol A20-A0 Name Address Inputs Functions provide memory addresses. During Sector-Erase Hardware Sector Protection, A20-A11 address lines will select sector. During Block-Erase A20-A15 address lines will select block. output data during Read cycles receive input data during Write cycles Data internally latched during Write cycle. outputs tri-state when high. DQ15 used data when mode (BYTE# "1") used address when mode (BYTE# "0") activate device when low. gate data output buffers control Write operations reset return device Read mode output status Program Erase operation RY/BY# open drain output, 100K pull-up resistor required allow RY/BY# transition high indicating device ready read. protect unprotect bottom KWord outermost sectors) from Erase Program operation. provide 2.7-3.6V power supply voltage Unconnected pins
T5.0 1270
DQ14-DQ0 Data Input/Output
DQ15/A-1 RST# RY/BY#
Data Input/Output Address Chip Enable Output Enable Write Enable Hardware Reset Ready/Busy#
BYTE#
Write Protect
Word/Byte Configuration select 8-bit 16-bit mode. Power Supply Ground Connection
TABLE OPERATION MODES SELECTION
DQ15-DQ8 Mode Read Program Erase RST# DQ7-DQ0 DOUT BYTE# DOUT BYTE# DQ14-DQ8 High DQ15 High Address Sector Block address, 555H Chip-Erase
Standby Write Inhibit Product Identification Software Mode Reset
VIHC
VIHC
High High DOUT High DOUT
High High DOUT High DOUT
High High High
Manufacturer's (BFH) Device High
Manufacturer's (00H) Device High
High High High
Table
T6.1 1270
VIH, other value. Device SST36VF3203 7354H, SST36VF3204 7353H
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
Data Sheet TABLE SOFTWARE COMMAND SEQUENCE
Command Sequence Word-Program Sector-Erase Block-Erase Chip-Erase Erase-Suspend Erase-Resume Query User Security Word-Program User Security Program Lock-out7 Software Entry8,9 Query Entry9 Query Entry9 Software Exit/ Exit/ Exit10,11 Software Exit/ Exit/ Exit10,11 Write Cycle Addr1
555H 555H 555H 555H XXXH XXXH 555H 555H 555H 555H 555H BKX4 555H
Write Cycle Addr1
2AAH 2AAH 2AAH 2AAH
Write Cycle Addr1
555H 555H 555H 555H
Write Cycle Addr1
555H 555H 555H
Write Cycle Addr1
2AAH 2AAH 2AAH
Write Cycle Addr1
SAX4
Data2
Data2
Data2
Data2
Data
Data2
Data2
555H
2AAH 2AAH 2AAH 2AAH 2AAH
555H 555H 555H BKX4 555H BKX4 555H
SIWA6 XXXH Data 0000H
2AAH
555H
T7.1 1270
Address format A10-A0 (Hex), Addresses A20-A11 VIH, other value (unless otherwise stated), command sequence when mode. When mode, Addresses A20-A12, Address A-1, DQ14-DQ8 VIH, other value (unless otherwise stated), command sequence. DQ15-DQ8 VIH, other value, command sequence Program word address Sector-Erase; uses A20-A11 address lines Block-Erase; uses A20-A15 address lines Bank Address; uses A20-A18 address lines SST36VF3203 Security Address Range (x16 mode) 100000H 100087H,(x8 mode) 100000H 10010FH read Address Range(x16 mode) 100000H 100007H mode) 100000H 10000FH User read Address Range(x16 mode) 100008H 100087H mode) 100010H 10010FH Lock status read Address 1000FFH (x16) 1001FFH (x8). Unlocked: Locked: SST36VF3204 Security Address Range is:(x16 mode) 000000H 000087H, mode) 000000H 00010FH read Address Range (x16 mode) 000000H 000007H mode) 000000H 00000FH User read Address Range (x16 mode) 000008H 000087H mode) 000010H 00010FH Lock Status read Address 0000FFH (x16) 0001FFH (x8). Unlocked: Locked: SIWA Valid Word addresses user SST36VF3203 User valid Address Range (x16 mode) 100008H-100087H mode) 100010H-10010FH. SST36VF3204 User valid Address Range (x16 mode) 000008H-000087H mode) 000010H-00010FH. cycles User Security Program Program Lock-out must completed before going back Read-Array mode. User Security Program Lock-out command must executed mode (BYTE#=VIH). device does remain Software Product Identification mode powered down. A20, A19, (Bank Address): address bank that switched Software ID/CFI Mode With A17-A1 0;SST Manufacturer's 00BFH, read with SST36VF3203 Device 7354H, read with SST36VF3204 Device 7353H, read with Both Software Exit operations equivalent users never lock after programming, User programmed over previously unprogrammed bits (data=1) using User mode again (the programmed bits cannot reversed "1").
©2005 Silicon Storage Technology, Inc. S71270-03-000 7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
Data Sheet TABLE QUERY IDENTIFICATION STRING1
Address Mode Address Mode Data2 0051H 0052H 0059H 0002H 0000H 0000H 0000H 0000H 0000H 0000H 0000H Description Query Unique ASCII string "QRY"
Primary command Address Primary Extended Table Alternate command (00H none exists) Address Alternate extended Table (00H none exits)
T8.1 1270
Refer publication more details. mode, only lower byte data output.
TABLE SYSTEM INTERFACE INFORMATION
Address Mode Address Mode Data1 0027H 0036H 0000H 0000H 0004H 0000H 0004H 0006H 0001H 0000H 0001H 0001H Description (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: millivolts (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: millivolts (00H pin) (00H pin) Typical time Program Typical time size buffer program (00H supported) Typical time individual Sector/Block-Erase Typical time Chip-Erase Maximum time Program times typical Maximum time buffer program times typical Maximum time individual Sector-/Block-Erase times typical Maximum time Chip-Erase times typical
T9.0 1270
mode, only lower byte data output.
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
Data Sheet TABLE DEVICE GEOMETRY INFORMATION
Address Mode Address Mode Data1 0016H 0002H 0000H 0000H 0000H 0002H 003FH 0000H 0000H 0001H 00FFH 0003H 0010H 0000H Description Device size Bytes (16H MByte) Flash Device Interface description; 0002H x8/x16 asynchronous interface Maximum number bytes multi-byte write (00H supported) Number Erase Sector/Block sizes supported device Block Information Number blocks; 256B block size) blocks (003FH Bytes KByte/block (0100H 256) Sector Information Number sectors; 256B sector size) 1023 1024 sectors (03FFH 1023) Bytes KByte/sector (0010H
T10.2 1270
mode, only lower byte data output.
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VDD+0.5V Transient Voltage (<20 Ground Potential -2.0V VDD+2.0V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Solder Reflow Temperature 260°C seconds Output Short Circuit Current
OPERATING RANGE
Range Extended Industrial Ambient Temp -20°C +85°C -40°C +85°C 2.7-3.6V 2.7-3.6V
CONDITIONS TEST
Input Rise/Fall Time Output Load Figures
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
Data Sheet TABLE OPERATING CHARACTERISTICS 2.7-3.6V
Limits Symbol IDD1 Parameter Active Current Read Program Erase Concurrent Read/Write IALP Standby Current Auto Power Current CE#=VIL, WE#=OE#=VIH CE#=WE#=VIL, OE#=VIH CE#=VIL, OE#=VIH CE#, RST#=VDD±0.3V CE#=0.1V, VDD=VDD WE#=VDD-0.1V Address inputs=0.1V VDD-0.1V RST#=GND =GND VDD, VDD=VDD WP#=GND VDD, VDD=VDD RST#=GND VDD, VDD=VDD VOUT =GND VDD, VDD=VDD VDD=VDD VDD=VDD VDD=VDD VDD=VDD IOL=100 VDD=VDD IOH=-100 VDD=VDD
T11.1 1270
Freq
Units
Test Conditions
ILIW VILC VIHC
Reset Current Input Leakage Current Input Leakage Current RST# Output Leakage Current Input Voltage Input Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Output Voltage Output High Voltage VDD-0.2 VDD-0.3
VDD+0.3 VDD+0.3
Address input VILT/VIHT, VDD=VDD (See Figure
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ
Parameter Power-up Read Operation Power-up Write Operation
Minimum
Units
T12.0 1270
TPU-WRITE1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE CAPACITANCE 25°C, Mhz, other pins open)
Parameter CI/O1
Description Capacitance Input Capacitance
Test Condition VI/O
Maximum
T13.0 1270
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE RELIABILITY CHARACTERISTICS
Symbol NEND TDR1 ILTH1
Parameter Endurance Data Retention Latch
Minimum Specification 10,000
Units Cycles Years
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T14.0 1270
This parameter measured only initial qualification after design process change that could affect this parameter.
©2005 Silicon Storage Technology, Inc. S71270-03-000 7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
CHARACTERISTICS
TABLE READ CYCLE TIMING PARAMETERS 2.7-3.6V
Symbol TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 TRP1 TRHR
Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change RST# Pulse Width RST# High before Read RST# Read Mode
Units
T15.1 1270
TRY1,2
This parameter measured only initial qualification after design process change that could affect this parameter. This parameter applies Sector-Erase, Block-Erase, Program operations. This parameter does apply Chip-Erase operations.
TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TOES TOEH TWPH1 TCPH1 TDH1 TIDA TSCE TBY1,2 TBR1
Parameter Program Time Address Setup Time Address Hold Time Setup Time Hold Time High Setup Time High Hold Time Pulse Width Pulse Width Pulse Width High Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time Sector-Erase Block-Erase Chip-Erase Erase-Suspend Latency RY/BY# Delay Time Recovery Time
Units
T16.1 1270
This parameter measured only initial qualification after design process change that could affect this parameter. This parameter applies Sector-Erase, Block-Erase, Program operations. This parameter does apply Chip-Erase operations.
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
ADDRESSES
TCLZ DATA VALID TCHZ HIGH-Z DATA VALID
1270 F03.0
TOLZ
TOHZ
DQ15-0
HIGH-Z
FIGURE READ CYCLE TIMING DIAGRAM
ADDRESSES RY/BY# DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA) Note: VIH, other value. VALID
1270 F04.0
ADDR
TWPH
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
ADDRESSES RY/BY# DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA) Note: VIH, other value. VALID
1270 F05.0
ADDR
TCPH
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS TOEH RY/BY# TOES
DATA
DATA#
DATA#
DATA
1270 F06.0
FIGURE DATA# POLLING TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc. S71270-03-000 7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
ADDRESSES TOEH
READ CYCLES WITH SAME OUTPUTS VALID DATA
1270 F07.0
FIGURE TOGGLE TIMING DIAGRAM
SIX-BYTE CODE CHIP-ERASE ADDRESSES
TSCE
RY/BY#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX10
VALID
1270 F08.0
Note: This device also supports controlled Chip-Erase operation. signals interchageable long minimum timings met. (See Table VIH, other value.
FIGURE CONTROLLED CHIP-ERASE TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc. S71270-03-000 7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
SIX-BYTE CODE BLOCK-ERASE ADDRESSES
RY/BY#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX30
VALID
1270 F09.0
Note: This device also supports controlled Block-Erase operation. signals interchageable long minimum timings met. (See Table Block Address VIH, other value.
FIGURE CONTROLLED BLOCK-ERASE TIMING DIAGRAM
SIX-BYTE CODE SECTOR-ERASE ADDRESSES
RY/BY#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX50
VALID
1270 F10.0
Note: This device also supports controlled Sector-Erase operation. signals interchageable long minimum timings met. (See Table Sector Address VIH, other value.
FIGURE CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc. S71270-03-000 7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
THREE-BYTE SEQUENCE SOFTWARE ENTRY ADDRESSES 0000 0001
TWPH DQ15-0 XXAA XX55 XX90 00BF
Device
1270 F11.1
TIDA
Device 7354H SST36VF3203 7353H SST36VF3204 Note: VIH, other value.
FIGURE SOFTWARE ENTRY READ
THREE-BYTE SEQUENCE QUERY ENTRY ADDRESSES
TWPH DQ15-0 XXAA XX55 XX98
1270 F12.0
TIDA
Note: VIH, other value.
FIGURE ENTRY READ
©2005 Silicon Storage Technology, Inc. S71270-03-000 7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
THREE-BYTE SEQUENCE SOFTWARE EXIT RESET
ADDRESSES
DQ15-0
XXAA
XX55
XXF0 TIDA
TWPH
1270 F13.0
Note: VIH, other value.
FIGURE SOFTWARE EXIT/CFI EXIT
THREE-BYTE SEQUENCE QUERY ENTRY ADDRESS AMS-0
TWPH DQ15-0 XXAA XX55 XX88
1270 F14.0
TIDA
Note: Most significant address SST39VF3203/3204 must held proper logic state (VIL VIH) prior after command sequence VIH, other value.
FIGURE ENTRY
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
RY/BY# RST#
CE#/OE# TRHR
1270 F15.0
FIGURE RST# TIMING DIAGRAM (WHEN INTERNAL OPERATION PROGRESS)
RY/BY# RST#
1270 F16.0
FIGURE RST# TIMING DIAGRAM (DURING SECTOR- BLOCK-ERASE OPERATION)
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
VIHT
INPUT
REFERENCE POINTS
OUTPUT
VILT
1270 F17.0
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD). Input rise fall times (10% 90%)
Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TESTER
1270 F18.0
FIGURE TEST LOAD EXAMPLE
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
Start
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XXA0H Address: 555H
Load Address/Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
1270 F19.0
Note: VIH, other value.
FIGURE WORD-PROGRAM ALGORITHM
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
Internal Timer Program/Erase Initiated
Toggle Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE,
Read byte/word
Read
Program/Erase Completed
Read same byte/word
true data?
Does match? Program/Erase Completed
Program/Erase Completed
1270 F20.0
FIGURE WAIT OPTIONS
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
Software Product Entry Command Sequence Load data: XXAAH Address: 555H
Query Entry Command Sequence Load data: XXAAH Address: 555H
Software Exit/ Exit/Sec Command Sequence Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX90H Address: 555H
Load data: XX98H Address: 555H
Load data: XXF0H Address: 555H
Wait TIDA
Wait TIDA
Wait TIDA
Read Software
Read data
Return normal operation
VIH, other value
1270 F20.0
FIGURE SOFTWARE PRODUCT ID/CFI/SEC ENTRY COMMAND FLOWCHARTS
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
Chip-Erase Command Sequence Load data: XXAAH Address: 555H
Sector-Erase Command Sequence Load data: XXAAH Address: 555H
Block-Erase Command Sequence Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX80H Address: 555H
Load data: XX80H Address: 555H
Load data: XX80H Address: 555H
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX10H Address: 555H
Load data: XX50H Address:
Load data: XX30H Address:
Wait TSCE
Wait
Wait
Chip erased FFFFH
Sector erased FFFFH
Block erased FFFFH
1270 F22.0
Note: VIH, other value.
FIGURE ERASE COMMAND SEQUENCE
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
PRODUCT ORDERING INFORMATION
320x XXXX Environmental Attribute non-Pb Package Modifier balls leads Package Type TFBGA (6mm 8mm) =TSOP (type 12mm 20mm) Temperature Range Extended -20°C +85°C Industrial -40°C +85°C Minimum Endurance 10,000 cycles Read Access Speed Bank Split Mbit Mbit Mbit Mbit Device Density Mbit Mbit Voltage 2.7-3.6V Product Series Concurrent SuperFlash
Environmental suffix denotes non-Pb solder. non-Pb solder devices "RoHS Compliant".
Valid combinations SST36VF3203 SST36VF3203-70-4E-B3KE SST36VF3203-70-4I-B3KE SST36VF3203-70-4E-EKE SST36VF3203-70-4I-EKE
Valid combinations SST36VF3204 SST36VF3204-70-4E-B3KE SST36VF3204-70-4I-B3KE SST36VF3204-70-4E-EKE SST36VF3204-70-4I-EKE
Note: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
PACKAGING DIAGRAMS
VIEW
8.00 0.20
BOTTOM VIEW
5.60 0.80 0.45 0.05 (48X)
0.80 CORNER 4.00 6.00 0.20
SIDE VIEW
1.10 0.10
CORNER
SEATING PLANE 0.35 0.05
0.12
Note:
Complies with JEDEC Publication MO-210, variant 'AB-1', although some dimensions more stringent. linear dimensions millimeters. Coplanarity: 0.12 Ball opening size 0.38 0.05 48-tfbga-B3K-6x8-450mic-4
48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) PACKAGE CODE:
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
1.05 0.95 Identifier 0.50
12.20 11.80
0.27 0.17
18.50 18.30
0.15 0.05
DETAIL 1.20 max. 0.70 0.50 20.20 19.80 Note: Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (max/min). Coplanarity: Maximum allowable mold flash 0.15 package ends, 0.25 between leads. 0.70 0.50
48-tsop-EK-8
48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM 20MM PACKAGE CODE:
©2005 Silicon Storage Technology, Inc.
S71270-03-000
7/06
Mbit Concurrent SuperFlash SST36VF3203 SST36VF3204
Data Sheet TABLE REVISION HISTORY
Number Description Date 2005 2005
Initial release data sheet Updated "Erase-Suspend/Erase-Resume Operations" page Updated footnote added footnote Table page Updated Query Identification Table page Updated Device Geometry Information Table page Updated parameter from Table page "Product Ordering Information" page Removed MPNs packages containing (B3K/EK) Removed commercial temperature MPNs Added extended temperature MPNs devices Removed Industrial Grade reference Changed Data Sheet Removed non-Pb reference Updated Bank information Changes from 30ns 35ns, Table page Re-added Industrial Grade reference
2006
2006
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2005 Silicon Storage Technology, Inc. S71270-03-000 7/06
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