SST34HF162C SST34HF164C SST34HF162C16Mb Dual-Bank Flash SRAM Comb
|
|
|
Top Searches for this datasheet
Mbit Dual-Bank Flash Mbit SRAM ComboMemory
SST34HF162C SST34HF164C
SST34HF162C16Mb Dual-Bank Flash SRAM ComboMemory
FEATURES:
Flash Organization: Mbit: Mbit Mbit Concurrent Operation Read from Write SRAM while Erase/Program Flash SRAM Organization: Mbit:128K Mbit: 256K Single 2.7-3.3V Read Write Operations Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: (typical values MHz) Active Current: Flash (typical) SRAM (typical) Standby Current: (typical) Sector-Erase Capability Uniform KWord sectors Block-Erase Capability Uniform KWord blocks Read Access Time Flash: SRAM: Erase-Suspend Erase-Resume Capabilities Latched Address Data Fast Erase Word-Program (typical): Sector-Erase Time: Block-Erase Time: Chip-Erase Time: Program Time: Automatic Write Timing Internal Generation End-of-Write Detection Toggle Data# Polling CMOS Compatibility JEDEC Standard Command Packages Available 48-ball LBGA (10mm 12mm)
PRODUCT DESCRIPTION
SST34HF162C/164C ComboMemory devices integrate CMOS flash memory bank with either 128K 256K CMOS SRAM memory bank multichip package (MCP). These devices fabricated using SST's proprietary, high-performance CMOS SuperFlash technology incorporating split-gate cell design thick-oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST34HF162C/164C devices ideal applications such cellular phones, devices, PDAs, other portable electronic devices power small form factor system. SuperFlash technology provides fixed Erase Program times, independent number Erase/Program cycles that have occurred. Therefore, system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. SST34HF162C/164C devices offer guaranteed endurance 10,000 cycles. Data retention rated greater than years. With high-performance Program operations, flash memory banks provide typical Program time µsec. entire flash memory bank erased programmed word-by-word seconds (typically) SST34HF162C/164C, when using interface features such Toggle Data# Polling
©2004 Silicon Storage Technology, Inc. S71269-01-000 9/04
indicate completion Program operation. protect against inadvertent flash write, SST34HF162C/164C devices contain on-chip hardware software data protection schemes. flash SRAM operate independent memory banks with respective bank enable signals. memory bank selection done bank enable signals. SRAM bank enable signal, BES#, selects SRAM bank. flash memory bank enable signal, BEF#, used with Software Data Protection (SDP) command sequence when controlling Erase Program operations flash memory bank. memory banks superimposed same memory address space where they share common address lines, data lines, which minimize power consumption area. Figure memory organization. Designed, manufactured, tested applications requiring power small form factor, SST34HF162C/ 164C offered both commercial extended temperatures small footprint package meet board space constraint requirements. Figure assignments.
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. ComboMemory trademark Silicon Storage Technology, Inc. These specifications subject change without notice.
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
Device Operation
SST34HF162C/164C BES# BEF# control operation either flash SRAM memory bank. When BEF# low, flash bank activated Read, Program Erase operation. When BES# SRAM activated Read Write operation. BEF# BES# cannot level same time. bank enable signals asserted, contention will result device suffer permanent damage. address, data, control lines shared flash SRAM memory banks which minimizes power consumption loading. device goes into standby when BEF# BES# bank enables raised VIHC (Logic High) when BEF# high.
Flash Program Operation
These devices programmed word-by-word basis. Before programming, must ensure that sector which being programmed fully erased. Program operation accomplished three steps: Software Data Protection initiated using three-byte load sequence. Address data loaded. During Program operation, addresses latched falling edge either BEF# WE#, whichever occurs last. data latched rising edge either BEF# WE#, whichever occurs first. internal Program operation initiated after rising edge fourth BEF#, whichever occurs first. Program operation, once initiated, will completed typically within Figures BEF# controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands issued during internal Program operation ignored.
Concurrent Read/Write Operation
SST34HF162C/164C provide unique benefit being able read from write SRAM, while simultaneously erasing programming flash. This allows data alteration code executed from SRAM, while altering data flash. following table lists valid states. CONCURRENT READ/WRITE STATE TABLE
Flash Program/Erase Program/Erase SRAM Read Write
device will ignore commands when Erase Program operation progress. Note that Product Identification commands SDP; therefore, these commands will also ignored while Erase Program operation progress.
Flash Sector- /Block-Erase Operation
These devices offer both Sector-Erase Block-Erase operations. These operations allow system erase devices sector-by-sector block-by-block) basis. sector architecture based uniform sector size KWord. Block-Erase mode based uniform block size KWord. Sector-Erase operation initiated executing six-byte command sequence with Sector-Erase command (30H) sector address (SA) last cycle. Block-Erase operation initiated executing six-byte command sequence with Block-Erase command (50H) block address (BA) last cycle. sector block address latched falling edge sixth pulse, while command (30H 50H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. commands issued during Block- SectorErase operation ignored except Erase-Suspend Erase-Resume. Figures timing waveforms.
Flash Read Operation
Read operation SST34HF162C/164C controlled BEF# OE#, both have system obtain data from outputs. BEF# used device selection. When BEF# high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either BEF# high. Refer Read cycle timing diagram further details (Figure
©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
Flash Chip-Erase Operation
SST34HF162C/164C provide Chip-Erase operation, which allows user erase sectors/blocks state. This useful when device must quickly erased. Chip-Erase operation initiated executing sixbyte command sequence with Chip-Erase command (10H) address 555H last byte sequence. Erase operation begins with rising edge sixth BEF#, whichever occurs first. During Erase operation, only valid read Toggle Bits Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands issued during Chip-Erase operation ignored.
vent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid. Flash Data# Polling (DQ7) When device internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth BEF#) pulse Program operation. Sector-, Block-, Chip-Erase, Data# Polling valid after rising edge sixth BEF#) pulse. Figure Data# Polling (DQ7) timing diagram Figure flowchart. Toggle Bits (DQ6 DQ2) During internal Program Erase operation, consecutive attempts read will produce alternating "1"s "0"s, i.e., toggling between When internal Program Erase operation completed, will stop toggling. device then ready next operation. toggle valid after rising edge fourth BEF#) pulse Program operations. Sector-, Block-, Chip-Erase, toggle (DQ6) valid after rising edge sixth BEF#) pulse. will Read operation attempted Erase-suspended Sector/Block. Program operation initiated sector/block selected Erase-Suspend mode, will toggle. additional Toggle available DQ2, which used conjunction with check whether particular sector being actively erased erase-suspended. Table shows detailed status information. Toggle (DQ2) valid after rising edge last BEF#) pulse Write operation. Figure Toggle timing diagram Figure flowchart. TABLE WRITE OPERATION STATUS
Status Normal Operation Standard Program Standard Erase DQ7# Toggle Toggle Toggle Toggle
Flash Erase-Suspend/-Resume Operations
Erase-Suspend operation temporarily suspends Sector- Block-Erase operation thus allowing data read from memory location, program data into sector/block that suspended Erase operation. operation executed issuing one-byte command sequence with Erase-Suspend command (B0H). device automatically enters read mode within after Erase-Suspend command been issued. Valid data read from sector block that suspended from Erase operation. Reading address location within erase-suspended sectors/blocks will output toggling "1". While Erase-Suspend mode, Program operation allowed except sector block selected Erase-Suspend. resume Sector-Erase Block-Erase operation which been suspended, system must issue Erase-Resume command. operation executed issuing one-byte command sequence with Erase Resume command (30H) address one-byte sequence.
Flash Write Operation Status Detection
SST34HF162C/164C provides software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-of-Write detection mode enabled after rising edge WE#, which initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling (DQ7) Toggle (DQ6) read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order pre©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
Preliminary Specifications TABLE WRITE OPERATION STATUS
Status EraseSuspend Mode Read From Erase Suspended Sector/ Block Read From Non-Erase Suspended Sector/ Block Program Toggle
Product Identification
Product Identification mode identifies device SST34HF162C SST34HF164C manufacturer SST. This mode accessed software operations only. hardware device Read operation, which typically used programmers cannot used this device because shared lines between flash SRAM multi-chip package. Therefore, application high voltage damage this device. Users software Product Identification operation identify part (i.e., using device when using multiple manufacturers same socket. details, Tables software operation, Figure Software Entry Read timing diagram Figure Entry command sequence flowchart. TABLE PRODUCT IDENTIFICATION
ADDRESS Manufacturer's Device SST34HF162C/164C BK0001H 734BH
T2.1 1269
Data
Data
Data
DQ7#
Toggle
Toggle
T1.0 1269
Note: DQ7, DQ6, require valid address when reading status information.
Data Protection
SST34HF162C/164C provide both hardware software features protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: BEF# pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, BEF# high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down. Software Data Protection (SDP) SST34HF162C/164C provide JEDEC standard Software Data Protection scheme data alteration operations, i.e., Program Erase. Program operation requires inclusion three-byte sequence. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte sequence. SST34HF162C/164C shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode within TRC. contents DQ15DQ8 "Don't Care" during command sequence.
DATA 00BFH
BK0000H
Note: Bank Address (A19-A18)
Product Identification Mode Exit order return standard Read mode, Software Product Identification mode must exited. Exit accomplished issuing Software Exit command sequence, which returns device Read mode. This command also used reset device Read mode after inadvertent transient condition that apparently causes device behave abnormally, e.g., read correctly. Please note that Software Exit command ignored during internal Program Erase operation. Table software command codes, Figure timing waveform Figure flowchart.
©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
SRAM Operation
With BES# BEF# high, SST34HF162C/164C operate either 128K 256K CMOS SRAM, with fully static operation requiring external clocks timing strobes. SST34HF162C/164C SRAM mapped into first KWord address space. When BES# BEF# high, memory banks deselected device enters standby. Read Write cycle times equal. control signals UBS# LBS# provide access upper data byte lower data byte. Table SRAM Read Write data byte control modes operation. SRAM Read SRAM Read operation SST34HF162C/164C controlled BES#, both have with high system obtain data from outputs.
BES# used SRAM bank selection. output control used gate data from output pins. data high impedance state when high. Refer Read cycle timing diagram, Figure further details. SRAM Write SRAM Write operation SST34HF162C/164C controlled BES#, both have system write SRAM. During Word-Write operation, addresses data referenced rising edge either BES# whichever occurs first. write time measured from last falling edge BES# first rising edge BES# WE#. Refer Write cycle timing diagrams, Figures further details.
FUNCTIONAL BLOCK DIAGRAM
AMSF1- AMSS2-
Address Buffers SuperFlash Memory (Bank
BEF# LBS# UBS# BES#
SuperFlash Memory (Bank Control Logic Buffers DQ15
Address Buffers
Mbit SRAM
1269 B1.1
Notes: AMSF Most significant flash address AMSF SST34HF162C/164C AMSS Most significant SRAM address AMSS SST34HF162C SST34HF164C
©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
KWord Blocks; KWord Sectors
FFFFFH F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H A7FFFH A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH 10000H 0FFFFH 08000H 07FFFH 02000H 01FFFH 00000H Block Block Block
Bank Bank
1269 F01.0
Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block
Block
FIGURE DUAL-BANK MEMORY ORGANIZATION
©2004 Silicon Storage Technology, Inc. S71269-01-000 9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
VIEW (balls facing down)
SST34HF162C/164C
BES#
DQ12
LBS# DQ15
VDDS
DQ11 DQ13 DQ14
FIGURE ASSIGNMENTS 48-BALL LBGA (10MM 12MM) TABLE DESCRIPTION
Symbol Name Functions provide flash address, A19-A0. provide SRAM address, AMSS-A0 AMSS1 Address Inputs DQ15-DQ0 Data Inputs/Outputs
output data during Read cycles receive input data during Write cycles. Data internally latched during flash Erase/Program cycle. outputs tri-state when OE#, BES#, BEF# high. activate Flash memory bank when BEF# activate SRAM memory bank when BES# gate data output buffers control Write operations enable DQ15-DQ8 enable DQ7-DQ0 2.7-3.3V Power Supply Flash only 2.7-3.3V Power Supply SRAM only Unconnected pins
T3.1 1269
BEF# BES# UBS# LBS#
Flash Memory Bank Enable SRAM Memory Bank Enable Output Enable Write Enable Upper Byte Control (SRAM) Lower Byte Control (SRAM) Ground Power Supply (Flash) Power Supply (SRAM) Connection
VDDF VDDS
Most Significant Address SST34HF162C SST34HF164C
©2004 Silicon Storage Technology, Inc.
1269 48-lbga P1.1
UBS# BEF# DQ10 VDDF
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
Preliminary Specifications TABLE OPERATIONAL MODES SELECTION SRAM
Mode Full Standby Output Disable BEF#1 Flash Read Flash Write Flash Erase SRAM Read BES#1,2 SRAM Write Product Identification3
OE#2
WE#2
LBS#2
UBS#2
DQ15-0 HIGH-Z HIGH-Z HIGH-Z DOUT DOUT HIGH-Z DOUT HIGH-Z HIGH-Z HIGH-Z HIGH-Z DOUT DOUT DOUT HIGH-Z HIGH-Z
DQ15-8 HIGH-Z HIGH-Z HIGH-Z DQ15-8=HIGH-Z DQ15-8=HIGH-Z DOUT DOUT HIGH-Z HIGH-Z
Manufacturer's Device
T4.1 1269
apply BEF# BES# same time VIH, other value. Software mode only With A19-A18 VIL; Manufacturer's BFH, read with A0=0, SST34HF162C/164C Device 734BH, read with A0=1
©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
Preliminary Specifications TABLE SOFTWARE COMMAND SEQUENCE
Command Sequence Program Sector-Erase Block-Erase Chip-Erase Erase-Suspend Erase-Resume Software Entry5 Write Cycle Addr1
555H 555H 555H 555H XXXXH XXXXH 555H 555H
Write Cycle Addr1
2AAH 2AAH 2AAH 2AAH
Write Cycle Addr1
555H 555H 555H 555H
Write Cycle Addr1
555H 555H 555H
Write Cycle Addr1
2AAH 2AAH 2AAH
Write Cycle Addr1
SAX4
Data2
Data2
Data2
Data2
Data
Data2
Data2
555H
2AAH 2AAH
BKX6 555H 555H
Software Exit Software Exit
T5.0 1269
Address format A11-A0 (Hex), Addresses A19-A12 VIH, other value, command sequence. DQ15-DQ8 VIH, other value, command sequence Program word address Sector-Erase; uses A19-A10 address lines Block-Erase; uses A19-A15 address lines device does remain Software Product Identification mode powered down.
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Operating Temperature -20°C +85°C Storage Temperature -65°C +125°C Voltage Ground Potential .-0.5V VDD1+0.3V Transient Voltage (<20 Ground Potential -1.0V VDD1+1.0V Package Power Dissipation Capability 25°C) 1.0W Output Short Circuit Current2
VDDF VDDS Outputs shorted more than second. more than output shorted time.
OPERATING RANGE
Range Commercial Extended Ambient Temp +70°C -20°C +85°C 2.7-3.3V 2.7-3.3V
CONDITIONS TEST
Input Rise/Fall Time Output Load Figures
©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
Preliminary Specifications TABLE OPERATING CHARACTERISTICS (VDD VDDF VDDS 2.7-3.3V)
Limits Symbol IDD1 Parameter Active Current Read Flash SRAM Concurrent Operation Write2 Flash SRAM VILC VIHC VOLF VOHF VOLS VOHS Standby Current Input Leakage Current Output Leakage Current Input Voltage Input Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Flash Output Voltage Flash Output High Voltage SRAM Output Voltage SRAM Output High Voltage Units Test Conditions Address input VILT/VIHT, MHz, VDD=VDD Max, open OE#=VIL, WE#=VIH BEF#=VIL, BES#=VIH BEF#=VIH, BES#=VIL BEF#=VIH, BES#=VIL WE#=VIL BEF#=VIL, BES#=VIH, OE#=VIH BEF#=VIH, BES#=VIL Max, BEF#=BES#=VIHC VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD VDD=VDD VDD=VDD IOL=100 VDD=VDD IOH=-100 VDD=VDD VDD=VDD =-500 VDD=VDD
T6.1 1269
VDD-0.3 VDD-0.2
Figure active while Erase Program progress.
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ
Parameter Power-up Read Operation Power-up Write Operation
Minimum
Units
T7.0 1269
TPU-WRITE1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE CAPACITANCE 25°C, Mhz, other pins open)
Parameter CI/O
Description Capacitance Input Capacitance
Test Condition VI/O
Maximum
T8.0 1269
CIN1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE FLASH RELIABILITY CHARACTERISTICS
Symbol NEND1
Parameter Endurance Data Retention Latch
Minimum Specification 10,000
Units Cycles Years
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T9.0 1269
ILTH1
This parameter measured only initial qualification after design process change that could affect this parameter.
©2004 Silicon Storage Technology, Inc. S71269-01-000 9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
CHARACTERISTICS
TABLE SRAM READ CYCLE TIMING PARAMETERS
Symbol TRCS TAAS TBES TOES TBYES TBLZS1 TOLZS1 TBYLZS1 TBHZS
Parameter Read Cycle Time Address Access Time Bank Enable Access Time Output Enable Access Time UBS#, LBS# Access Time BES# Active Output Output Enable Active Output UBS#, LBS# Active Output BES# High-Z Output Output Disable High-Z Output
Units
T10.0 1269
TOHZS1 TBYHZS TOHS
UBS#, LBS# High-Z Output Output Hold from Address Change
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE SRAM WRITE CYCLE TIMING PARAMETERS
Symbol TWCS TBWS TAWS TASTS TWPS TWRS TBYWS TODWS TOEWS TDSS TDHS Parameter Write Cycle Time Bank Enable End-of-Write Address Valid End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time UBS#, LBS# End-of-Write Output Disable from Output Enable from High Data Set-up Time Data Hold from Write Time Units
T11.0 1269
©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
Preliminary Specifications TABLE FLASH READ CYCLE TIMING PARAMETERS 2.7-3.3V
Symbol TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time BEF# Active Output Active Output BEF# High High-Z Output High High-Z Output Output Hold from Address Change Units
T12.0 1269
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TOES TOEH TWPH1 TCPH1 TBR1 TSCE
Parameter Program Time Address Setup Time Address Hold Time BEF# Setup Time BEF# Hold Time High Setup Time High Hold Time BEF# Pulse Width Pulse Width Pulse Width High BEF# Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time Erase-Suspend Latency Bus# Recovery Time Sector-Erase Block-Erase Chip-Erase
Units
TIDA1
T13.1 1269
This parameter measured only initial qualification after design process change that could affect this parameter.
©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
TRCS ADDRESSES AMSS-0 TAAS BES# TBES TBLZS TOLZS UBS#, LBS# TBYLZS DQ15-0 DATA VALID
1269 F03.1
TOHS
TBHZS TOES TOHZS TBYES TBYHZS
Note: AMSS Most Significant Address AMSS SST34HF162C SST34HF164C
FIGURE SRAM READ CYCLE TIMING DIAGRAM
TWCS ADDRESSES AMSS3-0
TAWS
TASTS
TWPS
TWRS
TBWS
BES#
UBS#, LBS# TODWS DQ15-8, DQ7-0
NOTE
TBYWS TDSS TOEWS TDHS
NOTE
1269 F04.1
VALID DATA
Note: High during Write cycle, outputs will remain high impedance. BES# goes coincident with after goes low, output will remain high impedance. BES# goes high coincident with before goes high, output will remain high impedance. Because signals output state this time, input signals reverse polarity must applied. AMSS Most Significant SRAM Address AMSS SST34HF162C SST34HF164C
FIGURE SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1
©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
TWCS ADDRESSES AMSS3-0 TWPS TBWS BES# TAWS TASTS UBS#, LBS# TDSS DQ15-8, DQ7-0
NOTE
TWRS
TBYWS
TDHS
NOTE
1269 F05.1
VALID DATA
Note: High during Write cycle, outputs will remain high impedance. Because signals output state this time, input signals reverse polarity must applied. AMSS Most Significant SRAM Address AMSS SST34HF162C SST34HF164C
FIGURE SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1
ADDRESS A19-0 BEF# TCLZ DATA VALID TOLZ
TOHZ
TCHZ HIGH-Z DATA VALID
1269 F06.0
DQ15-0
HIGH-Z
FIGURE FLASH READ CYCLE TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
ADDRESS A19-0 BEF# DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA) Note: VIH, other value. VALID
1269 F07.0
ADDR
TWPH
FIGURE FLASH CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A19-0 BEF# XXAA XX55 XXA0 DATA WORD (ADDR/DATA) Note: VIH, other value. VALID TCPH ADDR
DQ15-0
1269 F08.0
FIGURE FLASH BEF# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
ADDRESS A19-0 BEF# TOEH TOES
DATA
DATA#
DATA#
DATA
1269 F09.0
FIGURE FLASH DATA# POLLING TIMING DIAGRAM
ADDRESS A19-0 BEF# TOEH
READ CYCLES WITH SAME OUTPUTS
VALID DATA
1269 F10.0
FIGURE FLASH TOGGLE TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
SIX-BYTE CODE CHIP-ERASE ADDRESS A19-0
TSCE
BEF#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX10
VALID
1269 F11.0
Note: This device also supports BEF# controlled Chip-Erase operation. BEF# signals interchangeable long minimum timings met. (See Table 13.) VIH, other value.
FIGURE FLASH CONTROLLED CHIP-ERASE TIMING DIAGRAM
SIX-BYTE CODE BLOCK-ERASE ADDRESS A19-0 BEF# XXAA XX55 XX80 XXAA XX55 XX50
DQ15-0
VALID
1269 F12.0
Note: This device also supports BEF# controlled Block-Erase operation. BEF# signals interchangeable long minimum timings met. (See Table 13.) Block Address VIH, other value.
FIGURE FLASH CONTROLLED BLOCK-ERASE TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
SIX-BYTE CODE SECTOR-ERASE ADDRESS A19-0 BEF#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX30
VALID
1269 F13.0
Note: This device also supports BEF# controlled Sector-Erase operation. BEF# signals interchangeable long minimum timings met. (See Table 13.) Sector Address VIH, other value.
FIGURE FLASH CONTROLLED SECTOR-ERASE TIMING DIAGRAM
Three-Byte Sequence Software Entry 0000 0001
ADDRESS A14-0
BEF#
TWPH DQ15-0 XXAA XX55 XX90 00BF
Device
1269 F14.0
TIDA
Note: VIH, other value. Device 734BH SST34HF162C/164C
FIGURE FLASH SOFTWARE ENTRY READ
©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
Three-Byte Sequence Software Exit Reset
ADDRESS A14-0
DQ15-0
XXAA
XX55
XXF0 TIDA
BEF#
TWHP
1269 F15.0
Note: VIH, other value
FIGURE FLASH SOFTWARE EXIT
©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
VIHT INPUT VILT
1269 F16.0
REFERENCE POINTS
OUTPUT
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD). Input rise fall times (10% 90%)
Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TESTER
1269 F17.0
FIGURE TEST LOAD EXAMPLE
©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
Start
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XXA0H Address: 555H
Load Address/Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
1269 F18.0
Note: VIH, other value.
FIGURE PROGRAM ALGORITHM
©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
Internal Timer Program/Erase Initiated
Toggle Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE,
Read byte/word
Read
Program/Erase Completed
Read same byte/word
true data?
Does match? Program/Erase Completed
Program/Erase Completed
1269 F19.0
FIGURE WAIT OPTIONS
©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
Software Product Entry Command Sequence
Software Exit Command Sequence
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX90H Address:
Load data: XXF0H Address: 555H
Wait TIDA
Wait TIDA
Read Software
Return normal operation
1269 F20.0
Note: VIH, other value.
FIGURE SOFTWARE PRODUCT COMMAND FLOWCHARTS
©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
Chip-Erase Command Sequence Load data: XXAAH Address: 555H
Sector-Erase Command Sequence Load data: XXAAH Address: 555H
Block-Erase Command Sequence Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX80H Address: 555H
Load data: XX80H Address: 555H
Load data: XX80H Address: 555H
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XXAAH Address: 555H
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX55H Address: 2AAH
Load data: XX10H Address: 555H
Load data: XX30H Address:
Load data: XX50H Address:
Wait TSCE
Wait
Wait
Chip erased FFFFH
Sector erased FFFFH
Block erased FFFFH
1269 F21.0
Note: VIH, other value.
FIGURE ERASE COMMAND SEQUENCE
©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
PRODUCT ORDERING INFORMATION
Device Speed Suffix1 Suffix2 XXXX
SST34HF162C
Package Modifier balls Package Type LBGA (10mm 12mm 1.4mm, 0.50mm ball size) Temperature Range Commercial +70°C Extended -20°C +85°C Minimum Endurance =10,000 cycles Read Access Speed Version SRAM SRAM Density Mbit Mbit Flash Density Mbit Voltage 2.7-3.3V Product Series Dual-Bank Flash SRAM ComboMemory
Valid combinations SST34HF162C SST34HF162C-70-4C-LBK SST34HF162C-70-4E-LBK Valid combinations SST34HF164C SST34HF164C-70-4C-LBK SST34HF164C-70-4E-LBK
Note: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2004 Silicon Storage Technology, Inc.
S71269-01-000
9/04
Mbit Dual-Bank Flash Mbit SRAM ComboMemory SST34HF162C SST34HF164C
PACKAGING DIAGRAMS
VIEW
12.00 0.20
BOTTOM VIEW
10.00 0.20
0.50 0.05 (48X) CORNER
CORNER
SIDE VIEW
SEATING PLANE 0.40 0.05 Note:
0.12
Although many dimensions similar those JEDEC Publication MO-210, this specific package registered. linear dimensions millimeters. Coplanarity: 0.12 Ball opening size 0.05
48-lbga-LBK-10x12-500mic-2
48-BALL LOW-PROFILE BALL GRID ARRAY (LBGA) 10MM 12MM PACKAGE CODE: TABLE REVISION HISTORY
Number Description Date 2004 2004
Initial Release Adding Mbit SRAM parts associated MPNs Removed PB-free MPNs SST34HF162C devices Clarifed values Power Consumption page Added specifications Active Current (IDD) Table page Data sheet status changed "Preliminary Specifications"
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2004 Silicon Storage Technology, Inc. S71269-01-000 9/04
Other recent searches
YTD423 - YTD423 YTD423 Datasheet
SHCNA20S7 - SHCNA20S7 SHCNA20S7 Datasheet
Q62702-P5118 - Q62702-P5118 Q62702-P5118 Datasheet
PBSS4620PA - PBSS4620PA PBSS4620PA Datasheet
NL3224AC35-01 - NL3224AC35-01 NL3224AC35-01 Datasheet
MMBZ4681-V - MMBZ4681-V MMBZ4681-V Datasheet
MMBZ4717-V - MMBZ4717-V MMBZ4717-V Datasheet
MAX3318E - MAX3318E MAX3318E Datasheet
LMB202DBC - LMB202DBC LMB202DBC Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
