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SST25WF512 SST25WF010 SST25WF020 SST25VF016B16Mb Serial Periphera


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Kbit Mbit Mbit 1.8V Serial Flash
SST25WF512 SST25WF010 SST25WF020
SST25VF016B16Mb Serial Peripheral Interface (SPI) flash memory
FEATURES:
Single Voltage Read Write Operations 1.65-1.95V Serial Interface Architecture Compatible: Mode Mode High Speed Clock Frequency 40MHz Superior Reliability Endurance: 100,000 Cycles Greater than years Data Retention Ultra-Low Power Consumption: Active Read Current: (typical 20MHz) Standby Current: (typical) Flexible Erase Capability Uniform KByte sectors Uniform KByte overlay blocks Uniform KByte overlay blocks Mbit only) Fast Erase Byte-Program: Chip-Erase Time: (typical) Sector-/Block-Erase Time: 62ms (typical) Byte-Program Time: (typical) Auto Address Increment (AAI) Programming Decrease total chip programming time over Byte-Program operations End-of-Write Detection Software polling BUSY Status Register Busy Status readout Reset (RST#) Programmable Hold (HOLD#) option Hardware Reset default Hold option suspend serial sequence without deselecting device Write Protection (WP#) Enables/Disables Lock-Down function status register Software Write Protection Write protection through Block-Protection bits status register Temperature Range Industrial: -40°C +85°C Packages Available 8-lead SOIC (150 mils) non-Pb (lead-free) devices RoHS compliant
PRODUCT DESCRIPTION
SST25WF512/010/020 members Serial Flash Series family features four-wire, SPI-compatible interface that allows pin-count package which occupies less board space ultimately lowers total system costs. SST25WF512/010/020 serial flash memories manufactured with proprietary, highperformance CMOS SuperFlash technology. split-gate cell design thick-oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST25WF512/010/020 devices significantly improve performance reliability, while lowering power consumption. devices write (Program Erase) with single power supply 1.65-1.95V SST25WF512/010/020. total energy consumed function applied voltage, current, time application. Since given voltage range, SuperFlash technology uses less current program shorter erase time, total energy consumed during Erase Program operation less than alternative flash memory technologies. SST25WF512/010/020 devices offered 8lead, mils SOIC package. Figure assignment.
©2006 Silicon Storage Technology, Inc. S71328-01-000 02/07
logo SuperFlash registered Trademarks Silicon Storage Technology, Inc. These specifications subject change without notice.
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
Address Buffers Latches
Decoder
SuperFlash Memory
Decoder
Control Logic
Buffers Data Latches
Serial Interface
RST#/HOLD#
1328 F01.0
Note: mode, functions RY/BY# when configured ready/busy status pin. "End-of-Write Detection" page more information.
FIGURE Functional Block Diagram
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
DESCRIPTION
View RST#/HOLD#
1328.25WF 08-soic-P0.0
FIGURE Assignment 8-Lead SOIC TABLE Description
Symbol Name Serial Clock Functions provide timing serial interface. Commands, addresses, input data latched rising edge clock input, while output data shifted falling edge clock input. transfer commands, addresses, data serially into device. Inputs latched rising edge serial clock. transfer data serially device. Data shifted falling edge serial clock. Flash busy status mode configured hardware RY/BY# pin. "End-of-Write Detection" page more information. device enabled high transition CE#. must remain duration command sequence. Write Protect (WP#) used enable/disable status register. reset operation device internal logic. device powers with RST# functionality default. temporarily stop serial communication with Flash memory while device selected. This selected instruction sequence which detailed "Reset/Hold Mode" page provide power supply voltage: 1.65-1.95V SST25WF512/010/020
T1.0 1328
Serial Data Input Serial Data Output
RST#/HOLD#
Chip Enable Write Protect Reset Hold
Power Supply Ground
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
MEMORY ORGANIZATION
SST25WF512/010/020 SuperFlash memory arrays organized uniform KByte with KByte, KByte, KByte (2Mbit Only) overlay erasable blocks.
used select device, data accessed through Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK). SST25WF512/010/020 support both Mode (0,0) Mode (1,1) operations. difference between modes, shown Figure state signal when master Stand-by mode data being transferred. signal Mode signal high Mode both modes, Serial Data (SI) sampled rising edge clock signal Serial Data Output (SO) driven after falling edge clock signal.
DEVICE OPERATION
SST25WF512/010/020 accessed through (Serial Peripheral Interface) compatible protocol. consist four control lines; Chip Enable (CE#)
MODE MODE MODE
MODE
DON'T CARE
1328 F03.0
HIGH IMPEDANCE
FIGURE Protocol
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
Reset/Hold Mode
RST#/HOLD# provides either hardware reset hold pin. From power-on, RST#/HOLD# defaults hardware reset (RST#). Hold mode this user selected option where Enable-Hold instruction enables Hold mode. Once selected hold (HOLD#), RST#/HOLD# will configured HOLD# pin, goes back RST# only after poweroff power-on sequence. Reset RST#/HOLD# used reset pin, RST# provides hardware method resetting device. Driving RST# high puts device normal operating mode. RST# must driven minimum TRST time reset device. high impedance state while device reset. successful reset will reset status register power-up state. Table default power-up modes. device reset during active Program Erase operation aborts operation data targeted address range corrupted lost aborted erase program operation. device exits Programming Mode progress places high impedance state.
TRECR TRECP TRECE TRST RST# TRHZ
1328 Fx4.0
FIGURE Reset Timing Diagram TABLE Reset Timing Parameters
Symbol TRST TRHZ TRECR TRECP TRECE Parameter Reset Pulse Width Reset High-Z Output Reset Recovery from Read Reset Recovery from Program Reset Recovery from Erase Units
T2.1328
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
Advance Information Hold Hold operation enables hold functionality RST#/HOLD# pin. Once hold mode, RST#/ HOLD# continues functioning hold until device powered then powered After poweroff power-on, functionality returns reset (RST#) mode. "Enable-Hold (EHLD)" page detailed timing Hold instruction. hold mode, serial sequences underway with Flash memory paused without resetting clocking sequence. activate HOLD# mode, must active state. HOLD# mode begins when active state coincides with falling edge HOLD# signal. Hold mode ends when rising edge HOLD# signal coincides with active state. falling edge HOLD# signal does coincide with active state, then device enters Hold mode when next reaches active state. Similarly, rising edge HOLD# signal does coincide with active state, then device exits Hold mode when next reaches active state. Figure Hold Condition waveform. Once device enters Hold mode, will highimpedance state while VIH. driven active high during Hold condition, device returns standby mode. device then re-initiated with command sequences listed Tables long HOLD# signal low, memory remains Hold condition. resume communication with device, HOLD# must driven active high, must driven active low. Figure Hold timing.
HOLD# Active Hold Active Hold Active
1328 Fx5.0
FIGURE Hold Condition Waveform
Write Protection
SST25WF512/010/020 provide software Write protection. Write Protect (WP#) enables disables lockdown function status register. Block-Protection bits (BP1, BP0, BPL) status register provide Write protection memory array status register. Table Block-Protection description. Write Protect (WP#) Write Protect (WP#) enables lock-down function (bit status register. When driven low, execution Write-Status-Register (WRSR) instruction determined value (see Table When high, lock-down function disabled.
TABLE Conditions execute Write-Status-Register (WRSR) Instruction
Execute WRSR Instruction Allowed Allowed Allowed
T3.0 1328
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
Status Register
software status register provides status whether flash memory array available Read Write operation, whether device Write enabled, state Memory Write protection. During internal Erase TABLE Software Status Register
Name BUSY Function Internal Write operation progress internal Write operation progress Device memory Write enabled Device memory Write enabled Indicate current level block write protection (See Table Indicate current level block write protection (See Table Reserved future Auto Address Increment Programming status programming mode Byte-Program mode read-only bits read/writable Default Power-up Read/Write
Program operation, status register read only determine completion operation progress. Table describes function each software status register.
T4.1 1328
Busy Busy determines whether there internal Erase Program operation progress. Busy indicates device busy with operation progress. indicates device ready next valid operation. Write Enable Latch (WEL) Write-Enable-Latch indicates status internal Write-Enable-Latch memory. `1', indicates device Write enabled. (reset), indicates device Write enabled does accept Write (Program/Erase) commands. Write-Enable-Latch automatically reset under following conditions: Device Reset Power-up Write-Disable (WRDI) instruction completion Byte-Program instruction completion Auto Address Increment (AAI) programming completed reached highest unprotected memory address Sector-Erase instruction completion Block-Erase instruction completion Chip-Erase instruction completion Write-Status-Register instructions
Auto Address Increment (AAI) Auto Address Increment Programming-Status provides status whether device programming mode Byte-Program mode. default power Byte-Program mode.
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
Advance Information Block-Protection (BP1, BP0) Block-Protection (BP1, BP0) bits define size memory area software protected against memory Write (Program Erase) operation, Tables 5-7. Write-Status-Register (WRSR) instruction used program bits long high Block-Protect-Lock (BPL) `0'. Chip-Erase only executed Block-Protection bits `0'. After powerup, defaults. Table defaults power-up. Block Protection Lock-Down (BPL) When driven (VIL), enables BlockProtection-Lock-Down (BPL) bit. When `1', prevents further alteration BPL, BP1, bits. When driven high (VIH), effect value `Don't Care'. After power-up, reset `0'.
TABLE Software Status Register Block Protection SST25WF512
Status Register Protection Level None (Upper Quarter Memory) (Upper Half Memory) (Full Memory)
Default power-up `11'.
Protected Memory Address Kbit None 00C000H-00FFFFH 008000H-00FFFFH 000000H-00FFFFH
T5.1 1328
BP11
TABLE Software Status Register Block Protection SST25WF010
Status Register Protection Level None (Upper Quarter Memory) (Upper Half Memory) (Full Memory)
Default power-up `11'.
Protected Memory Address Mbit None 018000H-01FFFFH 010000H-01FFFFH 000000H-01FFFFH
T6.0 1328
BP11
TABLE Software Status Register Block Protection SST25WF020
Status Register Protection Level None (Upper Quarter Memory) (Upper Half Memory) (Full Memory)
Default power-up `11'.
Protected Memory Address Mbit None 030000H-03FFFFH 020000H-03FFFFH 000000H-03FFFFH
T7.0 1328
BP11
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
INSTRUCTIONS
Instructions used read, write (Erase Program), configure SST25WF512/010/020. instruction cycles bits each commands Code), data, addresses. Write-Enable (WREN) instruction must executed prior Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-Status-Register, Chip-Erase instructions. complete instructions provided Tables instructions synchronized high-to-low transition CE#. Inputs will accepted rising edge starting with most significant bit. must driven before instruction entered must driven high after last instruction been shifted (except Read, Read-ID, Read-Status-Register instructions). low-to-high transition CE#, before receiving last instruction cycle, will terminate instruction progress return device standby mode. Instruction commands Code), addresses, data input from most significant (MSB) first.
TABLE Device Operation Instructions SST25WF512 SST25WF010
Instruction Read High-Speed Read KByte SectorErase3 KByte BlockErase4 Chip-Erase Byte-Program AAI-Word-Program5 RDSR6 EWSR7 WRSR WREN7 WRDI RDID8 EBSY DBSY JEDEC-ID EHLD Description Read Memory Erase KByte memory array Erase KByte block memory array Erase Full Memory Array Program Data Byte Auto Address Increment Programming Read-Status-Register Enable-Write-Status-Register Write-Status-Register Write-Enable Write-Disable Read-ID Code Cycle1 0000 0011b (03H) 0010 0000b (20H) 0101 0010b (52H) 0110 0000b (60H) 1100 0111b (C7H) 0000 0010b (02H) 1010 1101b (ADH) 0000 0101b (05H) 0110 0000b (50H) 0000 0001b (01H) 0000 0110b (06H) 0000 0100b (04H) 1001 0000b (90H) 1010 1011b (ABH) Address Cycle(s)2 Dummy Data Maximum Cycle(s) Cycle(s) Frequency
T8.0 1328
Read Memory Higher Speed 0000 1011b (0BH)
Enable output RY/BY# 0111 0000b (70H) status during programming Disable output RY/BY# 1000 0000b (80H) status during programming JEDEC read Enable HOLD# functionality RST#/HOLD# 1001 1111b (9FH) 1010 1010b (AAH)
cycle eight clock periods. Address bits above most significant each density VIH. KByte Sector-Erase addresses: AMS-A12, remaining addresses don't care must either VIH. KByte Block-Erase addresses: AMS-A15, remaining addresses don't care must either VIH. continue programming next sequential address location, enter 8-bit command, ADH, followed bytes data programmed. Data Byte will programmed into initial address [A23-A1] with A0=0, Data Byte will programmed into initial address [A23-A1] with Read-Status-Register continuous with ongoing clock cycles until terminated high transition CE#. Either EWSR WREN followed WRSR will write Status register. EWSR-WRSR sequence provides backward compatibility SST25VF/LF series. WREN-WRSR sequence recommended designs. Manufacturer's read with A0=0, Device read with A0=1. other address bits 00H. Manufacturer's device output stream continuous until terminated low-to-high transition CE#.
©2006 Silicon Storage Technology, Inc. S71328-01-000 02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
Advance Information TABLE Device Operation Instructions SST25WF020
Instruction Read High-Speed Read KByte SectorErase3 KByte BlockErase4 KByte BlockErase5 Chip-Erase Byte-Program AAI-Word-Program6 RDSR7 EWSR8 WRSR WREN8 WRDI RDID9 EBSY DBSY JEDEC-ID EHLD Description Read Memory Erase KByte memory array Erase KByte block memory array Erase KByte block memory array Erase Full Memory Array Program Data Byte Auto Address Increment Programming Read-Status-Register Enable-Write-Status-Register Write-Status-Register Write-Enable Write-Disable Read-ID Code Cycle1 0000 0011b (03H) 0010 0000b (20H) 0101 0010b (52H) 1101 1000b (D8H) 0110 0000b (60H) 1100 0111b (C7H) 0000 0010b (02H) 1010 1101b (ADH) 0000 0101b (05H) 0110 0000b (50H) 0000 0001b (01H) 0000 0110b (06H) 0000 0100b (04H) 1001 0000b (90H) 1010 1011b (ABH) Address Cycle(s)2 Dummy Data Maximum Cycle(s) Cycle(s) Frequency
T9.0 1328
Read Memory Higher Speed 0000 1011b (0BH)
Enable output RY/BY# 0111 0000b (70H) status during programming Disable output RY/BY# 1000 0000b (80H) status during programming JEDEC read Enable HOLD# functionality RST#/HOLD# 1001 1111b (9FH) 1010 1010b (AAH)
cycle eight clock periods. Address bits above most significant each density VIH. KByte Sector-Erase addresses: AMS-A12, remaining addresses don't care must either VIH. KByte Block-Erase addresses: AMS-A15, remaining addresses don't care must either VIH. KByte Block-Erase addresses: AMS-A16, remaining addresses don't care must either VIH. continue programming next sequential address location, enter 8-bit command, ADH, followed bytes data programmed. Data Byte will programmed into initial address [A23-A1] with A0=0, Data Byte will programmed into initial address [A23-A1] with Read-Status-Register continuous with ongoing clock cycles until terminated high transition CE#. Either EWSR WREN followed WRSR will write Status register. EWSR-WRSR sequence provides backward compatibility SST25VF/LF series. WREN-WRSR sequence recommended designs. Manufacturer's read with A0=0, Device read with A0=1. other address bits 00H. Manufacturer's device output stream continuous until terminated low-to-high transition CE#.
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
Read MHz)
Read instruction, 03H, supports Read. device outputs data stream starting from specified address location. data stream continuous through addresses until terminated low-to-high transition CE#. internal address pointer automatically increments until highest memory address reached. Once highest memory address reached, address pointer automatically increments beginning (wraparound) address space. example, Mbit density, once data from address location 3FFFFH read, next output from address location 000000H. Read instruction initiated executing 8-bit command, 03H, followed address bits A23-A0. must remain active duration Read cycle. Figure Read sequence.
MODE
MODE
ADD. HIGH IMPEDANCE
ADD.
ADD. DOUT
1328 Fx6.0
DOUT
DOUT
DOUT
DOUT
FIGURE Read Sequence
High-Speed-Read MHz)
High-Speed-Read instruction supporting Read initiated executing 8-bit command, 0BH, followed address bits [A23-A0] dummy byte. must remain active duration High-SpeedRead cycle. Figure High-Speed-Read sequence. Following dummy cycle, High-Speed-Read instruction outputs data starting from specified address location. data output stream continuous through addresses until terminated low-to-high transition CE#. internal address pointer will automatically increment until highest memory address reached. Once highest memory address reached, address pointer will automatically increment beginning (wraparound) address space. example, Mbit density, once data from address location 3FFFFH read, next output will from address location 000000H.
MODE MODE
ADD. HIGH IMPEDANCE
ADD.
ADD.
DOUT DOUT DOUT DOUT DOUT
1328 F07.0
FIGURE High-Speed-Read Sequence
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
Byte-Program
Byte-Program instruction programs bits selected byte desired data. selected byte must erased state (FFH) when initiating Program operation. Byte-Program instruction applied protected memory area will ignored. Prior Write operation, Write-Enable (WREN) instruction must executed. must remain active duration Byte-Program instruction. ByteProgram instruction initiated executing 8-bit command, 02H, followed address bits [A23-A0]. Following address, data input order from (bit (bit must driven high before instruction executed. user poll Busy software status register wait completion internal self-timed Byte-Program operation. Figure Byte-Program sequence.
MODE
MODE
ADD.
ADD.
ADD.
HIGH IMPEDANCE
1328 F08.0
FIGURE Byte-Program Sequence
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
Auto Address Increment (AAI) Word-Program
program instruction allows multiple bytes data programmed without re-issuing next sequential address location. This feature decreases total programming time when multiple bytes entire memory array programmed. Word program instruction pointing protected memory area will ignored. selected address range must erased state (FFH) when initiating Word Program operation. While within Word Programming sequence, only valid instructions Word (ADH), RDSR (05H), WRDI (04H). Users have three options determine completion each Word program cycle: hardware detection reading Serial Output, software detection polling BUSY software status register wait TBP. Refer End-Of-Write Detection section details. Prior write operation, Write-Enable (WREN) instruction must executed. Word Program instruction initiated executing 8-bit command, ADH, followed address bits [A23-A0]. Following addresses, bytes data input sequentially, each from (Bit (Bit first byte data (D0) will programmed into initial address [A23-A1] with second byte Data (D1) will programmed into initial address [A23-A1] with must driven high before Word Program instruction executed. user must check BUSY status before entering next valid command. Once device indicates longer busy, data next sequential addresses programmed When last desired byte been entered, check busy status using hardware method RDSR instruction execute Write-Disable (WRDI) instruction, 04H, terminate AAI. Check busy status after WRDI determine device ready command. Figures Word programming sequence. There wrap mode during programming; once highest unprotected memory address reached, device will exit operation reset Write-EnableLatch (WEL (AAI End-of-Write Detection There three methods determine completion program cycle during Word programming: hardware detection reading Serial Output, software detection polling BUSY Software Status Register wait
Hardware End-of-Write Detection Hardware End-of-Write detection method eliminates overhead polling Busy Software Status Register during Word program operation. 8-bit command, 70H, configures Serial Output (SO) indicate Flash Busy status during Word programming, shown Figure 8-bit command, 70H, must executed prior executing Word-Program instruction. Once internal programming operation begins, asserting will immediately drive status internal flash status pin. indicates device busy indicates device ready next instruction. De-asserting will return tristate. 8-bit command, 80H, disables Serial Output (SO) output busy status during AAI-Word-program operation, re-configures output pin. this state, will function normal Serial Output pin. this time, RDSR command poll status Software Status Register. This shown Figure
MODE
MODE
HIGH IMPEDANCE
1328 F09.0
FIGURE Enable Hardware RY/BY# during Programming
MODE
MODE
HIGH IMPEDANCE
1328 F10.0
FIGURE Disable Hardware RY/BY# during Programming
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
WREN
Dn-1 Last Data Bytes WRDI RDSR
Load command, Address, bytes data
WRDI exit Mode DOUT
Check Flash Busy Status load next valid command
Output Status Register Data
Note: Valid commands during programming: command WRDI command User must configure output Flash Busy status during programming
1328 F11.1
FIGURE Auto Address Increment (AAI) Word Program Sequence with Hardware End-of-Write Detection
Check Flash Busy Status load next valid command
WREN
Dn-1 Last Data Bytes WRDI WRDI exit Mode DOUT RDSR
Load command, Address, bytes data
Output Status Register Data
Note:
Valid commands during programming: command, Read Status Register command, WRDI command
1328 F12.1
FIGURE Auto Address Increment (AAI) Word Program Sequence with Software End-of-Write Detection
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
Sector-Erase
Sector-Erase instruction clears bits selected KByte sector FFH. Sector-Erase instruction applied protected memory area will ignored. Prior Write operation, Write-Enable (WREN) instruction must executed. must remain active duration command sequence. Sector-Erase instruction initiated executing 8-bit command, 20H, followed address bits [A23-A0]. Address bits [AMS-A12] (AMS Most Significant address) used determine sector address (SAX), remaining address bits VIH. must driven high before instruction executed. user poll Busy software status register wait completion internal self-timed Sector-Erase cycle. Figure Sector-Erase sequence.
MODE
MODE
ADD.
ADD.
ADD.
HIGH IMPEDANCE
1326 F13.0
FIGURE Sector-Erase Sequence
32-KByte Block-Erase
Block-Erase instruction clears bits selected KByte block FFH. Block-Erase instruction applied protected memory area ignored. Prior Write operation, Write-Enable (WREN) instruction must executed. must remain active duration command sequence. Block-Erase instruction initiated executing 8-bit command, 52H, followed address bits [A23-A0]. Address bits [AMS-A15] (AMS Most Significant Address) used determine block address (BAX), remaining address bits VIH. must driven high before instruction executed. Poll Busy software status register wait completion internal self-timed Block-Erase. Figure Block-Erase sequences.
MODE
MODE
ADDR
ADDR
ADDR
HIGH IMPEDANCE
1328 F14.0
FIGURE 32-KByte Block-Erase Sequence
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
64-KByte Block-Erase SST25WF020
Block-Erase instruction clears bits selected KByte block FFH. Block-Erase instruction applied protected memory area ignored. Prior Write operation, Write-Enable (WREN) instruction must executed. must remain active duration command sequence. Block-Erase instruction initiated executing 8-bit command, D8H, followed address bits [A23-A0]. Address bits [AMS-A16] (AMS Most Significant Address) used determine block address (BAX), remaining address bits VIH. must driven high before instruction executed. Poll Busy software status register wait completion internal self-timed Block-Erase. Figure Block-Erase sequences.
MODE
MODE
ADDR
ADDR
ADDR
HIGH IMPEDANCE
1328 F15.0
FIGURE 64-KByte Block-Erase Sequence
Chip-Erase
Chip-Erase instruction clears bits device FFH. Chip-Erase instruction ignored memory area protected. Prior Write operation, Write-Enable (WREN) instruction must executed. must remain active duration Chip-Erase instruction sequence. Chip-Erase instruction initiated executing 8-bit command, C7H. must driven high before instruction executed. user poll Busy software status register wait completion internal self-timed Chip-Erase cycle. Figure Chip-Erase sequence.
MODE
MODE
HIGH IMPEDANCE
1328 F16.0
FIGURE Chip-Erase Sequence
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
Read-Status-Register (RDSR)
Read-Status-Register (RDSR) instruction, 05H, allows reading status register. status register read time even during Write (Program/Erase) operation. When Write operation progress, Busy checked before sending commands assure that commands properly received device. must driven before RDSR instruction entered remain until status data read. Read-Status-Register continuous with ongoing clock cycles until terminated high transition CE#. Figure RDSR instruction sequence.
MODE
MODE
HIGH IMPEDANCE
Status Register
1327 F17.0
FIGURE Read-Status-Register (RDSR) Sequence
Write-Enable (WREN)
Write-Enable (WREN) instruction, 06H, sets WriteEnable-Latch Status Register allowing Write operations occur. WREN instruction must executed prior Write (Program/Erase) operation. WREN instruction also used allow execution Write-Status-Register (WRSR) instruction; however, Write-Enable-Latch Status Register will cleared upon rising edge WRSR instruction. must driven high before WREN instruction executed. Figure WREN instruction sequence.
MODE
MODE
HIGH IMPEDANCE
1328 F18.0
FIGURE Write Enable (WREN) Sequence
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
Write-Disable (WRDI)
Write-Disable (WRDI) instruction, 04H, resets Write-Enable-Latch disabling Write operations from occurring. WRDI instruction will terminate programming operation progress. program operation progress continue after executing WRDI instruction. must driven high before WRDI instruction executed. Figure WRDI instruction sequence.
MODE
MODE
HIGH IMPEDANCE
1328 Fx19.0
FIGURE Write Disable (WRDI) Sequence
Enable-Write-Status-Register (EWSR)
Enable-Write-Status-Register (EWSR) instruction arms Write-Status-Register (WRSR) instruction opens status register alteration. Write-StatusRegister instruction must executed immediately after execution Enable-Write-Status-Register instruction. This two-step instruction sequence EWSR instruction followed WRSR instruction works like (software data protection) command structure which prevents accidental alteration status register values. must driven before EWSR instruction entered must driven high before EWSR instruction executed. Figure EWSR instruction followed WRSR instruction.
WRSR instruction entered driven high before WRSR instruction executed. Figure EWSR WREN WRSR instruction sequences. Executing Write-Status-Register instruction will ignored when `1'. When low, only from lock-down status register, cannot reset from `0'. When high, lock-down function disabled BPL, BP0, bits status register changed. long driven high (VIH) prior low-to-high transition WRSR instruction, bits status register altered WRSR instruction. this case, single WRSR instruction lock down status register well altering BP0, bits same time. Table summary description functions.
Write-Status-Register (WRSR)
Write-Status-Register instruction writes values BP1, BP0, bits status register. must driven before command sequence
MODE
MODE
MODE
MODE
HIGH IMPEDANCE
STATUS REGISTER
1328 F20.0
FIGURE Enable-Write-Status-Register (EWSR) Write-Enable (WREN) Write-Status-Register (WRSR) Sequence
©2006 Silicon Storage Technology, Inc. S71328-01-000 02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
Enable-Hold (EHLD)
8-bit command, AAH, Enable-Hold instruction enables HOLD functionality RST#/HOLD# pin. must remain active duration Enable-Hold instruction sequence. must driven high before instruction executed. Figure Enable-Hold instruction sequence.
MODE
MODE
HIGH IMPEDANCE
1328 F21.0
FIGURE Enable-Hold Sequence
Read-ID
Read-ID instruction identifies manufacturer device SST25WF512/010/020. ReadID instruction identify device when using multiple manufacturers same socket. Table device information read executing 8-bit command, ABH, followed address bits [A23-A0]. Following Read-ID instruction, manufacturer's located address 000000H device located address 000001H. Once device Read-ID mode, manufacturer's device output data toggles between address 000000H 000001H until terminated high transition CE#. TABLE Product Identification
Address Manufacturer's Device SST25WF512 SST25WF010 SST25WF020 000000H 000001H 000001H 000001H Data
T10.1328
MODE
MODE
HIGH IMPEDANCE
Device
Device
HIGH IMPEDANCE
Note: manufacturer's device output stream continuous until terminated high transition CE#. will output manfacturer's first will output device first before toggling between two.
1328 F22.0
FIGURE Read-ID Sequence
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
JEDEC Read-ID
JEDEC Read-ID instruction identifies device SST25WF512/010/020 manufacturer SST. device information read from executing 8-bit command, 9FH. Following JEDEC Read-ID instruction, 8-bit manufacturer's BFH, output from device. After that, 16-bit device shifted pin. Device assigned manufacturer contains type memory first byte memory capacity device second byte. Figure instruction sequence. JEDEC Read instruction terminated high transition time during data output.
MODE
MODE
HIGH IMPEDANCE
01/02/03
Note:
indicates 25WF512, indicates 25WF010, indicates 25WF020
1328 F23.0
FIGURE JEDEC Read-ID Sequence TABLE JEDEC Read-ID Data-Out SST25WF512
Device Manufacturer's (Byte Memory Type (Byte Memory Capacity (Byte
T11.0 1328
TABLE JEDEC Read-ID Data-Out SST25WF010
Device Manufacturer's (Byte Memory Type (Byte Memory Capacity (Byte
T12.0 1328
TABLE JEDEC Read-ID Data-Out SST25WF020
Device Manufacturer's (Byte Memory Type (Byte Memory Capacity (Byte
T13.0 1328
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VDD+0.5V Transient Voltage (<20 Ground Potential -2.0V VDD+2.0V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Solder Reflow Temperature 260°C seconds Output Short Circuit Current1
Output shorted more than second. more than output shorted time.
Operating Range
Range Industrial Industrial (extended)1 Ambient Temp -40°C +85°C -40°C +105°C 1.65-1.95V 1.70-1.90V
Conditions Test
Input Rise/Fall Time Output Load
Maximum operating frequency Extended Industrial temperature range.
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
Power-Up Specifications
functionalities specifications specified ramp rate greater than 1.8V less than ms). ramp rate slower than 1V/100 hardware reset required. recommended power-up RESET# high time should greater than ensure proper reset. Table Figures more information. TABLE Recommended System Power-up Timings
Symbol TPU-READ1 TPU-WRITE1 Parameter Read Operation Write Operation Minimum Units
T14.0 1328
This parameter measured only initial qualification after design process change that could affect this parameter.
TPU-READ
RESET#
TRECR
1328 F37.1
Note: Table page TRECR parameter.
FIGURE Power-Up Reset Diagram
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
Chip selection allowed. Commands accepted properly interpreted device.
TPU-READ TPU-WRITE
Device fully accessible
Time
1326 F27.0
FIGURE Power-up Timing Diagram
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
Characteristics
TABLE Operating Characteristics
Limits Symbol IDDR IDDR2 IDDW Parameter Read Current Read Current Program Erase Current Standby Current Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Output Voltage Output High Voltage VDD-0.2 Typ1 Units Test Conditions CE#=0.1 VDD/0.9 VDD@20 MHz, SO=open CE#=0.1 VDD/0.9VDD@40 MHz, SO=open CE#=VDD CE#=VDD, VIN=VDD VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD IOL=100 VDD=VDD IOH=-100 VDD=VDD
T15.0 1328
Value characterized, fully tested production.
TABLE Capacitance 25°C, Mhz, other pins open)
Parameter COUT CIN1
Description Output Capacitance Input Capacitance
Test Condition VOUT
Maximum
T16.0 1328
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE Reliability Characteristics
Symbol NEND TDR1 ILTH1
Parameter Endurance Data Retention Latch
Minimum Specification 100,000
Units Cycles Years
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T17.0 1328
This parameter measured only initial qualification after design process change that could affect this parameter.
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
Characteristics
TABLE Operating Characteristics
Limits Symbol FCLK
Limits Units
T18.1 1328
Parameter Serial Clock Frequency Serial Clock High Time Serial Clock Time Serial Clock Rise Time Serial Clock Fall Time Active Setup Time Active Hold Time Active Setup Time Active Hold Time High Time High High-Z Output Low-Z Output Data Setup Time Data Hold Time HOLD# Setup Time HOLD# High Setup Time HOLD# Hold Time HOLD# High Hold Time HOLD# High-Z Output HOLD# High Low-Z Output Output Hold from Change Output Valid from Sector-Erase Block-Erase Chip-Erase Byte-Program
TSCKH TSCKL TSCKR TSCKF TCES2 TCEH2 TCHS2 TCHH2 TCPH TCHZ TCLZ THLS THHS THLH THHH TSCE
Maximum clock frequency Read instruction, 03H, Relative AAI-Word Program maximum specification also maximum time
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
TCPH TCHH TSCKR TSCKF TCES TCEH TCHS
HIGH-Z
HIGH-Z
1326 F24.0
FIGURE Serial Input Timing Diagram
TSCKH TCLZ
1328 F25.0
TSCKL
TCHZ
FIGURE Serial Output Timing Diagram
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
THHH THLH THLS THHS
HOLD#
1328 F26.0
FIGURE Hold Timing Diagram
VIHT
INPUT? REFERENCE POINTS
OUTPUT
VILT
1326 F28.0
test inputs driven VIHT (0.9VDD) logic VILT (0.1VDD) logic `0'. Measurement reference points inputs outputs (0.6VDD) (0.4VDD). Input rise fall times (10% 90%)
Note: VHIGH Test VLOW Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE Input/Output Reference Waveforms
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
PRODUCT ORDERING INFORMATION
Environmental Attribute non-Pb non-Sn contact (lead) finish: Nickel plating with Gold (outer) layer Package Modifier leads Package Type SOIC body width Temperature Range Industrial -40°C +85°C Minimum Endurance 100,000 cycles Operating Frequency Device Density Kbit Mbit Mbit Voltage 1.65-1.95V Product Series Serial Peripheral Interface flash memory
Environmental suffix denotes non-Pb/non-SN solder. non-Pb/non-Sn solder devices "RoHS Compliant".
Valid combinations SST25WF512 SST25WF512-40-5I-SAF Valid combinations SST25WF010 SST25WF010-40-5I-SAF Valid combinations SST25WF020 SST25WF020-40-5I-SAF
Note: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2006 Silicon Storage Technology, Inc.
S71328-01-000
02/07
Kbit Mbit Mbit 1.8V Serial Flash SST25WF512 SST25WF010 SST25WF020
PACKAGING DIAGRAMS
Identifier
VIEW
SIDE VIEW
places
1.27
0.51 0.33
VIEW
0.25 0.10 1.75 1.35 0.25 0.19 1.27 0.40 places
4.00 3.80 6.20 5.80
Note: Complies with JEDEC publication MS-012 dimensions, although some dimensions more stringent. linear dimensions millimeters (max/min). Coplanarity: Maximum allowable mold flash 0.15 package ends 0.25 between leads.
08-soic-5x6-SA-8
FIGURE 8-Lead Small Outline Integrated Circuit (SOIC) Package Code: TABLE Revision History
Number Description Date 2006 2007
Initial release data sheet Removed "Commercial" Temperature Range Added references Tables "Block-Protection (BP1, BP0)" page Modified EWSR WREN footnote information updated EBSY Code Cycle Tables Re-phrased first paragraph "Instructions" page Updated "Byte-Program" page Clarified statement second paragraph "Hardware End-of-Write Detection" page Added Industrial (extended) values Operating Range "Electrical Specifications" page Added "Power-Up Specifications" page Added typical values Table page Added contact-lead composition, updated minimum endurance from 10,000 100,000 cycles, changed product valid combinations "Product Ordering Information" page
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2006 Silicon Storage Technology, Inc. S71328-01-000 02/07

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