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Am29F004B
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Publication Number Am29F004B_00
Revision
Amendment
Issue Date 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29F004B
Megabit (512 8-Bit) CMOS Volt-only Boot Sector Flash Memory
This product been retired recommended designs. Please contact your Spansion representative alternates. Availability this document retained reference historical purposes only.
DISTINCTIVE CHARACTERISTICS
Volt single power supply operation Minimizes system-level power requirements High performance Access times fast Manufactured 0.32 process technology Ultra power consumption (typical values MHz) typical active read current typical program/erase current typical standby mode current Flexible sector architecture Kbyte, Kbyte, Kbyte, seven Kbyte sectors Supports full chip erase Sector Protection features: hardware method locking sector prevent program erase operations within that sector Sectors locked in-system programming equipment Temporary Sector Unprotect feature allows code changes previously locked sectors bottom boot block configurations available Minimum 1,000,000 write cycle guarantee sector Package option 32-pin PLCC Compatible with JEDEC standards Pinout software compatible with singlepower supply Flash Superior inadvertent write protection Embedded Algorithms Embedded Erase algorithm automatically preprograms erases entire chip combination designated sectors Embedded Program algorithm automatically writes verifies data specified addresses Erase Suspend/Erase Resume Suspends erase operation read data from, program data sector that being erased, then resumes erase operation Data# Polling toggle bits Provides software method detecting program erase operation completion 20-year data retention 125°C
This Data Sheet states AMD's current technical specifications regarding Products described herein. This Data Sheet revised subsequent versions modifications changes technical specifications.
Publication# Am29F004B_00 Revision: Amendment: Issue Date: 2006
GENERAL DESCRIPTION
Am29F004B Mbit, volt-only Flash memory device organized 524,288 bytes. data appears DQ0-DQ7. device offered 32-pin PLCC package. This device designed programmed in-system with standard system volt supply. 12.0 volt required program erase operations. device also programmed standard EPROM programmers. device offers access times allowing high speed microprocessors operate without wait states. eliminate contention each device separate chip enable (CE#), write enable (WE#) output enable (OE#) controls. Each device requires only single volt power supply both read write functions. Internally generated regulated voltages provided program erase operations. Am29F004B entirely command compatible with JEDEC single-power-supply Flash standard. Commands written command register using standard microprocessor write timing. Register contents serve inputs internal state-machine that controls erase programming circuitry. Write cycles also internally latch addresses data needed programming erase operations. Reading data device similar reading from other Flash EPROM devices. Device programming occurs executing program command sequence. This initiates Embedded Program algorithm-an internal algorithm that automatically times program pulse widths verifies proper cell margin. Device erasure occurs executing erase command sequence. This initiates Embedded Erase algorithm-an internal algorithm that automatically preprograms array already programmed) before executing erase operation. During erase, device automatically times erase pulse widths verifies proper cell margin. host system detect whether program erase operation complete reading (Data# Polling), (toggle) status bits. After program erase cycle completed, device ready read array data accept another command. sector erase architecture allows memory sectors erased reprogrammed without affecting data contents other sectors. device fully erased when shipped from factory. Hardware data protection measures include detector that automatically inhibits write operations during power transitions. hardware sector protection feature disables both program erase operations combination sectors memory. This achieved in-system programming equipment. Erase Suspend feature enables user erase hold period time read data from, program data sector that selected erasure. True background erase thus achieved. device offers standby mode power-saving feature. Once system places device into standby mode power consumption greatly reduced. AMD's Flash technology combines years Flash memory manufacturing experience produce highest levels quality, reliability cost effectiveness. device electrically erases bits within sector simultaneously FowlerNordheim tunnelling. data programmed using electron injection.
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TABLE CONTENTS
Product Selector Guide Block Diagram Connection Diagrams Configuration Logic Symbol Ordering Information Device Operations
Am29F004B Device Operations
DQ6: Toggle DQ2: Toggle Reading Toggle Bits DQ6/DQ2 DQ5: Exceeded Timing Limits DQ3: Sector Erase Timer
Toggle Algorithm Write Operation Status
Absolute Maximum Ratings
Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform
Requirements Reading Array Data Writing Commands/Command Sequences Program Erase Operation Status Standby Mode Output Disable Mode
Am29F004B Boot Block Sector Addresses Am29F004B Bottom Boot Block Sector Addresses
Operating Ranges Characteristics TTL/NMOS Compatible CMOS Compatible Test Conditions
Test Setup Test Specifications
Autoselect Mode
Am29F004B Autoselect Codes (High Voltage Method)
Sector Protection/Unprotection
In-System Sector Protect/Sector Unprotect Algorithms
Temporary Sector Unprotect
Temporary Sector Unprotect Operation
Switching Waveforms Characteristics Read Operations
Read Operations Timings
Hardware Data Protection
Write Inhibit Write Pulse Glitch Protection Logical Inhibit Power-Up Write Inhibit
Erase/Program Operations
Program Operation Timings Chip/Sector Erase Operation Timings Data# Polling Timings (During Embedded Algorithms) Toggle Timings (During Embedded Algorithms) DQ6. Sector Unlock Sequence Timing Diagram Sector Relock Timing Diagram Sector Protect/Unprotect Timing Diagram
Command Definitions Reading Array Data Reset Command Autoselect Command Sequence Byte Program Command Sequence
Program Operation
Alternate Controlled Erase/Program Operations
Alternate Controlled Write Operation Timings
Chip Erase Command Sequence Sector Erase Command Sequence
Erase Operation
Erase Suspend/Erase Resume Commands
Am29F004B Command Definitions
Write Operation Status DQ7: Data# Polling
Data# Polling Algorithm
Erase Programming Performance Latchup Characteristics PLCC Capacitance Data Retention Physical Dimensions 032-32-Pin Plastic Leaded Chip Carrier Revision Summary
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PRODUCT SELECTOR GUIDE
Family Part Number Speed Option access time, (tACC) access time, (tCE) access time, (tOE) Note: Characteristics" full specifications. Am29F004B
BLOCK DIAGRAM
DQ0-DQ7
Sector Switches Erase Voltage Generator
Input/Output Buffers
State Control Command Register Voltage Generator Chip Enable Output Enable Logic Data Latch
Address Latch
Y-Decoder
Y-Gating
Detector
Timer
X-Decoder
Cell Matrix
A0-A18
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CONNECTION DIAGRAMS
PLCC
Standard 48-Pin TSOP
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CONFIGURATION
A0-A18 addresses DQ0-DQ7 data inputs/outputs Chip enable Output enable Write enable +5.0 single power supply (see Product Selector Guide device speed ratings voltage supply tolerances) Device ground connected internally
LOGIC SYMBOL
A0-A18 DQ0-DQ7
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ORDERING INFORMATION Standard Product
standard products available several packages operating ranges. order number (Valid Combination) formed combination elements below.
Am29F004B
TEMPERATURE RANGE Industrial (-40°C +85°C) Industrial (-40°C +85°C) Pb-free package Extended (-55°C +125°C) Extended (-55°C +125°C) Pb-free package PACKAGE TYPE 32-Pin Rectangular Plastic Leaded Chip Carrier 032) SPEED OPTION Product Selector Guide Valid Combinations BOOT CODE SECTOR ARCHITECTURE sector Bottom sector
DEVICE NUMBER/DESCRIPTION Am29F004B Megabit (512 8-Bit) CMOS Flash Memory Volt-only Program Erase
Valid Combinations AM29F004BT-70 AM29F004BB-70 AM29F004BT-90 AM29F004BB-90
Voltage
Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Valid Combinations
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DEVICE OPERATIONS
This section describes requirements device operations, which initiated through internal command register. command register itself does occupy addressable memory location. register composed latches that store commands, along with address data information needed execute command. contents register serve inputs internal state machine. state machine outputs dictate function device. appropriate device operations table lists inputs control levels required, resulting output. following subsections describe each these operations further detail.
Table Am29F004B Device Operations
Operation Read Write CMOS Standby Standby Output Disable Temporary Sector Unprotect (See Note) A0-A18 DQ0-DQ7 DOUT High-Z High-Z High-Z
Legend:
Logic VIL, Logic High VIH, 12.0 Don't Care, Data DOUT Data Out, Address Note: sections Sector Protection Temporary Sector Unprotect more information.
Requirements Reading Array Data
read array data from outputs, system must drive pins VIL. power control selects device. output control gates array data output pins. should remain VIH. internal state machine reading array data upon device power-up. This ensures that spurious alteration memory content occurs during power transition. command necessary this mode obtain array data. Standard microprocessor read cycles that assert valid addresses device address inputs produce valid data device data outputs. device remains enabled read access until command register contents altered. Reading Array Data page more information. Refer Read Operations table timing specifications Read Operations Timings diagram timing waveforms. ICC1 Characteristics table represents active current specification reading array data.
separate from memory array) DQ7-DQ0. Standard read cycle timings apply this mode. Refer Autoselect Mode page Autoselect Command Sequence sections more information. ICC2 Characteristics table represents active curren speci mode Characteristics page section contains timing specification tables timing diagrams write operations.
Program Erase Operation Status
During erase program operation, system check status operation reading status bits DQ7- DQ0. Standard read cycle timings read specifications apply. Refer Write Operation Status page more information, each Characteristics section timing diagrams.
Standby Mode
When system reading writing device, place device standby mode. this mode, current consumption greatly reduced, outputs placed high impedance state, independent input. device enters CMOS standby mode when held (Note that this more restricted voltage range than VIH.) device enters standby mode when held VIH. device requires standard access time (tCE) read access when device either these standby modes, before ready read data. device deselected during erasure programming, device draws active current until operation completed. Characteristics tables, ICC3 represents standby current specification.
Writing Commands/Command Sequences
write command command sequence (which includes programming data device erasing sectors memory), system must drive VIL, VIH. erase operation erase sector, multiple sectors, entire device. Sector Address Tables indicate address space that each sector occupies. "sector address" consists address bits required uniquely select sector. Command Definitions page section details erasing sector entire chip, suspending/resuming erase operation. After system writes autoselect command sequence, device enters autoselect mode. system then read autoselect codes from internal register (which
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Output Disable Mode
When input VIH, output from device disabled. output pins placed high impedance state. Table Am29F004B Boot Block Sector Addresses
Sector SA10 Sector Size (Kbytes) Address Range hexadecimal) 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-77FFFh 78000h-79FFFh 7A000h-7BFFFh 7C000h-7FFFFh
Table
Sector SA10
Am29F004B Bottom Boot Block Sector Addresses
Sector Size (Kbytes) Address Range hexadecimal) 00000h-03FFFh 04000h-05FFFh 06000h-07FFFh 08000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh
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sector address must appear appropriate highest order address bits. Refer corresponding Sector Address Tables. Command Definitions table shows remaining address bits that don't care. When necessary bits required, programming equipment then read corresponding identifier code DQ7- DQ0. access autoselect codes in-system, host system issue autoselect command command register, shown Command Definitions table. This method does require VID. Command Definitions page details using autoselect mode.
Autoselect Mode
autoselect mode provides manufacturer device identification, sector protection verification, through identifier codes output DQ7-DQ0. This mode primarily intended programming equipment automatically match device programmed with corresponding programming algorithm. However, autoselect codes also accessed in-system through command register. When using programming equipment, autoselect mode requires address Address pins must shown Autoselect Codes (High Voltage Method) table. addition, when verifying sector protection,
Table Am29F004B Autoselect Codes (High Voltage Method)
(protected) Sector Protection Verification (unprotected)
Description Manufacturer Device Am29F004B (Top Boot Block) Device Am29F004B (Bottom Boot Block)
Logic VIL, Logic High VIH, Sector Address, Don't care.
Sector Protection/Unprotection
hardware sector protection feature disables both program erase operations sector. hardware sector unprotection feature re-enables both program erase operations previously protected sectors. primary method requires only, implemented either in-system programming equipment. Figure page show algorithms Figure page Figure page Figure page show timing diagrams. This method uses standard microprocessor cycle timing addition sector unlock sector relock sequences. sector unprotect, unprotected sectors must first protected prior first sector unprotect write cycle.
alternate method intended only programming equipment required address OE#. This method compatible with programmer routines written earlier volt-only Flash devices. Publication number 22289 contains further details; contact representative request copy. device shipped with sectors unprotected. offers option programming protecting sectors factory prior shipping device through AMD's ExpressFlashService. Contact representative details. possible determine whether sector protected unprotected. Autoselect Mode page details.
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START PLSCNT VID. Write Sector Unlock sequence with command Wait Write address with sector address Sector Protect: Write sector address with Wait Verify Sector Protect: Write sector address with Read from sector address with (requires access time)
START PLSCNT VID. Write Sector Unlock sequence with command Wait Write address with
Protect sectors: indicated portion sector protect algorithm must performed unprotected sectors prior issuing first sector unprotect address
sectors protected? first sector address Sector Unprotect: Write sector address with
Increment PLSCNT
Reset PLSCNT
Wait Verify Sector Unprotect: Write sector address with Read from sector address with (requires access time) Data 00h? Last sector verified?
Increment PLSCNT
PLSCNT
Data 01h?
Device failed
Protect another sector?
next sector address
PLSCNT 1000?
VID. Write Sector Relock sequence. VIH.
Device failed
Sector Protect Algorithm
Sector Protect complete
Sector Unprotect Algorithm
VID. Write Sector Relock sequence. VIH.
Sector Unprotect complete
Figure
In-System Sector Protect/Sector Unprotect Algorithms
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Temporary Sector Unprotect
This feature allows temporary unprotection previously protected sectors change data in-system. Sector Unprotect mode activated setting 12.0 Volts (VID). Figure shows algorithm, Figure page Figure page show timing diagrams, this feature. While VID, sector unlock sequence written device. After sector unlock sequence written, taken back VIH. device temporary sector unprotect mode. While this mode, formerly protected sectors programmed erased selecting appropriate sector address during programming erase operations. Either sector erase chip erase operations performed this mode. Byte program operations require only cycles, while sector chip erase operations only require four cycles. Refer Command Definitions table. Exiting temporary sector unprotect mode accomplished either removing from device taking back writing sector relock sequence. After writing sector relock sequence, taken back previously protected sectors protected again.
START
Write three-cycle Unlock sequence with command (Figure
(Note
Perform Erase Program Operations
Write two-cycle Sector Relock sequence (Figure
Temporary Sector Unprotect Completed (Note
Notes: protected sectors unprotected. previously protected sectors protected once again.
Figure Temporary Sector Unprotect Operation
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system must issue reset command re-enable device reading array data goes high, while autoselect mode. Reset Command section, next. also "Requirements Reading Array Data" Device Operations page section more information. Read Operations table provides read parameters, Read Operation Timings diagram shows timing diagram.
Hardware Data Protection
command sequence requirement unlock cycles programming erasing provides data protection against inadvertent writes (refer Command Definitions table). addition, following hardware data protection measures prevent accidental erasure programming, which might otherwise caused spurious system level signals during power-up power-down transitions, from system noise.
Write Inhibit
When less than VLKO, device does accept write cycles. This protects data during power-up power-down. command register internal program/erase circuits disabled, device resets. Subsequent writes ignored until greater than VLKO. system must provide proper signals control pins prevent unintentional writes when greater than VLKO.
Reset Command
Writing reset command device resets device reading array data. Address bits don't care this command. reset command written between sequence cycles erase command sequence before erasing begins. This resets device reading array data. Once erasure begins, however, device ignores reset commands until operation complete. reset command written between sequence cycles program command sequence before programming begins. This resets device reading array data (also applies programming Erase Suspend mode). Once programming begins, however, device ignores reset commands until operation complete. reset command written between sequence cycles autoselect command sequence. Once autoselect mode, reset command must written return reading array data (also applies autoselect during Erase Suspend). goes high during program erase operation, writing reset command returns device reading array data (also applies during Erase Suspend).
Write Pulse Glitch Protection
Noise pulses less than (typical) OE#, initiate write cycle.
Logical Inhibit
Write cycles inhibited holding VIL, VIH. initiate write cycle, must logical zero while logical one.
Power-Up Write Inhibit
during power device does accept commands rising edge WE#. internal state machine automatically reset reading array data power-up.
COMMAND DEFINITIONS
Writing specific address data commands sequences into command register initiates device operations. Command Definitions table defines valid register command sequences. Writing incorrect address data values writing them improper sequence resets device reading array data. addresses latched falling edge CE#, whichever happens later. data latched rising edge CE#, whichever happens first. Refer appropriate timing diagrams Characteristics page
Autoselect Command Sequence
autoselect command sequence allows host system access manufacturer devices codes, determine whether sector protected. Command Definitions table shows address data requirements. This method alternative that shown Autoselect Codes (High Voltage Method) table, which intended PROM programmers requires address autoselect command sequence initiated writing unlock cycles, followed autoselect command. device then enters autoselect mode, system read address number times, without initiating another command sequence. read cycle address XX00h retrieves manufacturer code. read cycle address XX01h returns device code. read cycle containing sector address (SA) address returns that sector protected, unprotected. Refer Sector Address tables valid sector addresses. system must write reset command exit autoselect mode return reading array data.
Reading Array Data
device automatically reading array data after device power-up. commands required retrieve data. device also ready read array data after completing Embedded Program Embedded Erase algorithm. After device accepts Erase Suspend command, device enters Erase Suspend mode. system read array data using standard read timings, except that reads address within erase-suspended sectors, device outputs status data. After completing programming operation Erase Suspend mode, system once again read array data with same exception. Reset Command more information this mode.
Byte Program Command Sequence
Programming four-bus-cycle operation. program command sequence initiated writing unlock write
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cycles, followed program set-up command. program address data written next, which turn initiate Embedded Program algorithm. system required provide further controls timings. device automatically provides internally generated program pulses verify programmed cell margin. (Note that device temporary sector unprotect mode, byte program command sequence only requires cycles.) Command Definitions table shows address data requirements byte program command sequence. When Embedded Program algorithm complete, device then returns reading array data addresses longer latched. system determine status program operation using DQ6. Write Operation Status page information these status bits. commands written device during Embedded Program Algorithm ignored. Sector Erase command sequence should reinitiated once device returns reading array data, ensure data integrity. Programming allowed sequence across sector boundaries. cannot programmed from back Attempting halt operation cause Data# Polling algorithm indicate operation successful. However, succeeding read shows that data still Only erase operations convert
Chip Erase Command Sequence
Chip erase six-bus-cycle operation. chip erase command sequence initiated writing unlock cycles, followed set-up command. additional unlock write cycles then followed chip erase command, which turn invokes Embedded Erase algorithm. device does require system preprogram prior erase. Embedded Erase algorithm automatically preprograms verifies entire memory zero data pattern prior electrical erase. system required provide controls timings during these operations. (Note that device temporary sector unprotect mode, chip erase command sequence only requires four cycles.) Command Definitions table shows address data requirements chip erase command sequence. commands written chip during Embedded Erase algorithm ignored. Sector Erase command sequence should reinitiated once device returns reading array data, ensure data integrity. system determine status erase operation using DQ7, DQ6, DQ2. Write Operation Status page information these status bits. When Embedded Erase algorithm complete, device returns reading array data addresses longer latched. Figure page illustrates algorithm erase operation. Erase/Program Operations page parameters, Figure page timing waveforms.
START
Sector Erase Command Sequence
Sector erase six-bus-cycle operation. sector erase command sequence initiated writing unlock cycles, followed set-up command. additional unlock write cycles then followed address sector erased, sector erase command. (Note that device temporary sector unprotect mode, sector erase command sequence only requires four cycles.) Command Definitions table shows address data requirements sector erase command sequence. device does require system preprogram memory prior erase. Embedded Erase algorithm automatically programs verifies sector zero data pattern prior electrical erase. system required provide controls timings during these operations. After command sequence written, sector erase timeout begins. During time-out period, additional sector addresses sector erase commands written. Loading sector erase buffer done sequence, number sectors from sector sectors. time between these additional cycles must less than otherwise last address command might accepted, erasure begin. recommended that processor interrupts disabled during this time ensure commands accepted. interrupts re-enabled after last Sector Erase command written. time between additional sector erase commands assumed less than system need monitor DQ3. command other than Sector Erase Erase Suspend during time-out period resets device reading array data. system must rewrite command
Write Program Command Sequence
Embedded Program algorithm progress
Data Poll from System
Verify Data?
Increment Address
Last Address?
Programming Completed
Note: appropriate Command Definitions table program command sequence.
Figure
Program Operation
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sequence additional sector addresses commands. system monitor determine sector erase timer timed out. (See DQ3: Sector Erase Timer page 18.) time-out begins from rising edge final pulse command sequence. Once sector erase operation begins, only Erase Suspend command valid. other commands ignored. Sector Erase command sequence should reinitiated once device returns reading array data, ensure data integrity. When Embedded Erase algorithm complete, device returns reading array data addresses longer latched. system determine status erase operation using DQ7, DQ6, DQ2. Refer Write Operation Status page information these status bits. Figure illustrates algorithm erase operation. Refer Erase/Program Operations page parameters, Sector Erase Operations Timing diagram timing waveforms.
Erase Suspend/Erase Resume Commands
Erase Suspend command allows system interrupt sector erase operation then read data from, program data sector selected erasure. This command valid only during sector erase operation, including time-out period during sector erase command sequence. Erase Suspend command ignored written during chip erase operation Embedded Program algorithm. Writing Erase Suspend command during Sector Erase time-out immediately terminates time-out period suspends erase operation. Addresses don't-cares when writing Erase Suspend command. When Erase Suspend command written during sector erase operation, device requires maximum suspend erase operation. However, when Erase Suspend command written during sector erase timeout, device immediately terminates time-out period suspends erase operation. After erase operation suspended, system read array data from program data sector selected erasure. (The device "erase suspends" sectors selected erasure.) Normal read write timings command definitions apply. Reading address within erase-suspended sectors produces status data DQ7-DQ0. system DQ7, together, determine sector actively erasing erase-suspended. Write Operation Status page information these status bits. After erase-suspended program operation complete, system once again read array data within non-suspended sectors. system determine status program operation using status bits, just standard program operation. Write Operation Status page more information.
START
Write Erase Command Sequence
Data Poll from System
Embedded Erase algorithm progress
Data FFh?
Erasure Completed
system also write autoselect command sequence when device Erase Suspend mode. device allows reading autoselect codes even addresses within erasing sectors, since codes stored memory array. When device exits autoselect mode, device reverts Erase Suspend mode, ready another valid operation. Autoselect Command Sequence page more information. system must write Erase Resume command (address bits don't care) exit erase suspend mode continue sector erase operation. Further writes Resume command ignored. Another Erase Suspend command written after device resumes erasing.
Note: appropriate Command Definitions table erase command sequence. DQ3: Sector Erase Timer page more information.
Figure Erase Operation
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Table
Command Sequence (Note Read (Note Reset (Note Manufacturer Device Boot Block Autoselect (Note Device Bottom Boot Block Sector Protect Verify (Note Program Chip Erase Sector Erase Erase Suspend (Note Erase Resume (Note Temporary Sector Unprotect Mode (Note Enter Mode Program Sector Erase Chip Erase Cycles First Addr
Am29F004B Command Definitions
Cycles (Notes 2-4) Second Addr Data Data programmed location Data latches rising edge pulse, whichever happens first. Address sector verified autoselect mode) erased. Address bits A18-A13 uniquely select sector. sector address must asserted combination with (for protect) (for unprotect). (SA) Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data Data
Sector Unlock (Note Sector Relock (Notes Legend: Don't care
Address memory location read. Data read from location during read operation. Address memory location programmed. Addresses latch falling edge pulse, whichever happens later. Notes: Table description operations. values hexadecimal. Except when reading array autoselect data, cycles write operations. Address bits A18-A11 don't cares unlock command cycles, except when required. unlock command cycles required when reading array data. Reset command required return reading array data when device autoselect mode, goes high (while device providing status data). fourth cycle autoselect command sequence read cycle.
data unprotected sector protected sector. Autoselect Command Sequence page more information. activate sequence, must VID. sector relock command second cycle written either F0h. system read program non-erasing sectors, enter autoselect mode, when Erase Suspend mode. Erase Suspend command valid only during sector erase operation. Erase Resume command valid only during Erase Suspend mode.
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WRITE OPERATION STATUS
device provides several bits determine status write operation: DQ2, DQ3, DQ5, DQ6, DQ7. Table page following subsections describe functions these bits. each offer method determining whether program erase operation complete progress. These three bits discussed first.
START
Read DQ7-DQ0 Addr
DQ7: Data# Polling
Data# Polling bit, DQ7, indicates host system whether Embedded Algorithm progress completed, whether device Erase Suspend. Data# Polling valid after rising edge final pulse program erase command sequence. During Embedded Program algorithm, device outputs complement datum programmed DQ7. This status also applies programming during Erase Suspend. When Embedded Program algorithm complete, device outputs datum programmed DQ7. system must provide program address read valid status information DQ7. program address falls within prot approximately then device returns reading array data. During Embedded Erase algorithm, Data# Polling produces DQ7. When Embedded Erase algorithm complete, device enters Erase Suspend mode, Data# Polling produces DQ7. This analogous complement/true datum output described Embedded Program algorithm: erase function changes bits sector "1"; prior this, device outputs "complement," "0." system must provide address within sectors selected erasure read valid status information DQ7. After erase command sequence written, sectors selected erasing protected, Data# Polling active approximately then device returns reading array data. selected sectors protected, Embedded Erase algorithm erases unprotected sectors, ignores selected sectors that protected. When system detects changes from complement true data, read valid data DQ7-DQ0 following read cycles. This because change asynchronously with DQ0-DQ6 while Output Enable (OE#) asserted low. Data# Polling Timings (During Embedded Algorithms) figure Characteristics page section illustrates this. Table page shows outputs Data# Polling DQ7. Figure page shows Data# Polling algorithm.
Data?
Read DQ7-DQ0 Addr
Data?
FAIL PASS
Notes: Valid address programming. During sector erase operation, valid address address within sector selected erasure. During chip erase, valid address non-protected sector address. should rechecked even because change simultaneously with DQ5.
Figure Data# Polling Algorithm
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explains algorithm. also DQ6: Toggle page subsection. Refer Toggle Timings figure toggle timing diagram. figure shows differences between graphical form.
DQ6: Toggle
Toggle indicates whether Embedded Program Erase algorithm progress complete, whether device entered Erase Suspend mode. Toggle read address, valid after rising edge final pulse command sequence (prior program erase operation), during sector erase time-out. During Embedded Program Erase algorithm operation, successive read cycles address cause toggle. (The system either control read cycles.) When operation complete, stops toggling. After erase command sequence written, sectors selected erasing protected, toggles approximately then returns reading array data. selected sectors protected, Embedded Erase algorithm erases unprotected sectors, ignores selected sectors that protected. system together determine whether sector actively erasing erase-suspended. When device actively erasing (that Embedded Erase algorithm progress), toggles. When device enters Erase Suspend mode, stops toggling. However, system must also determine which sectors erasing erase-suspended. Alternatively, system (see subsection DQ7: Data# Polling). program address falls within protected sector, toggles approximately after program command sequence written, then returns reading array data. also toggles during erase-suspend-program mode, stops toggling once Embedded Program algorithm complete. Write Operation Status table shows outputs Toggle DQ6. Refer Figure toggle algorithm, Toggle Timings figure Characteristics" section timing diagram. figure shows differences between graphical form. also subsection DQ2: Toggle
Reading Toggle Bits DQ6/DQ2
Refer Figure page following discussion. Whenever system initially begins reading toggle status, must read DQ7-DQ0 least twice determine whether toggle toggling. Typically, system would note store value toggle after first read. After second read, system would compare value toggle with first. toggle toggling, device completed program erase operation. system read array data DQ7-DQ0 following read cycle. However, after initial read cycles, system determines that toggle still toggling, system also should note whether value high (see section DQ5). system should then determine again whether toggle toggling, since toggle have stopped toggling just went high. toggle longer toggling, device successfully completed program erase operation. still toggling, device complete operation successfully, system must write reset command return reading array data. remaining scenario that system initially determines that toggle toggling gone high. system continue monitor toggle through successive read cycles, determining status described previous paragraph. Alternatively, choose perform other system tasks. this case, system must start beginning algorithm when returns determine status operation (top Figure page 19).
DQ5: Exceeded Timing Limits
indicates whether program erase time exceeded specified internal pulse count limit. Under these conditions produces This failure condition that indicates program erase cycle successfully completed. failure condition appear system tries program location that previously programmed Only erase operation change back Under this condition, device halts operation, when operation exceeds timing limits, produces Under both these conditions, system must issue reset command return device reading array data.
DQ2: Toggle
Toggle DQ2, when used with DQ6, indicates whether particular sector actively erasing (that Embedded Erase algorithm progress), whether that sector erase-suspended. Toggle valid after rising edge final pulse command sequence. toggles when system reads addresses within those sectors that were selected erasure. (The system either control read cycles.) cannot distinguish whether sector actively erasing erase-suspended. DQ6, comparison, indicates whether device actively erasing, Erase Suspend, cannot distinguish which sectors selected erasure. Thus, both status bits required sector mode information. Refer Table page compare outputs DQ6. Figure page shows toggle algorithm flowchart form, section DQ2: Toggle page
DQ3: Sector Erase Timer
After writing sector erase command sequence, system read determine whether erase operation started. (The sector erase timer does apply chip erase command.) additional sectors selected erasure, entire time-out also applies after each additional sector erase command. When time-out complete, switches from system ignore system guarantee that time between additional sector
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erase commands always less than also Sector Erase Command Sequence page section.
START
After sector erase command sequence written, system should read status (Data# Polling) (Toggle ensure device accepts command sequence, then read DQ3. internally controlled erase cycle started; further commands (other than Erase Suspend) ignored until erase operation complete. device accepts additional sector erase commands. ensure command accepted, system software should check status prior following each subsequent sector erase command. high second status check, last command might have been accepted. Table page shows outputs DQ3.
Read DQ7-DQ0
Read DQ7-DQ0
(Note
Toggle Toggle?
Read DQ7-DQ0 Twice
(Notes
Toggle Toggle?
Program/Erase Operation Complete, Write Reset Command Program/Erase Operation Complete
Notes: Read toggle twice determine whether toggling. text. Recheck toggle because stop toggling changes text.
Figure Toggle Algorithm
Table
Operation Standard Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend-Program
Write Operation Status
Toggle Toggle toggle Data Toggle (Note Data Data (Note toggle Toggle Toggle Data
(Note DQ7# Data DQ7#
Erase Suspend Mode
Notes: require valid address when reading status information. Refer appropriate subsection further details. switches when Embedded Program Embedded Erase operation exceeded maximum timing limits. DQ5: Exceeded Timing Limits page more information.
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ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages -65°C +150°C Ambient Temperature with Power Applied. -55°C +125°C Voltage with Respect Ground (Note -2.0 +7.0 (Note -2.0 +12.5 other pins (Note -0.5 +7.0 Output Short Circuit Current (Note Figure Maximum Negative Overshoot Waveform
Notes: Minimum voltage input pins -0.5 During voltage transitions, input pins overshoot -2.0 periods Figure page Maximum voltage input pins +0.5 During voltage transitions, input pins overshoot +2.0 periods Figure page Minimum input voltage pins -0.5 During voltage transitions, overshoot -2.0 periods Figure page Maximum input voltage +12.5 which overshoot +13.5 periods more than output shorted ground time. Duration short circuit should greater than second. Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational sections this data sheet implied. Exposure device absolute maximum rating conditions extended periods affect device reliability. +2.0 +0.5 +0.8 -0.5 -2.0
Figure Maximum Positive Overshoot Waveform
OPERATING RANGES
Industrial Devices
Ambient Temperature (TA) -40°C +85°C
Extended Devices
Ambient Temperature (TA) -55°C +125°C
Supply Voltages
devices .+4.75 +5.25 devices .+4.5 +5.5 Operating ranges define those limits between which functionality device guaranteed.
Am29F004B
Am29F004B_00_E4 2006
CHARACTERISTICS TTL/NMOS Compatible
Parameter ILIT ICC1 ICC2 ICC3 VLKO Description Input Load Current Input Load Current (Note Output Leakage Current Active Read Current (Notes Active Write Current (Notes Standby Current (Note Input Voltage Input High Voltage Voltage Autoselect Temporary Sector Unprotect Output Voltage Output High Voltage Lock-Out Voltage -2.5 Test Conditions VCC, max; 12.5 VOUT VCC, VIL, VIL, CE#, -0.5 11.5 ±1.0 ±1.0 12.5 0.45 Unit
Notes: Maximum specifications tested with VCCmax. current listed typically less than mA/MHz, with VIH.
active while Embedded Erase Embedded Program progress. 100% tested.
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CHARACTERISTICS CMOS Compatible
Parameter ILIT ICC1 ICC2 ICC3 VOH1 VOH2 VLKO Lock-Out Voltage Description Input Load Current OE#, Input Load Current (Note Output Leakage Current Active Read Current (Notes Active Write Current (Notes Standby Current (Notes Input Voltage Input High Voltage Voltage Autoselect Temporary Sector Unprotect Output Voltage Output High Voltage -2.5 -100 0.85 VCC-0.4 Test Conditions VCC, max; 12.5 VOUT VCC, VIL, VIL, -0.5 11.5 ±1.0 ±1.0 12.5 0.45 Unit
Notes: Maximum specifications tested with VCCmax. current listed typically less than mA/MHz, with VIH.
active while Embedded Erase Embedded Program progress. 100% tested. ICC3 extended temperature (>+85°
Am29F004B
Am29F004B_00_E4 2006
TEST CONDITIONS
Table Test Specifications
Test Condition Device Under Test Output Load Output Load Capacitance, (including capacitance) Input Rise Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 0.45-2.4 0.8, 0.8, Unit gate
Note: Diodes IN3064 equivalent
Figure
Test Setup
SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady OUTPUTS
Changing from
Changing from
Don't Care, Change Permitted
Changing, State Unknown
Does Apply
Center Line High Impedance State (High
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CHARACTERISTICS Read Operations
Parameter JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tACC Description Read Cycle Time (Note Address Output Delay Chip Enable Output Delay Output Enable Output Delay Chip Enable Output High (Note Output Enable Output High (Note Output Enable Hold Time (Note Read Toggle Data# Polling Test Setup Speed Options Unit
tOEH
tAXQX
Output Hold Time From Addresses, OE#, Whichever Occurs First (Note
Notes: 100% tested. Table Figure page test specifications.
Addresses tOEH HIGH Outputs Output Valid HIGH Addresses Stable tACC
Figure Read Operations Timings
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CHARACTERISTICS Erase/Program Operations
Parameter JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX tOES tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 tGHWL tWPH tWHWH1 tWHWH2 tVCS Notes: 100% tested. Erase Programming Performance page more information. Description Write Cycle Time (Note Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write (OE# High Low) Setup Time Hold Time Write Pulse Width Write Pulse Width High Programming Operation (Note Sector Erase Operation (Note Setup Time (Note Speed Options Unit
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CHARACTERISTICS
Program Command Sequence (last cycles) Addresses 555h Data Status DOUT tWPH tWHWH1 Read Status Data (last cycles)
tVCS
Notes: program address, program data, DOUT true data program address.
Figure Program Operation Timings
Erase Command Sequence (last cycles) Addresses 2AAh
555h chip erase
Read Status Data
tWPH
tWHWH2
Data tVCS
Notes: sector address (for Sector Erase), Valid Address reading status data ("see Write Operation Status page 17).
Chip Erase
Progress
Complete
Figure Chip/Sector Erase Operation Timings
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CHARACTERISTICS
Addresses tACC tOEH
High
Complement
Complement
True
Valid Data
High
DQ0-DQ6
Status Data
Status Data
True
Valid Data
Note: Valid address. Illustration shows first status cycle after command sequence, last status read cycle, array data read cycle.
Figure Data# Polling Timings (During Embedded Algorithms)
Addresses tACC tOEH DQ6/DQ2
High
Valid Status (first read)
Valid Status (second read)
Valid Status (stops toggling)
Valid Data
Note: Valid address; required DQ6. Illustration shows first status cycle after command sequence, last status read cycle, array data read cycle.
Figure Toggle Timings (During Embedded Algorithms)
Enter Embedded Erasing
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
Note: system toggle DQ6. toggles only when read address within erase-suspended sector.
Figure
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CHARACTERISTICS
Parameter JEDEC Std. tVIDR
VSS,
tVIDR
Description Rise Fall Time (Not 100% tested)
Speed Options
Unit
555h
2AAh
555h
20h/24h
Device ready read from array.
written, Sector Unprotect mode enabled. written, command mode Sector Protect/Unprotect enabled.
Figure
Sector Unlock Sequence Timing Diagram
VSS,
tVIDR tVIDR
XXXh
XXXh
Device either Temporary Sector Unprotect mode command mode Sector Protect/Unprotect. Device exits Temporary Sector Unprotect mode command mode Sector Protect/Unprotect. Returns reading array data.
Figure
Sector Relock Timing Diagram
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CHARACTERISTICS
XXXh
Valid (Note
Valid (Note
Array Data
Sector Unlock sequence (three cycles)
Notes: enable command mode sector protection/unprotection algorithm, system must issue command sector unlock sequence. sector protection, valid address consists sector address with sector
Sector Relock sequence (two cycles)
unprotection, valid address consists sector address with
Figure Sector Protect/Unprotect Timing Diagram
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CHARACTERISTICS Alternate Controlled Erase/Program Operations
Parameter JEDEC tAVAV tAVEL tELAX tDVEH tEHDX Std. tOES tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2 tGHEL tCPH tWHWH1 tWHWH2 Description Write Cycle Time (Note Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write (OE# High Low) Setup Time Hold Time Pulse Width Pulse Width High Programming Operation (Note Sector Erase Operation (Note Speed Options Unit
100% tested. Erase Programming Performance page more information.
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Am29F004B_00_E4 2006
CHARACTERISTICS
program erase program sector erase chip erase
Data# Polling
Addresses tGHEL tCPH Data
program erase program sector erase chip erase
tWHWH1
DQ7#
DOUT
Notes: Program Address, Program Data, DQ7# complement data written device, DOUT data written device. Figure indicates last cycles command sequence.
Figure Alternate Controlled Write Operation Timings
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ERASE PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time (Note (Note 10.8 (Note Unit Comments Excludes programming prior erasure (Note Excludes system level overhead (Note
Notes: Typical program erase times assume following conditions: 25°C, VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. Under worst case conditions 90°C, (4.75 devices), 1,000,000 cycles. typical chip programming time considerably less than maximum chip programming time listed, since most bytes program faster than maximum program times listed. pre-programming step Embedded Erase algorithm, bytes programmed before erasure. System-level overhead time required execute four-bus-cycle sequence program command. Table further information command definitions. device minimum guaranteed erase program cycle endurance 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description Input voltage with respect pins except pins (including OE#) Input voltage with respect pins Current Note: Includes pins except VCC. Test conditions: time. -1.0 -1.0 -100 12.5 +100
PLCC CAPACITANCE
Parameter Symbol COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Capacitance VOUT Test Conditions Unit
Notes:
Sampled, 100% tested. Test conditions 25°C, MHz.
DATA RETENTION
Parameter Minimum Pattern Data Retention Time 125°C Years Test Conditions 150°C Unit Years
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PHYSICAL DIMENSIONS 032-32-Pin Plastic Leaded Chip Carrier
10/99
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sector protect unprotect algorithm requires access time
REVISION SUMMARY Revision (January 1999)
Initial release.
Revision (November 1999)
Characteristics-Figure Program Operations Timing Figure Chip/Sector Erase Operations
Deleted tGHWL changed waveform start high.
Revision (March 1999)
Global
Revised document into full data sheet.
Physical Dimensions
Revision (March 1999)
In-System Sector Protect/Sector Unprotect Algorithms figure
Added requirements asserting address setting during both algorithms.
Replaced figures with more detailed illustrations.
Revision (February 2000)
Global
"preliminary" designation removed from document. Parameters stable, only speed, package, temperature range combinations expected change future data sheet revisions.
Command Definitions table
Added requirement definition legend. fourth cycle Sector Relock sequence, changed address from SA+.
Revision (November 2000)
Added table contents.
Sector Protect/Unprotect Timing Diagram
Modified drawing indicate that should dropped during third cycle.
Ordering Information
Deleted burn-in option.
Revision (May 1999)
Ordering Information
Changed temperature range example
Table Command Definitions
Note corrected lower address don't care range A11.
Device Operation table
Corrected highest address range column header A18.
Revision (March 2005)
Global
Added Colophon Updated Trademark
Command Definitions table
Note changed address range bits that don't care A18-A12.
Ordering Information
Added Pb-free temperature ranges Industrial Extended packaging Added Valid Combination Codes
Characteristics table
Note deleted reference ICC4.
Read Operations Timings Alternate Controlled Write Operations figures
Deleted RESET# waveform.
Revision (July 2005)
Global
Removed information from Datasheet.
Revision (July 1999)
Global
Deleted references PDIP package. Changed data sheet status Preliminary.
Revision (December 2005)
Global
Eliminated speed option from entire document.
In-System Sector Protect/Unprotect Algorithms figure
Added tolerance specifications waits. Clarified that reading from sector address during either
Revision (May 2006)
Added "Not recommended designs" note.
Am29F004B
Am29F004B_00_E4 2006
Colophon products described this document designed, developed manufactured contemplated general use, including without limitation, ordinary industrial use, general office use, personal use, household use, designed, developed manufactured contemplated that includes fatal risks dangers that, unless extremely high safety secured, could have serious effect public, could lead directly death, personal injury, severe physical damage other loss (i.e., nuclear reaction control nuclear facility, aircraft flight control, traffic control, mass transport control, medical life support system, missile launch control weapon system), where chance failure intolerable (i.e., submersible repeater artificial satellite). Please note that Spansion will liable and/or third party claims damages arising connection with above-mentioned uses products. semiconductor devices have inherent chance failure. must protect against injury, damage loss from such failures incorporating safety design measures into your facility equipment such redundancy, fire protection, prevention over-current levels other abnormal operating conditions. products described this document represent goods technologies subject certain restrictions export under Foreign Exchange Foreign Trade Japan, Export Administration Regulations applicable laws other country, prior authorization respective government entity will required export those products. Trademarks Copyright 2000-2006 Advanced Micro Devices, Inc. rights reserved. AMD, logo, combinations thereof registered trademarks Advanced Micro Devices, Inc. ExpressFlash trademark Advanced Micro Devices, Inc. Product names used this publication identification purposes only trademarks their respective companies.
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Am29F004B

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